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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 235 records · Page 13

Extended Characterization of the Common-Source and Common-Gate Amplifiers using a Metal-Ferroelectric-Semiconductor Field Effect Transistor

Collected data for both common-source and common-gate amplifiers is presented in this paper. Characterizations of the two amplifier circuits using metal-ferroelectric-semiconductor field effect transistors (MFSFETs) are developed with wider input frequency ranges and varying device sizes compared to earlier characterizations. The effects of the ferroelectric layer's capacitance and variation load, quiescent point, or input signal on each circuit are discussed. Comparisons between the MFSFET and MOSFET circuit operation and performance are discussed at length as well as applications and advantages for the MFSFETs.

Hunt, Mitchell↗

Load power device and system for real-time execution of hierarchical load identification algorithms

A load power device includes a power input; at least one power output for at least one load; and a plurality of sensors structured to sense voltage and current at the at least one power output. A processor is structured to provide real-time execution of: (a) a plurality of load identification algorithms, and (b) event detection and operating mode detection for the at least one load.

24 POWER TRANSMISSION AND DISTRIBUTION↗

Load power device, system and method of load control and management employing load identification

A load power device includes a power input, at least one power output for at least one load, a plurality of sensors structured to sense voltage and current at the at least one power output, and a processor. The processor provides: (a) load identification based upon the sensed voltage and current, and (b) load control and management based upon the load identification.

24 POWER TRANSMISSION AND DISTRIBUTION↗

FETSIM user's manual and example

A batch program written in FORTRAN IV which does D.C. and transient analysis of MOS circuits is presented. Circuits employing N-MOS transistors and/or P-MOS transistors in either a bulk technology or an SOS technology, or almost any combination of R-C elements may be analyzed. The program requires as input data the complete circuit topology, device parameters, process parameters, and control parameters. The user can specify initial node conditions and the input pulse format. For example, pulse rise time, fall time, width and time between succeeding pulses are all independently controllable. The program contains a sophisticated mathematical model that can accurately handle either NMOS, P-MOS, Bulk or SOS devices. Sensitivity to process changes is maintained by requiring such process parameters as threshold voltage and doping level as program inputs.

Source record↗

Analog to digital converter for two-dimensional radiant energy array computers

The analog to digital converter stage derives a bit array of digital radiant energy signals representative of the amplitudes of an input radiant energy analog signal array and derives an output radiant energy analog signal array to serve as an input to succeeding stages. The converter stage includes a digital radiant energy array device which contains radiant energy array positions so that the analog array is less than a predetermined threshold level. A scaling device amplifies the radiant signal levels of the input array and the digital array so that the radiant energy signal level carried by the digital array corresponds to the threshold level. An adder device adds the signals of the scaled input and digital arrays at corresponding array positions to form the output analog array.

Shaefer, D. H.↗

Defining and Characterizing Methods, Tools, and Computing Resources to Support Pseudo Exhaustive Testability of Software Based I&C Devices

Under the Department of Energy’s Light Water Reactor Sustainability Program, within the Plant Modernization research pathway, the Digital I&C Qualification Project is identifying new methods that would be beneficial in qualifying digital I&C systems and devices for safety-related usage. One such method that would be useful in qualifying field components such as sensors and actuators is the concept of testability. The Nuclear Regulatory Commission (NRC) considers testability to be one of two design attributes sufficient to eliminate consideration of software-based or software logic-based common cause failure (the other being diversity). The NRC defines acceptable “testability” as follows: Testability – A system is sufficiently simple such that every possible combination of inputs and every possible sequence of device states are tested and all outputs are verified for every case (100% tested). [NUREG 0800, Chapter 7, Branch Technical Position (BTP) 7-19] This qualification method has never proven to be practical in view of the very large number of combinations of inputs and sequences of device states for a typical I&C device. However, many of these combinations are not unique in the sense that they represent the same state space or in that that they represent state space that would not affect the critical design basis functions of the device. Therefore, the state space of interest might possibly be reduced to a manageable dimension through such analysis. This project focuses on a representative I&C device similar in design, function, and complexity to the types of devices that would likely be deployed in nuclear power plants as digital or software based sensors and actuators (e.g. Smart Sensors). Analysis will be conducted to determine the feasibility of testing this device in a manner consistent with the NRC definition. This report describes acceptable test methods, needed tools (existing or new), and computing resources, all based on engineering and computer science principles. This information will then be used in a later phase of this project to develop a test specification for I&C device testability that can be used in a future phase of this project to demonstrate digital qualification with respect to common cause failure. Following that, testing will be conducted and the results analyzed to determine if the methods employed are sufficient to eliminate consideration of software common cause failure in accordance with the concept of testability.

22 GENERAL STUDIES OF NUCLEAR REACTORS↗

REALIZATION OF A AUTOMATED T-WAY COMBINATORIAL TESTING APPROACH FOR A SOFTWARE BASED EMBEDDED DIGITAL DEVICE

Under the Department of Energy’s Light Water Reactor Sustainability Program, within the Plant Modernization research pathway, the Digital I&C Qualification Project is identifying new methods that would be beneficial in qualifying digital I&C systems and devices for safety-related usage. One such method that would be useful in qualifying field components such as sensors and actuators is the concept of testability. The Nuclear Regulatory Commission (NRC) considers testability to be one of two design attributes sufficient to eliminate consideration of software-based or software logic-based common cause failure (the other being diversity). The NRC defines acceptable “testability” as follows: Testability – A system is sufficiently simple such that every possible combination of inputs and every possible sequence of device states are tested and all outputs are verified for every case (100% tested). [NUREG 0800, Chapter 7, Branch Technical Position (BTP) 7-19] This qualification method has never proven to be practical in view of the very large number of combinations of inputs and sequences of device states for a typical I&C device. However, many of these combinations are not unique in the sense that they represent the same state space or in that that they represent state space that would not affect the critical design basis functions of the device. Therefore, the state space of interest might possibly be reduced to a manageable dimension through such analysis. This project will focus on a representative I&C device similar in design, function, and complexity to the types of devices that would likely be deployed in nuclear power plants as digital or software based sensors and actuators (e.g. Smart Sensors). Analysis will be conducted to determine the feasibility of testing this device in a manner consistent with the NRC definition. This report describes the development of test process for Bounded Exhaustive Testing with respect to Combinatorial Test (CT) methods. The report describes the candidate Device Under Test SW – the VCU smart sensor, conceptual experimental methods for stated test objectives, description of the process, tools, resources, and computing. This information will be used to fully develop a detailed test plan (based on statistical measure needs) and test environment for conducting an I&C device testability demonstration study. The future planed experimental study of this project is to demonstrate digital qualification via Bounded Exhaustive Testability with respect to Common Cause Failure.

22 GENERAL STUDIES OF NUCLEAR REACTORS↗

High Input Voltage Discharge Supply for High Power Hall Thrusters Using Silicon Carbide Devices

A power processing unit for a 15 kW Hall thruster is under development at NASA Glenn Research Center. The unit produces up to 400 VDC with two parallel 7.5 kW discharge modules that operate from a 300 VDC nominal input voltage. Silicon carbide MOSFETs and diodes were used in this design because they were the best choice to handle the high voltage stress while delivering high efficiency and low specific mass. Efficiencies in excess of 97 percent were demonstrated during integration testing with the NASA-300M 20 kW Hall thruster. Electromagnet, cathode keeper, and heater supplies were also developed and will be integrated with the discharge supply into a vacuum-rated brassboard power processing unit with full flight functionality. This design could be evolved into a flight unit for future missions that requires high power electric propulsion.

Electric Propulsion↗

Push-pull circuit with driving assisted by asymmetric charge sharing

A push-pull circuit for an opto-electronic device includes: an output node; a pull-up circuit that, in operation, controls a falling edge rate of an input signal to the opto-electronic device while sharing charge with the output node; and a pull-down circuit that, in operation, controls a rising edge rate of the input signal to the opto-electronic device while sharing charge with the output node.

Zhu, Zhubiao↗

Inner loop flight control for the High-Speed Civil Transport

High-speed aerospace vehicles which employ high strength, light weight, yet deformable materials may exhibit significant interaction between the rigid-body and vibrational dynamics. Preliminary High-Speed Civil Transport (HSCT) configurations are a prime example. Traditionally, separate control systems have been used to augment the rigid-body and vibrational dynamics. In the HSCT arena, the highly coupled motions may not allow this design freedom. The research activity addresses two specific issues associated with the design and development of an integrated flight control system (FCS) for HSCT configurations, which are discussed next. The HSCT is expected to have a short period instability at subsonic speeds. Flight vehicles with this characteristic (i.e., F-16, F-22, X-29, Space Shuttle) are stabilized with what is called a superaugmented pitch rate loop. One concern is 'Will this stability augmentation logic work for a HSCT?' Studies show that an idealized pitch rate design would be acceptable, but is not realistic. Investigations using a contaminated pitch rate design reveal serious hurdles to overcome in the FCS design. Mounting location for the pitch rate sensor is critical. Results indicate a forward location leads to destabilizing pick-up of aeroelastic modes, while aft locations lead to undesirable coupling of the dominate pitch mode with the first aeroelastic mode. Intermediate locations for the sensor may not be acceptable. The source of the problem is the presence of low frequency aeroelastic modes in HSCT configurations, which are not present in vehicles currently using the superaugmented logic. To say the least, a conventional superaugmented pitch rate loop strategy may have undesirable characteristics. An unconventional strategy, which attempts to eliminate the above deficiencies by blending several pitch rate signals, indicates an improvement in the FCS architecture feasibility, but is still lacking in some respects. The HSCT configuration does not have aerodynamic surfaces in the vicinity of the nose (i.e., no canard or vane). A second concern is 'Can the fuselage bending/torsion aeroelastic modes be effectively augmented without sufficient control input near the vehicle nose?' The superaugmented FCS results above may be suggesting the necessity of a secondary feedback loop to achieve an acceptable integrated FCS. Preliminary analysis of HSCT aeroelastic mode shapes indicate the use of existing wing leading edge devices as a second control input may be lacking in control authority for the rigid-body attitude and aeroelastic modes. An effort is underway to incorporate generic wing leading edge devices and canards into a generic HSCT model for the purpose of assessing additional control authority and it's use in candidate FCS designs. A generic HSCT mathematical model was necessary for the studies above. A HSCT category model is available in NASA-CR-172201. This model describes the linear, longitudinal dynamics about the following flight condition: ascent, W = 730,000 lbs, h = 6,500 ft, M = 0.6. The model incorporates the full rigid-body variable set, as well as eighteen aeroelastic modes. Elevator deflection serves as the control input. Modifications to the model include the incorporation of relaxed static stability (i.e., static margin from -7.3% to +10%) and additional control inputs.

Newman, Brett A.↗

Semiconductor topologies and devices for soft starting and active fault protection of power converters

Various examples are provided related to semiconductor topologies and devices that can be used for soft starting and active fault protection of power converters. In one example, an active switch device includes an active switch having a gating control input; and a thyristor having a gating control input. The thyristor is coupled in parallel with the active switch. The active switch can be an IGBT, MOSFET, or other appropriate device. In another example, a power converter can include the active switch devices and switching control circuitry coupled to gating control inputs of the active switch devices.

Beddingfield, Richard B.↗

Stackable Form-Factor Peripheral Component Interconnect Device and Assembly

A stackable form-factor Peripheral Component Interconnect (PCI) device can be configured as a host controller or a master/target for use on a PCI assembly. PCI device may comprise a multiple-input switch coupled to a PCI bus, a multiplexor coupled to the switch, and a reconfigurable device coupled to one of the switch and multiplexor. The PCI device is configured to support functionality from power-up, and either control function or add-in card function.

Somervill, Kevin M.↗

Building environment data collection systems

Building environment data collection systems and methods are described. According to one aspect, a system includes a plurality of sensor devices which store different types of environment data, a base system comprising a plurality of interface devices configured to receive the environment data from the sensor devices, storage circuitry configured to store the environment data, and communications circuitry configured to implement communications, and a user interface apparatus comprising communications circuitry configured to communicate with the communications circuitry of the base system, a user interface configured to receive user inputs during installation of the sensor devices, and processing circuitry configured to control the user interface to generate the displayed information and to process the user inputs received via the user interface, and wherein different ones of the sensor devices are configured to generate the different types of environment data as a result of the user inputs.

Hughes, Michael A.↗

Assurance of Complex Electronics. What Path Do We Take?

Many of the methods used to develop software bare a close resemblance to Complex Electronics (CE) development. CE are now programmed to perform tasks that were previously handled in software, such as communication protocols. For instance, Field Programmable Gate Arrays (FPGAs) can have over a million logic gates while system-on-chip (SOC) devices can combine a microprocessor, input and output channels, and sometimes an FPGA for programmability. With this increased intricacy, the possibility of "software-like" bugs such as incorrect design, logic, and unexpected interactions within the logic is great. Since CE devices are obscuring the hardware/software boundary, we propose that mature software methodologies may be utilized with slight modifications to develop these devices. By using standardized S/W Engineering methods such as checklists, missing requirements and "bugs" can be detected earlier in the development cycle, thus creating a development process for CE that will be easily maintained and configurable based on the device used.

FROM↗

Software Process Assurance for Complex Electronics

Complex Electronics (CE) now perform tasks that were previously handled in software, such as communication protocols. Many methods used to develop software bare a close resemblance to CE development. Field Programmable Gate Arrays (FPGAs) can have over a million logic gates while system-on-chip (SOC) devices can combine a microprocessor, input and output channels, and sometimes an FPGA for programmability. With this increased intricacy, the possibility of software-like bugs such as incorrect design, logic, and unexpected interactions within the logic is great. With CE devices obscuring the hardware/software boundary, we propose that mature software methodologies may be utilized with slight modifications in the development of these devices. Software Process Assurance for Complex Electronics (SPACE) is a research project that used standardized S/W Assurance/Engineering practices to provide an assurance framework for development activities. Tools such as checklists, best practices and techniques were used to detect missing requirements and bugs earlier in the development cycle creating a development process for CE that was more easily maintained, consistent and configurable based on the device used.

Plastow, Richard A.↗

Software Process Assurance for Complex Electronics (SPACE)

Complex Electronics (CE) are now programmed to perform tasks that were previously handled in software, such as communication protocols. Many of the methods used to develop software bare a close resemblance to CE development. For instance, Field Programmable Gate Arrays (FPGAs) can have over a million logic gates while system-on-chip (SOC) devices can combine a microprocessor, input and output channels, and sometimes an FPGA for programmability. With this increased intricacy, the possibility of software-like bugs such as incorrect design, logic, and unexpected interactions within the logic is great. Since CE devices are obscuring the hardware/software boundary, we propose that mature software methodologies may be utilized with slight modifications in the development of these devices. Software Process Assurance for Complex Electronics (SPACE) is a research project that looks at using standardized S/W Assurance/Engineering practices to provide an assurance framework for development activities. Tools such as checklists, best practices and techniques can be used to detect missing requirements and bugs earlier in the development cycle creating a development process for CE that will be more easily maintained, consistent and configurable based on the device used.

Plastow, Richard A.↗

The effect of output-input isolation on the scaling and energy consumption of all-spin logic devices

All-spin logic (ASL) is a novel approach for digital logic applications wherein spin is used as the state variable instead of charge. One of the challenges in realizing a practical ASL system is the need to ensure non-reciprocity, meaning the information flows from input to output, not vice versa. One approach described previously, is to introduce an asymmetric ground contact, and while this approach was shown to be effective, it remains unclear as to the optimal approach for achieving non-reciprocity in ASL. In this study, we quantitatively analyze techniques to achieve non-reciprocity in ASL devices, and we specifically compare the effect of using asymmetric ground position and dipole-coupled output/input isolation. For this analysis, we simulate the switching dynamics of multiple-stage logic devices with FePt and FePd perpendicular magnetic anisotropy materials using a combination of a matrix-based spin circuit model coupled to the Landau–Lifshitz–Gilbert equation. The dipole field is included in this model and can act as both a desirable means of coupling magnets and a source of noise. The dynamic energy consumption has been calculated for these schemes, as a function of input/output magnet separation, and the results show that using a scheme that electrically isolates logic stages produces superior non-reciprocity, thus allowing both improved scaling and reduced energy consumption.

71 CLASSICAL AND QUANTUM MECHANICS, GENERAL PHYSIC↗

Processing Device for High-Speed Execution of an Xrisc Computer Program

A processing device for high-speed execution of a computer program is provided. A memory module may store one or more computer programs. A sequencer may select one of the computer programs and controls execution of the selected program. A register module may store intermediate values associated with a current calculation set, a set of output values associated with a previous calculation set, and a set of input values associated with a subsequent calculation set. An external interface may receive the set of input values from a computing device and provides the set of output values to the computing device. A computation interface may provide a set of operands for computation during processing of the current calculation set. The set of input values are loaded into the register and the set of output values are unloaded from the register in parallel with processing of the current calculation set.

Ng, Tak-Kwong↗