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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 235 records · Page 13
All sourcesNASA NTRSDOE OSTI
NASA NTRS1980

An Imaging Infrared (IIR) seeker using a microprogrammed processor

A recently developed Imaging Infrared Seeker uses a microprogrammed processor to perform gimbal servo control and system interface while performing the seeker functions of automatic target detection, acquisition, and tracking. The automatic detection mode requires up to 80% of the available capability of a high performance microprogrammed processor. Although system complexity was increased significantly, this approach can be cost effective when the basic computation capacity is already available.

Richmond, K. V.↗
NASA NTRS1980

A high performance multiplier processor for use with aerospace microcomputers

An MC68000 based microcomputer including a hardware multiplier processor has been designed and prototyped for a reentry vehicle navigation and control application. In this paper, the microcomputer is discussed with emphasis on the multiplier processor architecture, software control and theory of operation.

Pierce, P. E.↗
NASA NTRS1981

Extended operating range of the 30-cm ion thruster with simplified power processor requirements

A two grid 30 cm diameter mercury ion thruster was operated with only six power supplies over the baseline J series thruster power throttle range with negligible impact on thruster performance. An analysis of the functional model power processor showed that the component mass and parts count could be reduced considerably and the electrical efficiency increased slightly by only replacing power supplies with relays. The input power, output thrust, and specific impulse of the thruster were then extended, still using six supplies, from 2660 watts, 0.13 newtons, and 2980 seconds to 9130 watts, 0.37 newtons, and 3820 seconds, respectively. Increases in thrust and power density enable reductions in the number of thrusters and power processors required for most missions. Preliminary assessments of the impact of thruster operation at increased thrust and power density on the discharge characteristics, performance, and lifetime of the thruster were also made.

Rawlin, V. K.↗
NASA NTRS1980

The massively parallel processor

Future sensor systems will utilize massively parallel computing systems for rapid analysis of two-dimensional data. The Goddard Space Flight Center has an ongoing program to develop these systems. A single-instruction multiple data computer known as the Massively Parallel Processor (MPP) is being fabricated for NASA by the Goodyear Aerospace Corporation. This processor contains 16,384 processing elements arranged in a 128 x 128 array. The MPP will be capable of adding more than 6 billion 8-bit numbers per second. Multiplication of eight-bit numbers can occur at a rate of 2 billion per second. Delivery of the MPP to Goddard Space Flight Center is scheduled for 1983.

Schaefer, D. H.↗
NASA NTRS1982

A floating-point/multiple-precision processor for airborne applications

A compact input output (I/O) numerical processor capable of performing floating-point, multiple precision and other arithmetic functions at execution times which are at least 100 times faster than comparable software emulation is described. The I/O device is a microcomputer system containing a 16 bit microprocessor, a numerical coprocessor with eight 80 bit registers running at a 5 MHz clock rate, 18K random access memory (RAM) and 16K electrically programmable read only memory (EPROM). The processor acts as an intelligent slave to the host computer and can be programmed in high order languages such as FORTRAN and PL/M-86.

Yee, R.↗
NASA NTRS1982

Computer simulation of a space SAR using a range-sequential processor for soil moisture mapping

The ability of a spaceborne synthetic aperture radar (SAR) to detect soil moisture was evaluated by means of a computer simulation technique. The computer simulation package includes coherent processing of the SAR data using a range-sequential processor, which can be set up through hardware implementations, thereby reducing the amount of telemetry involved. With such a processing approach, it is possible to monitor the earth's surface on a continuous basis, since data storage requirements can be easily met through the use of currently available technology. The Development of the simulation package is described, followed by an examination of the application of the technique to actual environments. The results indicate that in estimating soil moisture content with a four-look processor, the difference between the assumed and estimated values of soil moisture is within + or - 20% of field capacity for 62% of the pixels for agricultural terrain and for 53% of the pixels for hilly terrain. The estimation accuracy for soil moisture may be improved by reducing the effect of fading through non-coherent averaging.

Fujita, M.↗
NASA NTRS1982

Seasat synthetic-aperture radar data reduction using parallel programmable array processors

This paper presents a digital processing system that produces the Seasat synthetic-aperture radar (SAR) imagery. The system consists of a SEL 32/77 host minicomputer and three AP-120B array processors. The partitioning of the SAR processing functions and the design of software modules is described. The rationale for selecting the parallel array processor architecture and the methodology for developing the parallel processing scheme on this system is described. This system attains a Seasat SAR data reduction speed of 2.5 h per 25-m resolution 4-look and 100 km x 100 km image frame. A preliminary performance evaluation of this parallel processing system and potential future applications for remote sensing data reduction are described.

Wu, C.↗
NASA NTRS1982

Real-time optical synthetic aperture radar /SAR/ processor

A description is given of a real-time optical synthetic aperture radar (SAR). The processor employs an acoustooptic device as the input electronic-to-optical transducer and a CCD camera that serves as the optical detector and simultaneously performs the focusing of the SAR image in the azimuth direction. The performance criteria of the optical processor that are discussed include azimuth resolution, image size in azimuth, range resolution, image size in range, flexibility, and dynamic range.

Psaltis, D.↗
NASA NTRS1982

A microprocessor-based one dimensional optical data processor for spatial frequency analysis

A high degree of accuracy was obtained in measuring the spatial frequency spectrum of known samples using an optical data processor based on a microprocessor, which reliably collected intensity versus angle data. Stray light control, system alignment, and angle measurement problems were addressed and solved. The capabilities of the instrument were extended by the addition of appropriate optics to allow the use of different wavelengths of laser radiation and by increasing the travel limits of the rotating arm to + or - 160 degrees. The acquisition, storage, and plotting of data by the computer permits the researcher a free hand in data manipulation such as subtracting background scattering from a diffraction pattern. Tests conducted to verify the operation of the processor using a 25 mm diameter pinhole, a 39.37 line pairs per mm series of multiple slits, and a microscope slide coated with 1.091 mm diameter polystyrene latex spheres are described.

Collier, R. L.↗
NASA NTRS1983

The development of a power spectral density processor for C and L band airborne radar scatterometer sensor systems

A real-time signal processor was developed for the NASA/JSC L-and C-band airborne radar scatterometer sensor systems. The purpose of the effort was to reduce ground data processing costs. Conversion of two quadrature channels of data (like and cross polarized) was made to obtain Power Spectral Density (PSD) values. A chirp-z transform (CZT) approach was used to filter the Doppler return signal and improved high frequency and angular resolution was realized. The processors have been tested with record signals and excellent results were obtained. CZT filtering can be readily applied to scatterometers operating at other wavelengths by altering the sample frequency. The design of the hardware and software and the results of the performance tests are described in detail.

Harrison, D. A., III↗
NASA NTRS1983

SPP: A data base processor data communications protocol

The design and implementation of a data communications protocol for the Intel Data Base Processor (DBP) is defined. The protocol is termed SPP (Service Port Protocol) since it enables data transfer between the host computer and the DBP service port. The protocol implementation is extensible in that it is explicitly layered and the protocol functionality is hierarchically organized. Extensive trace and performance capabilities have been supplied with the protocol software to permit optional efficient monitoring of the data transfer between the host and the Intel data base processor. Machine independence was considered to be an important attribute during the design and implementation of SPP. The protocol source is fully commented and is included in Appendix A of this report.

Fishwick, P. A.↗
NASA NTRS1982

Multibeam single frequency synthetic aperture radar processor for imaging separate range swaths

A single-frequency multibeam synthetic aperture radar for large swath imaging is disclosed. Each beam illuminates a separate ""footprint'' (i.e., range and azimuth interval). The distinct azimuth intervals for the separate beams produce a distinct Doppler frequency spectrum for each beam. After range correlation of raw data, an optical processor develops image data for the different beams by spatially separating the beams to place each beam of different Doppler frequency spectrum in a different location in the frequency plane as well as the imaging plane of the optical processor. Selection of a beam for imaging may be made in the frequency plane by adjusting the position of an aperture, or in the image plane by adjusting the position of a slit. The raw data may also be processed in digital form in an analogous manner.

Jain, A.↗
NASA NTRS1983

Parallel processing in a host plus multiple array processor system for radar

Host plus multiple array processor architecture is demonstrated to yield a modular, fast, and cost-effective system for radar processing. Software methodology for programming such a system is developed. Parallel processing with pipelined data flow among the host, array processors, and discs is implemented. Theoretical analysis of performance is made and experimentally verified. The broad class of problems to which the architecture and methodology can be applied is indicated.

Barkan, B. Z.↗
NASA NTRS1983

Frequency-multiplexed and pipelined iterative optical systolic array processors

Optical matrix processors using acoustooptic transducers are described, with emphasis on new systolic array architectures using frequency multiplexing in addition to space and time multiplexing. A Kalman filtering application is considered in a case study from which the operations required on such a system can be defined. This also serves as a new and powerful application for iterative optical processors. The importance of pipelining the data flow and the ordering of the operations performed in a specific application of such a system are also noted. Several examples of how to effectively achieve this are included. A new technique for handling bipolar data on such architectures is also described.

Casasent, D.↗
NASA NTRS1983

Optical systolic array processor using residue arithmetic

The use of residue arithmetic to increase the accuracy and reduce the dynamic range requirements of optical matrix-vector processors is evaluated. It is determined that matrix-vector operations and iterative algorithms can be performed totally in residue notation. A new parallel residue quantizer circuit is developed which significantly improves the performance of the systolic array feedback processor. Results are presented of a computer simulation of this system used to solve a set of three simultaneous equations.

Jackson, J.↗
NASA NTRS1984

Investigation of TM Band-to-band Registration Using the JSC Registration Processor

The JSC registration processor performs scene-to-scene (or band-to-band) correlation based on edge images. The edge images are derived from a percentage of the edge pixels calculated from the raw scene data, excluding clouds and other extraneous data in the scene. Correlations are performed on patches (blocks) of the edge images, and the correlation peak location in each patch is estimated iteratively to fractional pixel location accuracy. Peak offset locations from all patches over the scene are then considered together, and a variety of tests are made to weed out outliers and other inconsistencies before a distortion model is assumed. Thus, the correlation peak offset locations in each patch indicate quantitatively how well the two TM bands register to each other over that patch of scene data. The average of these offsets indicate the overall accuracies of the band-to-band registration. The registration processor was also used to register one acquisition to another acquisition of multitemporal TM data acquired over the same ground track. Band 4 images from both acquisitions were correlated and an rms error of a fraction of a pixel was routinely obtained.

Yao, S. S.↗
NASA NTRS1982

A programmable power processor for high power space applications

A Programmable Power Processor (P3) has been developed for application in future large space power systems. The P3 is capable of operation over a wide range of input voltage (26 to 375 Vdc) and output voltage (24 to 180 Vdc). The peak output power capability is 18 kW (180 V at 100 A). The output characteristics of the P3 can be programmed to any voltage and/or current level within the limits of the processor and may be controlled as a function of internal or external parameters. Seven breadboard P3s and one 'flight-type' engineering model P3 have been built and tested both individually and in electrical power systems. The programmable feature allows the P3 to be used in a variety of applications by changing the output characteristics. Test results, including efficiency at various input/output combinations, transient response, and output impedance, are presented.

Lanier, J. R., Jr.↗