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At least 253 records · Page 14

Manipulation of Micro Scale Particles in Optical Traps Using Programmable Spatial Light Modulation

1064 nm light, from an Nd:YAG laser, was polarized and incident upon a programmable parallel aligned liquid crystal spatial light modulator (PAL-SLM), where it was phase modulated according to the program controlling the PAL-SLM. Light reflected from the PAL-SLM was injected into a microscope and focused. At the focus, multiple optical traps were formed in which 9.975 m spheres were captured. The traps and the spheres were moved by changing the program of the PAL-SLM. The motion of ordered groups of micro particles was clearly demonstrated.

Seibel, Robin E.

Programmable 2-D Addressable Cryogenic Aperture Masks

We are developing a two-dimensional array of square microshutters (programmable aperture mask) for a multi-object spectrometer for the James Webb Space Telescope (JWST). This device will provide random access selection of the areas in the field to be studied. The device is in essence a close packed array of square slits, each of which can be opened independently to select areas of the sky for detailed study.The device is produced using a 100-micron thick silicon wafer as a substrate with 0.5-micron thick silicon nitride shutters on top of it. Silicon nitride has been selected as the blade and flexure material because its stiffness allows thinner and lighter structures than single crystal Si, the chief alternative, and because of its ease of manufacture. The 100 micron silicon wafer is backetched in a high aspect ratio Deep Reactive Ion Etching (Deep RIE) to leave only a support grid for the shutters and the address electronics. The shutter actuation is done magnetically whereas addressing is electrostatic. 128x128 format microshutter arrays have been produced. Their operation has been demostarted on 32x32 subarrays. Good reliability of the fabrication process and good quality of the microshutters has been achieved. The mechanical behavior and optical performance of the fabricated arrays at cryogenic temperature are being studied.

Kutyrev, A. S.

Evolutionary Based Techniques for Fault Tolerant Field Programmable Gate Arrays

The use of SRAM-based Field Programmable Gate Arrays (FPGAs) is becoming more and more prevalent in space applications. Commercial-grade FPGAs are potentially susceptible to permanently debilitating Single-Event Latchups (SELs). Repair methods based on Evolutionary Algorithms may be applied to FPGA circuits to enable successful fault recovery. This paper presents the experimental results of applying such methods to repair four commonly used circuits (quadrature decoder, 3-by-3-bit multiplier, 3-by-3-bit adder, 440-7 decoder) into which a number of simulated faults have been introduced. The results suggest that evolutionary repair techniques can improve the process of fault recovery when used instead of or as a supplement to Triple Modular Redundancy (TMR), which is currently the predominant method for mitigating FPGA faults.

Larchev, Gregory V.

Programmable Thermostat Module Upgrade for the Multi-Purpose Logistics Module

The STS-121/ULF1.1 mission was the maiden flight of the Programmable Thermostat Module (PTM) system used to control the 28 V shell heaters on the Multi-Purpose Logistics Module (MPLM). These PTMs, in conjunction with a Data Recorder Module (DRM), provide continuous closed loop temperature control and data recording of MPLM on-orbit heater operations. This paper will discuss the hardware design, development, test and verification (DDT&V) activities performed at the Marshall Space Flight Center (MSFC) as well as the operational implementation and mission performance.

Clark, Dallas

Use of Field Programmable Gate Array Technology in Future Space Avionics

Fulfilling NASA's new vision for space exploration requires the development of sustainable, flexible and fault tolerant spacecraft control systems. The traditional development paradigm consists of the purchase or fabrication of hardware boards with fixed processor and/or Digital Signal Processing (DSP) components interconnected via a standardized bus system. This is followed by the purchase and/or development of software. This paradigm has several disadvantages for the development of systems to support NASA's new vision. Building a system to be fault tolerant increases the complexity and decreases the performance of included software. Standard bus design and conventional implementation produces natural bottlenecks. Configuring hardware components in systems containing common processors and DSPs is difficult initially and expensive or impossible to change later. The existence of Hardware Description Languages (HDLs), the recent increase in performance, density and radiation tolerance of Field Programmable Gate Arrays (FPGAs), and Intellectual Property (IP) Cores provides the technology for reprogrammable Systems on a Chip (SOC). This technology supports a paradigm better suited for NASA's vision. Hardware and software production are melded for more effective development; they can both evolve together over time. Designers incorporating this technology into future avionics can benefit from its flexibility. Systems can be designed with improved fault isolation and tolerance using hardware instead of software. Also, these designs can be protected from obsolescence problems where maintenance is compromised via component and vendor availability.To investigate the flexibility of this technology, the core of the Central Processing Unit and Input/Output Processor of the Space Shuttle AP101S Computer were prototyped in Verilog HDL and synthesized into an Altera Stratix FPGA.

Ferguson, Roscoe C.

Programmable Thermostat Module Upgrade for the Multipurpose Logistics Module

The STS-121/ULF 1.1 mission was the maiden flight of the programmable thermostat module (PTM) system used to control the 28 V shell heaters on the multi-purpose logistics module (MPLM). These PTMs, in conjunction with a data recorder module (DRM), provide continuous closed loop temperature control and data recording of MPLM on-orbit heater operations. This Technical Memorandum discusses the hardware design, development, test, and verification (DDT&V) activities performed at the Marshall Space Flight Center as well as the operational implementation and mission performance.

Clark, D. W.

Initial Single Event Effects Testing of the Xilinx Virtex-4 Field Programmable Gate Array

We present initial results for the thin epitaxial Xilinx Virtex-4 Fie ld Programmable Gate Array (FPGA), and compare to previous results ob tained for the Virtex-II and Virtex-II Pro. The data presented was a cquired through a consortium based effort with the common goal of pr oviding the space community with data and mitigation methods for the use of Xilinx FPGAs in space.

single event effects

Compact programmable photonic variable delay devices

Optical variable delay devices for providing variable true time delay to multiple optical beams simultaneously. A ladder-structured variable delay device comprises multiple basic building blocks stacked on top of each other resembling a ladder. Each basic building block has two polarization beamsplitters and a polarization rotator array arranged to form a trihedron; Controlling an array element of the polarization rotator array causes a beam passing through the array element either going up to a basic building block above it or reflect back towards a block below it. The beams going higher on the ladder experience longer optical path delay. An index-switched optical variable delay device comprises of many birefringent crystal segments connected with one another, with a polarization rotator array sandwiched between any two adjacent crystal segments. An array element in the polarization rotator array controls the polarization state of a beam passing through the element, causing the beam experience different refractive indices or path delays in the following crystal segment. By independently control each element in each polarization rotator array, variable optical path delays of each beam can be achieved. Finally, an index-switched variable delay device and a ladder-structured variable device are cascaded to form a new device which combines the advantages of the two individual devices. This programmable optic device has the properties of high packing density, low loss, easy fabrication, and virtually infinite bandwidth. The device is inherently two dimensional and has a packing density exceeding 25 lines/cm.sup.2. The delay resolution of the device is on the order of a femtosecond (one micron in space) and the total delay exceeds 10 nanosecond. In addition, the delay is reversible so that the same delay device can be used for both antenna transmitting and receiving.

Yao, X. Steve

High Contrast Programmable Field Masks for JWST NIRSpec

Microshutter arrays are one of the novel technologies developed for the James Webb Space Telescope (JWST). It will allow Near Infrared Spectrometer (NIRSpec) to acquire spectra of hundreds of objects simultaneously therefore increasing its efficiency tremendously. We have developed these programmable arrays that are based on Micro-Electro Mechanical Structures (MEMS) technology. The arrays are 2D addressable masks that can operate in cryogenic environment of JWST. Since the primary JWST science requires acquisition of spectra of extremely faint objects, it is important to provide very high contrast of the open to closed shutters. This high contrast is necessary to eliminate any possible contamination and confusion in the acquired spectra by unwanted objects. We have developed and built a test system for the microshutter array functional and optical characterization. This system is capable of measuring the contrast of the microshutter array both in visible and infrared light of the NIRSpec wavelength range while the arrays are in their working cryogenic environment. We have measured contrast ratio of several microshutter arrays and demonstrated that they satisfy and in many cases far exceed the NIRSpec contrast requirement value of 2000.

Kutyrev, Alexander S.

Evolutionary Multiobjective Design Targeting a Field Programmable Transistor Array

This paper introduces the ISPAES algorithm for circuit design targeting a Field Programmable Transistor Array (FPTA). The use of evolutionary algorithms is common in circuit design problems, where a single fitness function drives the evolution process. Frequently, the design problem is subject to several goals or operating constraints, thus, designing a suitable fitness function catching all requirements becomes an issue. Such a problem is amenable for multi-objective optimization, however, evolutionary algorithms lack an inherent mechanism for constraint handling. This paper introduces ISPAES, an evolutionary optimization algorithm enhanced with a constraint handling technique. Several design problems targeting a FPTA show the potential of our approach.

global optimization

Programmable Low-Voltage Circuit Breaker and Tester

An instrumentation system that would comprise a remotely controllable and programmable low-voltage circuit breaker plus several electric-circuit-testing subsystems has been conceived, originally for use aboard a spacecraft during all phases of operation from pre-launch testing through launch, ascent, orbit, descent, and landing. The system could also be adapted to similar use aboard aircraft. In comparison with remotely controllable circuit breakers heretofore commercially available, this system would be smaller, less massive, and capable of performing more functions, as needed for aerospace applications.

Greenfield, Terry