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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 253 records · Page 14
All sourcesNASA NTRSDOE OSTI
DOE OSTI2022

Thermal Optimization of a Silicon Carbide, Half-Bridge Power Module

This project describes the modeling process to design the packaging and heat exchanger for a half-bridge wide-bandgap (WBG) power semiconductor module. The module uses two silicon carbide, metal-oxide-semiconductor field-effect transistor (MOSFET) devices per switch position that are soldered to an aluminum nitride, direct-bond copper (DBC) substrate. A baseplate cooling configuration (e.g., no thermal grease) is used along with a water-ethylene glycol, jet-impingement-style heat exchanger. The heat exchanger was designed to be fabricated using prototyping equipment from the National Renewable Energy Laboratory, complies with automotive standards (for minimal channel sizes, flow rates, and coolant), and considers reliability aspects (i.e., erosion/corrosion). Device-scale computational fluid dynamics (CFD) is used first to design the slot jet impingement cooling configuration and compute the effective heat transfer coefficient (HTC) of the concept. The computed HTCs are then used as boundary conditions for a finite element study to optimize the package geometry (e.g., device layout and baseplate thickness) to minimize thermal resistance and minimize temperature variation between the module's four devices. Finally, a fluid manifold is designed to generate the slot jets and cool the devices. Module-scale CFD predicts a relatively low junction-to-fluid thermal resistance of 16.7 mm2 K/W, a 1.4 degrees C temperature variation between devices, and a total pressure drop of 5,860 Pa (0.85 psi) for the design. The thermal resistance of the module design is about 67% lower than the 2015 BMW i3 power electronics/modules thermal resistance.

DIRECT ENERGY CONVERSION↗
DOE OSTI2025

Thermal Modeling and Limitations for Power Electronics Embedded in Medium-Voltage Cables

As next-generation energy technologies gain traction and power demand increases, the existing electrical infrastructure faces significant stress, prompting innovative solutions to enhance the grid's capacity and lifespan. This work explores the possibility of embedding medium-voltage (MV) power electronics directly inline with the cable, and the resulting thermal challenges. Since the majority of power distribution cables installed in the U.S. are passively cooled, the work focuses primarily on passive cooling, with an emphasis on the limitations of axial heat spreading within the cable. To date, literature on axial spreading of high incident heat loads on cables and cable environments is limited, typically reporting cases with <10 W of incident heat load. This work will explore the considerations, limits, and tradeoffs of cable-embedded heat loads significantly larger than the cable losses. Both external and internal effects are modeled analytically in nondimensional terms via a Biot number analysis, allowing fundamental limits and tradeoffs to be derived. The work culminates in the design and experimental validation of a cable-embedded thermal system capable of passively dissipating 300 W of heat from a coaxial SiC mosfet switch module over a length of 20 cm, thus validating the possibility of MV cable-embedded power electronics from a thermal standpoint.

24 POWER TRANSMISSION AND DISTRIBUTION↗
DOE OSTI2021

Efficiency Optimization of Dual Active Bridge Converter Based on dV/dt Snubber Capacitors

This paper presents a lossless regenerative dV/dt snubber circuit for PWM converters to achieve high-efficiency high power-density without significant cost and reliability penalties. The dV/dt snubber employs lossless capacitors for each MOSFET device in a converter to provide an additional path to store the switching energy during turn-off transient and decrease the actual turn-off loss of the MOSFET channel. A novel mathematical turn-off loss model is built to separate the actual turn-off loss of the MOSFET channel and the recycling switching energy stored in the total equivalent output capacitance including Coss, the dV/dt snubber, and etc. Necessary snubber optimization strategy is proposed in order to balance the turn-off loss with ZVS operation range and deadtime conduction loss, and thereby achieving an optimal efficiency performance. To prove the validity and accuracy of the novel turn-off loss model and optimization strategy, the dV/dt snubber has been incorporated into a 1.3kV/200kW DC/DC and a 1kV/70kVA DC/AC PWM converters. Experimental results are given to demonstrate the validity of the proposed dV/dt snubber capacitors and optimization strategy.

Xu, Wei↗
DOE OSTI2026

A Vertical GaN-Based Neutral-Pointless Three-Level Inverter for High-Performance Automotive Traction Applications

Silicon Carbide (SiC) MOSFETs have emerged as a dominant solution for electric vehicle traction inverters because of their superior power density and efficiency compared to Silicon (Si) counterparts. However, SiC devices possess inherent switching speed limitations that constrain the maximum switching frequency and hinder further power density and efficiency improvements. To address these limitations, this paper proposes a vertical Gallium Nitride (vGaN) based X-type Neutral-Pointless (NPL.X) three-level (3L) inverter for an 800V, 200 kW traction system. Integrating 700V vGaN technology within the NPL.X 3L topology enables improved drive efficiency and higher switching frequencies, resulting in enhanced power density and output power quality. To evaluate the performance benefits, this work conducts a comprehensive loss characterization of the vGaN￾based NPL.X topology, providing a direct comparison with a SiC￾based two level (2L) inverter. The results show that the proposed vGaN-based inverter achieves superior efficiency, particularly within the low-torque regions that dominate standard automotive drive cycles. The proposed vGaN-based inverter represents a critical advancement toward high-power-density and high efficiency traction drives

Halawa, Ali [Purdue Univ., West Lafayette, IN (Uni↗
NASA NTRS1980

Oxidation of gallium arsenide in a plasma multipole device. Study of the MOS structures obtained

The oxygen plasma oxidation of GaAs was studied in order to obtain extremely high frequency responses with MOS devices. In the multipole system a homogeneous oxygen plasma of high density can easily be obtained in a large volume. This system is thus convenient for the study of plasma oxidation of GaAs. The electrical properties of the MOS diodes obtained in this way are controlled by interface states, located mostly in the upper half of the band gap where densities in the 10 to the 13th power/(sq cm) (eV) range can be estimated. Despite these interface states the possibility of fabricating MOSFET transistors working mostly in the depletion mode for a higher frequency cut-off still exists.

Gourrier, S.↗
DOE OSTI2020

Packaging Development for a 1200V SiC BiDFET Switch Using Highly Thermally Conductive Organic Epoxy Laminate

A novel 1.2 kV/10A, 4H-SiC monolithic, bidirectional switch has been developed for use in cycloconverter applications to facilitate high-frequency direct AC-to-AC power conversion and enables new power converter topologies. A new packaging solution, utilizing a 100 µm flexible polyimide organic laminate substrate is developed to mitigate thermo-mechanical stress during power cycling and enable smaller form factor and lower cost. Multiphysics simulations and static tests were conducted to show performance characterization of the module and compare it against metallic substrates. A new organic laminate epoxy resin composite dielectric (ERCD) is also evaluated for superior thermal performance and shows 63% reduction in junction to case resistance compared to DBC substrates.

Silicon Carbide, Bi-directional switch, BiDFET, MO↗
NASA NTRS2002

Methods for growth of relatively large step-free SiC crystal surfaces

A method for growing arrays of large-area device-size films of step-free (i.e., atomically flat) SiC surfaces for semiconductor electronic device applications is disclosed. This method utilizes a lateral growth process that better overcomes the effect of extended defects in the seed crystal substrate that limited the obtainable step-free area achievable by prior art processes. The step-free SiC surface is particularly suited for the heteroepitaxial growth of 3C (cubic) SiC, AlN, and GaN films used for the fabrication of both surface-sensitive devices (i.e., surface channel field effect transistors such as HEMT's and MOSFET's) as well as high-electric field devices (pn diodes and other solid-state power switching devices) that are sensitive to extended crystal defects.

Neudeck, Philip G.↗
NASA NTRS2010

Modeling of Sonos Memory Cell Erase Cycle

Silicon-oxide-nitride-oxide-silicon (SONOS) nonvolatile semiconductor memories (NVSMS) have many advantages. These memories are electrically erasable programmable read-only memories (EEPROMs). They utilize low programming voltages, endure extended erase/write cycles, are inherently resistant to radiation, and are compatible with high-density scaled CMOS for low power, portable electronics. The SONOS memory cell erase cycle was investigated using a nonquasi-static (NQS) MOSFET model. The SONOS floating gate charge and voltage, tunneling current, threshold voltage, and drain current were characterized during an erase cycle. Comparisons were made between the model predictions and experimental device data.

Phillips, Thomas A.↗
NASA NTRS2009

SOI N-Channel Field Effect Transistors, CHT-NMOS80, for Extreme Temperatures

Extreme temperatures, both hot and cold, are anticipated in many of NASA space exploration missions as well as in terrestrial applications. One can seldom find electronics that are capable of operation under both regimes. Even for operation under one (hot or cold) temperature extreme, some thermal controls need to be introduced to provide appropriate ambient temperatures so that spacecraft on-board or field on-site electronic systems work properly. The inclusion of these controls, which comprise of heating elements and radiators along with their associated structures, adds to the complexity in the design of the system, increases cost and weight, and affects overall reliability. Thus, it would be highly desirable and very beneficial to eliminate these thermal measures in order to simplify system's design, improve efficiency, reduce development and launch costs, and improve reliability. These requirements can only be met through the development of electronic parts that are designed for proper and efficient operation under extreme temperature conditions. Silicon-on-insulator (SOI) based devices are finding more use in harsh environments due to the benefits that their inherent design offers in terms of reduced leakage currents, less power consumption, faster switching speeds, good radiation tolerance, and extreme temperature operability. Little is known, however, about their performance at cryogenic temperatures and under wide thermal swings. The objective of this work was to evaluate the performance of a new commercial-off-the-shelf (COTS) SOI parts over an extended temperature range and to determine the effects of thermal cycling on their performance. The results will establish a baseline on the suitability of such devices for use in space exploration missions under extreme temperatures, and will aid mission planners and circuit designers in the proper selection of electronic parts and circuits. The electronic part investigated in this work comprised of a CHT-NMOS80 high temperature N-channel MOSFET (metal-oxide semiconductor field-effect transistor) device that was manufactured by CISSOID. This high voltage, medium-power transistor is fabricated using SOI processes and is designed for extreme wide temperature applications such as geothermal well logging, aerospace and avionics, and automotive industry. It has a high DC current capability and is specified for operation in the temperature range of -55 C to +225 C

Patterson, Richard L.↗
NASA NTRS1993

Power management and distribution technology

Power management and distribution (PMAD) technology is discussed in the context of developing working systems for a piloted Mars nuclear electric propulsion (NEP) vehicle. The discussion is presented in vugraph form. The following topics are covered: applications and systems definitions; high performance components; the Civilian Space Technology Initiative (CSTI) high capacity power program; fiber optic sensors for power diagnostics; high temperature power electronics; 200 C baseplate electronics; high temperature component characterization; a high temperature coaxial transformer; and a silicon carbide mosfet.

Dickman, John Ellis↗
NASA NTRS1995

Improved L-C resonant decay technique for Q measurement of quasilinear power inductors: New results for MPP and ferrite powdered cores

The L-C resonant decay technique for measuring circuit Q or losses is improved by eliminating the switch from the inductor-capacitor loop. A MOSFET switch is used instead to momentarily connect the resonant circuit to an existing voltage source, which itself is gated off during the decay transient. Very reproducible, low duty cycle data could be taken this way over a dynamic voltage range of at least 10:1. Circuit Q is computed from a polynomial fit to the sequence of the decaying voltage maxima. This method was applied to measure the losses at 60 kHz in inductors having loose powder cores of moly permalloy and an Mn-Zn power ferrite. After the copper and capacitor losses are separated out, the resulting specific core loss is shown to be roughly as expected for the MPP powder, but anomalously high for the ferrite powder. Possible causes are mentioned.

Niedra, Janis M.↗
DOE OSTI2023

Selective area doping of GaN toward high-power applications

Abstract Selective area doping in GaN, especially p-type, is a critical and inevitable building block for the realization of advanced device structures for high-power applications, including, but not limited to, current-aperture vertical electron transistors, junction termination extensions, junction barrier Schottky diodes, junction field-effect transistors (JFETs), vertical-channel JFETs, U-shaped metal–oxide–semiconductor field-effect transistors (U-MOSFETs), and Fin MOSFETs. This paper reviews and summarizes some of the recent advances in the fields of selective area etching and regrowth, ion implantation, and polarity-dependent doping that may lead to the practical realization of GaN-based power devices.

Physics↗
NASA NTRS2011

Modeling of SONOS Memory Cell Erase Cycle

Utilization of Silicon-Oxide-Nitride-Oxide-Silicon (SONOS) nonvolatile semiconductor memories as a flash memory has many advantages. These electrically erasable programmable read-only memories (EEPROMs) utilize low programming voltages, have a high erase/write cycle lifetime, are radiation hardened, and are compatible with high-density scaled CMOS for low power, portable electronics. In this paper, the SONOS memory cell erase cycle was investigated using a nonquasi-static (NQS) MOSFET model. Comparisons were made between the model predictions and experimental data.

Phillips, Thomas A.↗
NASA NTRS1993

Design of power electronics for TVC EMA systems

The Composite Development Division of the Propulsion Laboratory at Marshall Space Flight Center (MSFC) is currently developing a class of electromechanical actuators (EMA's) for use in space transportation applications such as thrust vector control (TVC) and propellant control valves (PCV). These high power servomechanisms will require rugged, reliable, and compact power electronic modules capable of modulating several hundred amperes of current at up to 270 volts. MSFC has selected the brushless dc motor for implementation in EMA's. This report presents the results of an investigation into the applicability of two new technologies, MOS-controlled thyristors (MCT's) and pulse density modulation (PDM), to the control of brushless dc motors in EMA systems. MCT's are new power semiconductor devices, which combine the high voltage and current capabilities of conventional thyristors and the low gate drive requirements of metal oxide semiconductor field effect transistors (MOSFET's). The commanded signals in a PDM system are synthesized using a series of sinusoidal pulses instead of a series of square pulses as in a pulse width modulation (PWM) system. A resonant dc link inverter is employed to generate the sinusoidal pulses in the PDM system. This inverter permits zero-voltage switching of all semiconductors which reduces switching losses and switching stresses. The objectives of this project are to develop and validate an analytical model of the MCT device when used in high power motor control applications and to design, fabricate, and test a prototype electronic circuit employing both MCT and PDM technology for controlling a brushless dc motor.

Nelms, R. Mark↗
NASA NTRS1986

Development of 30 micrometers extrinsic silicon multiplexed infrared deterctor array

Two hybrid infrared (IR) detector arrays of antimony-doped silicon (Si:Sb) were produced and tested to evaluate their potential for use in low-background IR astronomy applications. The format of the arrays is 58 x 62 elements, with 76 micron-square pixels. A random-access, switched metal-oxide semiconductor field effect transistor (MOSFET) silicon multiplexer is used to read out the array elements. Reduced-background tests of signal, noise, and noise equivalent power were conducted over the temperature range 3.2 to 12 K. The arrays were found to have good sensitivity and good uniformity.

Orias, G.↗
DOE OSTI2025

Low Cost High-Performance HRE-Free 3-in-1 Electric Drive Unit

The project team completed work to expand upon American Axle & Manufacturing’s (AAM) baseline technology and develop a high-speed, AC induction electric drive unit (EDU) with total direct-oil-cooling and integrated power electronics. The project accelerated advancements in EDU technology by allowing AAM to build upon the progress made in developing the underlying baseline technologies. The following seven improvements to AAM’s baseline technology were implemented in this research and development program: 1) Increased speed (30k RPM) AC induction motor, 2) Silver-sintering of discrete silicon carbide (SiC) metal-oxide-semiconductor field-effect transistors (MOSFET) to heat sinks, 3) Electrically insulated rotor bars, 4) Optimized lamination steel, 5) EDU-integrated 650VDC inverter package, 6) Over-molded stator with molded liners, and 7) 650VDC power-dense stator design. The successful development of the technology resulted in a meaningful cost reduction for EDU systems in the market. Coupled with falling battery system costs, lower EDU costs will likely accelerate the market acceptance and related production scaling of battery electric vehicles. The objective of this project was to research, develop, and test a Heavy Rare Earth (HRE)-free 3-In-1 electric drive unit (EDU) that has class leading power density and cost. The key technologies to be developed were anticipated to meet or exceed the Department of Energy (DOE) targets of a cost ≤ $\$$7/kilowatt (kW), power density ≥ 12 kW/liter, and operating voltage ≥ 600 VDC.

33 ADVANCED PROPULSION SYSTEMS↗
NASA NTRSDate not supplied

Electronic Speed Controller Thermal Management

This experiment was coupled with an acoustic test for NASA’s QUiet Electric ENgine (QUEEN). A cold plate with water was used to cool the electronic speed controller of the motor under different conditions (shown on right). Part 1: Fixed motor RPM, translating to fixed power/heat dissipation (4W per MOSFET) of electrical components, with variable cooling capacity measured by flow rate of cold plate water in gpm. Part 2: Fixed cooling power (1 gpm) with variable RPM.

thermal↗
DOE OSTI2022

A PCB-Embedded 1.2 kV SiC MOSFET Half-Bridge Package for a 22 kW AC–DC Converter

This article presents the design and analysis of a double-side-cooled printed circuit board (PCB) embedded silicon carbide (SiC) MOSFET half-bridge package with low loop inductances and an integrated gate driver. The 1.2 kV SiC MOSFET dies used in the half-bridge package are embedded in the PCB using AT&S's patented technique. The dies are cooled and electrically connected to traces in the PCB through copper-filled microvias. The design methodology accounts for both electrical and thermal performance, limiting the power-loop inductance to 2.3 nH and the maximum package temperature to less than the 175 °C limit. The integration of the gate drive circuitry allows for a high power density and 2.2 nH gate-loop inductances. At 0.12 K/W, the measured junction-to-case thermal resistance with double-sided cooling is 57% lower than that of a TO-247 package. Under similar operating conditions, the PCB-embedded half-bridge package also achieves a 5.6 times lower voltage overshoot and a 0.5% higher peak efficiency than a TO-247-based half-bridge. This article reports the first demonstration of PCB-embedded 1.2 kV SiC MOSFET packages in buck, boost, and ac–dc converters. Furthermore, the prototype three-phase ac–dc converter for an electric vehicle on-board charger is composed of six PCB-embedded half-bridge packages and achieves an efficiency of 98.2% and a power density of 182 W/in 3 .

42 ENGINEERING↗