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The performance of minimal stuck-at fault test sets at detecting bridging faults are evaluated. New functional models of circuit primitives are presented which allow accurate representation of bridging faults under switch-level simulation. The effectiveness of the patterns is evaluated using both voltage and current testing.
Arrays of far-infrared photoconductor detectors operate at a few degrees Kelvin and require electronic amplifiers in close proximity. For the electronics, a cryogenic multiplexer is ideal to avoid the large number of wires associated with individual amplifiers for each pixel, and to avoid adverse effects of thermal and radiative heat loads from the circuitry. For low background applications, the 32 channel CRC 696 CMOS device was previously developed for SIRTF, the cryogenic Space Infrared Telescope Facility. For higher background applications, we have developed a similar circuit, featuring several modifications: (a) an AC coupled, capacitive feedback transimpedence unit cell, to minimize input offset effects, thereby enabling low detector biases, (b) selectable feedback capacitors to enable operation over a wide range of backgrounds, and (c) clamp and sample & hold output circuits to improve sampling efficiency, which is a concern at the high readout rates required. We describe the requirements for and design of the new device.
Customizable Digital Receivers for Radar Two-Camera Acquisition and Tracking of a Flying Target Visual Data Analysis for Satellites A Data Type for Efficient Representation of Other Data Types Hand-Held Ultrasonic Instrument for Reading Matrix Symbols Broadband Microstrip-to-Coplanar Strip Double-Y Balun A Topographical Lidar System for Terrain-Relative Navigation Programmable Low-Voltage Circuit Breaker and Tester Electronic Switch Arrays for Managing Microbattery Arrays Topics covered include: Lower-Dark-Current, Higher-Blue-Response CMOS Imagers; Fabricating Large-Area Sheets of Single-Layer Graphene by CVD; Support for Diagnosis of Custom Computer Hardware; Providing Goal-Based Autonomy for Commanding a Spacecraft; Dynamic Method for Identifying Collected Sample Mass; Optimal Planning and Problem-Solving; Attitude-Control Algorithm for Minimizing Maneuver Execution Errors; Grants Document-Generation System; Heat-Storage Modules Containing LiNO3 3H2O and Graphite Foam; Precipitation-Strengthened, High-Temperature, High-Force Shape Memory Alloys; Improved Relief Valve Would Be Less Susceptible to Failure; Safety Modification of Cam-and-Groove Hose Coupling; Using Composite Materials in a Cryogenic Pump; Using Electronic Noses to Detect Tumors During Neurosurgery; Producing Newborn Synchronous Mammalian Cells; Smaller, Lower-Power Fast-Neutron Scintillation Detectors; Rotationally Vibrating Electric-Field Mill; Estimating Hardness from the USDC Tool-Bit Temperature Rise; Particle-Charge Spectrometer; Automated Production of Movies on a Cluster of Computers; FIDO-Class Development Rover; and Tone-Based Command of Deep Space Probes Using Ground Antennas.
The development of two 256 by 256 hybrid HgCdTe focal plane array (FPA) families is described, and their performance is discussed. The hybrid FPAs employ a PV HgCdTe detector array and custom Si CMOS readouts. The PACE-1 process was used to fabricate the detectors, whereby the liquid phase epitaxial growth of HgCdTe occurs on sapphire substrates buffered by a layer of CdTe. The performance characteristics of the detector arrays are given. A tactical 256 by 256 CMOS readout is tested, in which a high functional yield was achieved. Updated test results are given for a 256 by 256 readout circuit developed for use in an orbital replacement instrument for the Hubble Space Telescope. The characterizations of several MWIR and SWIR FPAs were thorough and shown to be reliable. The pixel yield, maximum FPA responsivity nonuniformity, and SWIR FPA read noise for the tests are given. The high contrast and insignificant fixed pattern noise of the imagery from the MWIR 256 by 256 FPA are emphasized. These qualities were obtained when the device was operating at 80 k and utilizing f/2 optics with an 8-in. focal length and a 4.4 micron high pass filter.
Long-term spaceflight may induce a variety of harmful effects in astronauts, resulting in altered motor and cognitive behavior. The stresses experienced by humans in space - most significantly weightlessness (microgravity) and cosmic radiation - are difficult to accurately simulate on Earth. In fact, prolonged and concomitant exposure to microgravity and cosmic radiation can only be studied in space. Behavioral studies in space have focused on model organisms, including Drosophila melanogaster. Drosophila is often used due to its short life span and generational cycle, small size, and ease of maintenance. Additionally, the well-characterized genetics of Drosophila behavior on Earth can be applied to the analysis of results from spaceflights, provided that the behavior in space is accurately recorded. In 2001, the BioExplorer project introduced a low-cost option for researchers: the small satellite. While this approach enabled multiple inexpensive launches of biological experiments, it also imposed stringent restrictions on the monitoring systems in terms of size, mass, data bandwidth, and power consumption. Suggested parameters for size are on the order of 100 mm3 and 1 kg mass for the entire payload. For Drosophila behavioral studies, these engineering requirements are not met by commercially available systems. One system that does meet many requirements for behavioral studies in space is the actimeter. Actimeters use infrared light gates to track the number of times a fly crosses a boundary within a small container (3x3x40 mm). Unfortunately, the apparatus needed to monitor several flies at once would be larger than the capacity of the small satellite. A system is presented, which expands on the actimeter approach to achieve a highly compact, low-power, ultra-low bandwidth solution for simultaneous monitoring of the behavior of multiple flies in space. This also provides a simple, inexpensive alternative to the current systems for monitoring Drosophila populations in terrestrial experiments, and could be especially useful in field experiments in remote locations. Two practical limitations of the system should be noted: first, only walking flies can be observed - not flying - and second, although it enables population studies, tracking individual flies within the population is not currently possible. The system used video recording and an analog circuit to extract the average light changes as a function of time. Flies were held in a 5-cm diameter Petri dish and illuminated from below by a uniform light source. A miniature, monochrome CMOS (complementary metal-oxide semiconductor) video camera imaged the flies. This camera had automatic gain control, and this did not affect system performance. The camera was positioned 5-7 cm above the Petri dish such that the imaging area was 2.25 sq cm. With this basic setup, still images and continuous video of 15 flies at one time were obtained. To reduce the required data bandwidth by several orders of magnitude, a band-pass filter (0.3-10 Hz) circuit compressed the video signal and extracted changes in image luminance over time. The raw activity signal output of this circuit was recorded on a computer and digitally processed to extract the fly movement "events" from the waveform. These events corresponded to flies entering and leaving the image and were used for extracting activity parameters such as inter-event duration. The efficacy of the system in quantifying locomotor activity was evaluated by varying environmental temperature, then measuring the activity level of the flies.
Winner-take-all circuit selects best-match stored pattern. Prototype cascadable very-large-scale integrated (VLSI) circuit chips built and tested to demonstrate concept of electronic associative pattern recognition. Based on low-power, sub-threshold analog complementary oxide/semiconductor (CMOS) VLSI circuitry, each chip can store 128 sets (vectors) of 16 analog values (vector components), vectors representing known patterns as diverse as spectra, histograms, graphs, or brightnesses of pixels in images. Chips exploit parallel nature of vector quantization architecture to implement highly parallel processing in relatively simple computational cells. Through collective action, cells classify input pattern in fraction of microsecond while consuming power of few microwatts.
This paper presents a CMOS image sensor with focal-plane compression. The design has a column-level architecture and it is based on predictive coding techniques for image decorrelation. The prediction operations are performed in the analog domain to avoid quantization noise and to decrease the area complexity of the circuit, The prediction residuals are quantized and encoded by a joint quantizer/coder circuit. To save area resources, the joint quantizerlcoder circuit exploits common circuitry between a single-slope analog-to-digital converter (ADC) and a Golomb-Rice entropy coder. This combination of ADC and encoder allows the integration of the entropy coder at the column level. A prototype chip was fabricated in a 0.35 pm CMOS process. The output of the chip is a compressed bit stream. The test chip occupies a silicon area of 2.60 mm x 5.96 mm which includes an 80 X 44 APS array. Tests of the fabricated chip demonstrate the validity of the design.
An architecture for back-illuminated complementary metal oxide/semiconductor (CMOS) and charge-coupled-device (CCD) ultraviolet/visible/near infrared- light image sensors, and a method of fabrication to implement the architecture, are undergoing development. The architecture and method are expected to enable realization of the full potential of back-illuminated CMOS/CCD imagers to perform with high efficiency, high sensitivity, excellent angular response, and in-pixel signal processing. The architecture and method are compatible with next-generation CMOS dielectric-forming and metallization techniques, and the process flow of the method is compatible with process flows typical of the manufacture of very-large-scale integrated (VLSI) circuits. The architecture and method overcome all obstacles that have hitherto prevented high-yield, low-cost fabrication of back-illuminated CMOS/CCD imagers by use of standard VLSI fabrication tools and techniques. It is not possible to discuss the obstacles in detail within the space available for this article. Briefly, the obstacles are posed by the problems of generating light-absorbing layers having desired uniform and accurate thicknesses, passivation of surfaces, forming structures for efficient collection of charge carriers, and wafer-scale thinning (in contradistinction to diescale thinning). A basic element of the present architecture and method - the element that, more than any other, makes it possible to overcome the obstacles - is the use of an alternative starting material: Instead of starting with a conventional bulk-CMOS wafer that consists of a p-doped epitaxial silicon layer grown on a heavily-p-doped silicon substrate, one starts with a special silicon-on-insulator (SOI) wafer that consists of a thermal oxide buried between a lightly p- or n-doped, thick silicon layer and a device silicon layer of appropriate thickness and doping. The thick silicon layer is used as a handle: that is, as a mechanical support for the device silicon layer during micro-fabrication.
A new CMOS-based image sensor that is intrinsically compatible with on-chip CMOS circuitry is reported. The new CMOS active pixel image sensor achieves low noise, high sensitivity, X-Y addressability, and has simple timing requirements. The image sensor was fabricated using a 2 micrometer p-well CMOS process, and consists of a 128 x 128 array of 40 micrometer x 40 micrometer pixels. The CMOS image sensor technology enables highly integrated smart image sensors, and makes the design, incorporation and fabrication of such sensors widely accessible to the integrated circuit community.
Artificial neurons exhibiting volatile threshold switching and action potential‐like oscillations are crucial for brain‐inspired computing. While Complimentary Metal‐Oxide‐Semiconductor (CMOS)‐based strategies require hundreds of transistors to simulate each neuron, neuronal oscillations arise spontaneously in individual electro‐thermal devices due to nonlinearities like the Mott transition in VO 2 . Despite improved understanding of the physics, quantitative connections between neuronal performance and material properties remain under‐explored, preventing predictive neuron design and rational materials selection. In this work, a physics‐aware forward design methodology is developed for interrogating a wide palette of materials with properties varying by orders of magnitude, and their performance (high frequency, high dynamical reconfigurability and low power) under external circuit and device geometry constraints is assessed. The space of viable materials is identified to be much larger than previously recognized, with candidates from a range of materials classes, including Ge, GaP and MoS 2 . CMOS‐compatible performance (such as 100 GHz oscillating frequencies) can be achieved with CMOS‐compatible node sizes (≈10 nm). Finally, combinations of material properties yielding desired neuronal performance under uncertain design constraints are considered. This work solidifies forward design principles for electro‐thermal neuron devices, a necessary pre‐condition for inverse design from desired neuronal performance to required materials properties.
Tests showed that bipolar chips in the attitude control computer of the Galileo spacecraft would likely cause catastrophic mission failure due to single particle upset. This paper describes the design and testing of CMOS replacements which are speed compatible with the bipolar parts and are immune to upset by 165-MeV krypton ions.
Precision timing is a key requirement for emerging 4D particle tracking, Positron Emission Tomography (PET), beam and fusion plasma diagnostics, and other systems. Time-to-Digital Converters (TDCs) are commonly used to provide digital estimates of the relative timing between events, but the jitter performance of a TDC can be no better than the performance of the circuits that acquire the pulses and deliver them to the TDC. Several clock receiver and distribution circuits were evaluated, and a differential amplifier with resistive loads driving a pseudo-differential clock distribution network, developed using design guidelines for radiation tolerance and cryogenic compatibility, was fabricated as part of three prototypes: an analog front-end testbed chip for high-precision timing pixel readout, a dedicated TDC evaluation chip, and a Low-Gain Avalanche Detector (LGAD) readout circuit. Based on TDC measurements of the prototypes, we infer that the jitter added by the clock receiver and distribution circuits is less than 2.25 ps-rms. This performance meets the requirements of many future precision timing systems. The clock receiver and on-chip pseudo-differential driver were fabricated in commercial 28-nm CMOS technology and occupy 2288 µm 2 .
The standard cell design automation technique is described as an approach for generating random logic PMOS, CMOS or CMOS/SOS custom large scale integration arrays with low initial nonrecurring costs and quick turnaround time or design cycle. The system is composed of predesigned circuit functions or cells and computer programs capable of automatic placement and interconnection of the cells in accordance with an input data net list. The program generates a set of instructions to drive an automatic precision artwork generator. A series of support design automation and simulation programs are described, including programs for verifying correctness of the logic on the arrays, performing dc and dynamic analysis of MOS devices, and generating test sequences.
A complementary metal oxide/semiconductor (CMOS) image detector now undergoing development is designed to exhibit less cross-talk and greater full-well capacity than do prior CMOS image detectors of the same type. Imagers of the type in question are designed to operate from low-voltage power supplies and are fabricated by processes that yield device features having dimensions in the deep submicron range. Because of the use of low supply potentials, maximum internal electric fields and depletion widths are correspondingly limited. In turn, these limitations are responsible for increases in cross-talk and decreases in charge-handling capacities. Moreover, for small pixels, lateral depletion cannot be extended. These adverse effects are even more accentuated in a back-illuminated CMOS imager, in which photogenerated charge carriers must travel across the entire thickness of the device. The figure shows a partial cross section of the structure in the device layer of the present developmental CMOS imager. (In a practical imager, the device layer would sit atop either a heavily doped silicon substrate or a thin silicon oxide layer on a silicon substrate, not shown here.) The imager chip is divided into two areas: area C, which contains readout circuits and other electronic circuits; and area I, which contains the imaging (photodetector and photogenerated-charge-collecting) pixel structures. Areas C and I are electrically isolated from each other by means of a trench filled with silicon oxide. The electrical isolation between areas C and I makes it possible to apply different supply potentials to these areas, thereby enabling optimization of the supply potential and associated design features for each area. More specifically, metal oxide semiconductor field-effect transistors (MOSFETs) that are typically included in CMOS imagers now reside in area C and can remain unchanged from established designs and operated at supply potentials prescribed for those designs, while the dopings and the lower supply potentials in area I can be tailored to optimize imager performance. In area I, the device layer includes an n+ -doped silicon layer on which is grown an n-doped silicon layer. A p-doped silicon layer is grown on top of the n -doped layer. The total imaging device thickness is the sum of the thickness of the n+, n, and p layers. A pixel photodiode is formed between a surface n+ implant, a p implant underneath it, the aforementioned p layer, and the n and n+ layers. Adjacent to the diode is a gate for transferring photogenerated charges out of the photodiode and into a floating diffusion formed by an implanted p+ layer on an implanted n-doped region. Metal contact pads are added to the back-side for providing back-side bias.
This paper describes ongoing research and development of CMOS active pixel image sensors for low cost commercial applications. A number of sensor designs have been fabricated and tested in both p-well and n-well technologies. Major elements in the development of the sensor include on-chip analog signal processing circuits for the reduction of fixed pattern noise, on-chip timing and control circuits and on-chip analog-to-digital conversion (ADC). Recent results and continuing efforts in these areas will be presented.
Scaling superconducting digital circuits requires fundamental changes in the current material set and fabrication process. The transition to 300 mm wafers and the implementation of advanced lithography are instrumental in facilitating mature CMOS processes, ensuring uniformity, and optimizing the yield. Here, this study explores the properties of Nb x Ti (1–x) N films fabricated by magnetron DC sputtering on 300 mm Si wafers. As a promising alternative to traditional Nb in device manufacturing, Nb x Ti (1–x) N offers numerous advantages, including enhanced stability and scalability to smaller dimensions, in both processing and design. As a ternary material, Nb x Ti (1–x) N allows engineering material parameters by changing deposition conditions. The engineered properties can be used to modulate device parameters through the stack and mitigate failure modes. We report characterization of Nb x Ti (1–x) N films at less than 2% thickness variability, 2.4% T c variability and 3% composition variability. Film resistivity (140–375 Ωcm) shows a strong correlation with the film oxygen content, while the critical temperature T c (4.6 K–14.1 K) is strongly affected by film stoichiometry and its microstructure has only a moderate effect on modifying T c . Our results offer insights about the interplay between film stoichiometry, film microstructure and critical temperature.
A single-chip CMOS-based (complementary-metal-oxide-semiconductorbased) transmit/receive (T/R) module is being developed for L-band radar systems. Previous T/R module implementations required multiple chips employing different technologies (GaAs, Si, and others) combined with off-chip transmission lines and discrete components including circulators. The new design eliminates the bulky circulator, significantly reducing the size and mass of the T/R module. Compared to multi-chip designs, the single-chip CMOS can be implemented with lower cost. These innovations enable cost-effective realization of advanced phased array and synthetic aperture radar systems that require integration of thousands of T/R modules. The circulator is a ferromagnetic device that directs the flow of the RF (radio frequency) power during transmission and reception. During transmission, the circulator delivers the transmitted power from the amplifier to the antenna, while preventing it from damaging the sensitive receiver circuitry. During reception, the circulator directs the energy from the antenna to the low-noise amplifier (LNA) while isolating the output of the power amplifier (PA). In principle, a circulator could be replaced by series transistors acting as electronic switches. However, in practice, the integration of conventional series transistors into a T/R chip introduces significant losses and noise. The prototype single-chip T/R module contains integrated transistor switches, but not connected in series; instead, they are connected in a shunt configuration with resonant circuits (see figure). The shunt/resonant circuit topology not only reduces the losses associated with conventional semiconductor switches but also provides beneficial transformation of impedances for the PA and the LNA. It provides full singlepole/ double-throw switching for the antenna, isolating the LNA from the transmitted signal and isolating the PA from the received signal. During reception, the voltage on control line RX/TX (raised bar) is high, causing the field-effect transistor (FET) switch S1 to be closed, forming a parallel resonant tank circuit L1||C1. This circuit presents high impedance to the left of the antenna, so that the received signal is coupled to the LNA. At the same time, FET switches S2 and S3 are open, so that C2 is removed from the circuit (except for a small parasitic capacitance). The combination of L2 and C3 forms a matching network that transforms the antenna impedance of 50 ohms to a higher value from the perspective of the LNA input terminal. This transformation of impedance improves LNA noise figure by increasing the received voltage delivered to the input transistor. This allows lower transconductance and therefore a smaller transistor, which makes it possible to design the CMOS LNA for low power consumption. During transmission, the voltage on control line RX/TX (raised bar) is low, causing switch S1 to be open. In this configuration, the combination of L1 and C1 transforms the antenna impedance to a lower value from the perspective of the PA. This low impedance is helpful in producing a relatively high output power compatible with the low CMOS operating potential. At the same time, switches S2 and S3 are closed, forming the parallel resonant tank circuit L2||C2. This circuit presents high impedance to the right of the antenna, directing the PA output signal to the antenna and away from the LNA. During this time, S3 presents a short circuit across the LNA input terminals to guarantee that the voltage seen by the LNA is small enough to prevent damage.
The very large scale integration (VLSI) implementation of a fuzzy logic inference mechanism allows the use of rule-based control and decision making in demanding real-time applications. Researchers designed a full custom VLSI inference engine. The chip was fabricated using CMOS technology. The chip consists of 688,000 transistors of which 476,000 are used for RAM memory. The fuzzy logic inference engine board system incorporates the custom designed integrated circuit into a standard VMEbus environment. The Fuzzy Logic system uses Transistor-Transistor Logic (TTL) parts to provide the interface between the Fuzzy chip and a standard, double height VMEbus backplane, allowing the chip to perform application process control through the VMEbus host. High level C language functions hide details of the hardware system interface from the applications level programmer. The first version of the board was installed on a robot at Oak Ridge National Laboratory in January of 1990.