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NASA NTRS2018

Lessons Learned in the Flight Qualification of the S-NPP and NOAA-20 Solar Array Mechanisms

Deployable solar arrays are the energy source used on almost all Earth orbiting spacecraft and their release and deployment are mission-critical; fully testing them on the ground is a challenging endeavor. The 8 meter long deployable arrays flown on two sequential NASA weather satellites were each comprised of three rigid panels almost 2 meters wide. These large panels were deployed by hinges comprised of stacked constant force springs, eddy current dampers, and were restrained through launch by a set of four releasable hold-downs using shape memory alloy release devices. The ground qualification testing of such unwieldy deployable solar arrays, whose design was optimized for orbital operations, proved to be quite challenging and provides numerous lessons learned. A paperwork review and follow-up inspection after hardware storage determined that there were negative torque margins and missing lubricant, this paper will explain how these unexpected issues were overcome. The paper will also provide details on how the hinge subassemblies, the fully-assembled array, and mechanical ground support equipment were subsequently improved and qualified for a follow-on flight with considerably less difficulty. The solar arrays built by Ball Aerospace Corp. for the Suomi National Polar Partnership (S-NPP) satellite and the Joint Polar Satellite System (JPSS-1) satellite (now NOAA-20) were both successfully deployed on-obit and are performing well.

Helfrich, Daniel↗

NASA NTRS2018

Lessons Learned in the Flight Qualification of the S-NPP and NOAA-20 Solar Array Mechanisms

Deployable solar arrays are the energy source used on almost all Earth orbiting spacecraft and their release and deployment are mission-critical; fully testing them on the ground is a challenging endeavor. The 8 meter long deployable arrays flown on two sequential NASA weather satellites were each comprised of three rigid panels almost 2 meters wide. These large panels were deployed by hinges comprised of stacked constant force springs, eddy current dampers, and were restrained through launch by a set of four releasable hold-downs using shape memory alloy release devices. The ground qualification testing of such unwieldy deployable solar arrays, whose design was optimized for orbital operations, proved to be quite challenging and provides numerous lessons learned. A paperwork review and follow-up inspection after hardware storage determined that there were negative torque margins and missing lubricant, this paper will explain how these unexpected issues were overcome. The paper will also provide details on how the hinge subassemblies, the fully-assembled array, and mechanical ground support equipment were subsequently improved and qualified for a follow-on flight with considerably less difficulty. The solar arrays built by Ball Aerospace Corp. for the Suomi National Polar Partnership (SNPP) satellite and the Joint Polar Satellite System (JPSS-1) satellite (now NOAA-20) were both successfully deployed on-obit and are performing well.

Sexton, Adam↗

DOE OSTI2025

IRIS-MEMFLOW: Data Flow-Enabled Portable Memory Orchestration in IRIS Runtime for Diverse Heterogeneity

Task-based programming models and execution paradigms provide a means to decompose a computation by expressing it as a graph in which each node represents a specific computation operating on memory objects and the edges define the dependencies in the execution flow. In this execution model, independent nodes in the graph can be executed concurrently in different computing devices, making it suitable for heterogeneous systems in which computing devices with different architectures coexist. However, careful memory orchestration across heterogeneous devices is needed because copies of the same memory object may reside in multiple devices during execution. Manually ensuring such an orchestration is quite challenging. Not only must an application developer guard against race conditions, but they must also optimize data movement between the host and devices because unnecessary data movement significantly impacts performance. To mitigate these challenges, we enhance the IRIS heterogeneous runtime and introduce IRIS-MEMFLOW–a data flow–enabled portable memory abstraction for seamlessly orchestrating memory in diverse heterogeneous computing environments. By using data-flow analysis, IRIS-MEMFLOW guards against race conditions while multiple heterogeneous devices access memory objects. IRIS-MEMFLOW also optimizes data movement between the host and devices without manual intervention. As a result, IRIS provides improved programming productivity, performance, and portability for multidevice heterogeneous executions in high-performance computing and cloud systems that run diverse architectures from different vendors. The efficacy of IRIS-MEMFLOW is evaluated through experiments that show its capability in terms of programming productivity, multidevice heterogeneity, portability, and low overhead versus the state of the art.

Monil, M. A. H. [ORNL] (ORCID:0000000334194037)↗

NASA NTRS1972

Design, processing, and testing of lsi arrays for space station

The design of a MOS 256-bit Random Access Memory (RAM) is discussed. Technological achievements comprise computer simulations that accurately predict performance; aluminum-gate COS/MOS devices including a 256-bit RAM with current sensing; and a silicon-gate process that is being used in the construction of a 256-bit RAM with voltage sensing. The Si-gate process increases speed by reducing the overlap capacitance between gate and source-drain, thus reducing the crossover capacitance and allowing shorter interconnections. The design of a Si-gate RAM, which is pin-for-pin compatible with an RCA bulk silicon COS/MOS memory (type TA 5974), is discussed in full. The Integrated Circuit Tester (ICT) is limited to dc evaluation, but the diagnostics and data collecting are under computer control. The Silicon-on-Sapphire Memory Evaluator (SOS-ME, previously called SOS Memory Exerciser) measures power supply drain and performs a minimum number of tests to establish operation of the memory devices. The Macrodata MD-100 is a microprogrammable tester which has capabilities of extensive testing at speeds up to 5 MHz. Beam-lead technology was successfully integrated with SOS technology to make a simple device with beam leads. This device and the scribing are discussed.

Lile, W. R.↗

NASA NTRS1970

Improved solid state electron-charge-storage device

Storage device is applicable in memory systems and in high-resolution arrays for light-responsive image sensing. The device offers high yield in multiple arrays and allows charge release with light striking only the edge of a metal electrode.

Kuper, A. B.↗

NASA NTRS1991

Shape-memory alloy micro-actuator

A method of producing an integral piece of thermo-sensitive material, which is responsive to a shift in temperature from below to above a phase transformation temperature range to alter the material's condition to a shape-memory condition and move from one position to another. The method is characterized by depositing a thin film of shape-memory material, such as Nickel titanium (Ni-Ti) onto a substrate by vacuum deposition process such that the alloy exhibits an amorphous non-crystalline structure. The coated substrate is then annealed in a vacuum or in the presence of an inert atmosphere at a selected temperature, time and cool down rate to produce an ordered, partially disordered or fully disordered BCC structure such that the alloy undergoes thermoelastic, martinsetic phase transformation in response to alteration in temperature to pass from a martinsetic phase when at a temperature below a phase transformation range and capable of a high level of recoverable strain to a parent austenitic phase in a memory shape when at a temperature above the phase transformation range. Also disclosed are actuator devices employing shape-memory material actuators that deform from a set shape toward an original shape when subjected to a critical temperature level after having been initially deformed from the original shape into the set shape while at a lower temperature. The actuators are mechanically coupled to one or more movable elements such that the temperature-induce deformation of the actuators exerts a force or generates a motion of the mechanical element(s).

Busch, John D.↗

NASA NTRS2013

FY12 End of Year Report for NEPP DDR2 Reliability

This document reports the status of the NASA Electronic Parts and Packaging (NEPP) Double Data Rate 2 (DDR2) Reliability effort for FY2012. The task expanded the focus of evaluating reliability effects targeted for device examination. FY11 work highlighted the need to test many more parts and to examine more operating conditions, in order to provide useful recommendations for NASA users of these devices. This year's efforts focused on development of test capabilities, particularly focusing on those that can be used to determine overall lot quality and identify outlier devices, and test methods that can be employed on components for flight use. Flight acceptance of components potentially includes considerable time for up-screening (though this time may not currently be used for much reliability testing). Manufacturers are much more knowledgeable about the relevant reliability mechanisms for each of their devices. We are not in a position to know what the appropriate reliability tests are for any given device, so although reliability testing could be focused for a given device, we are forced to perform a large campaign of reliability tests to identify devices with degraded reliability. With the available up-screening time for NASA parts, it is possible to run many device performance studies. This includes verification of basic datasheet characteristics. Furthermore, it is possible to perform significant pattern sensitivity studies. By doing these studies we can establish higher reliability of flight components. In order to develop these approaches, it is necessary to develop test capability that can identify reliability outliers. To do this we must test many devices to ensure outliers are in the sample, and we must develop characterization capability to measure many different parameters. For FY12 we increased capability for reliability characterization and sample size. We increased sample size this year by moving from loose devices to dual inline memory modules (DIMMs) with an approximate reduction of 20 to 50 times in terms of per device under test (DUT) cost. By increasing sample size we have improved our ability to characterize devices that may be considered reliability outliers. This report provides an update on the effort to improve DDR2 testing capability. Although focused on DDR2, the methods being used can be extended to DDR and DDR3 with relative ease.

Guertin, Steven M.↗

DOE OSTI2024

When in-memory computing meets spiking neural networks—A perspective on device-circuit-system-and-algorithm co-design

This review explores the intersection of bio-plausible artificial intelligence in the form of spiking neural networks (SNNs) with the analog in-memory computing (IMC) domain, highlighting their collective potential for low-power edge computing environments. Through detailed investigation at the device, circuit, and system levels, we highlight the pivotal synergies between SNNs and IMC architectures. Additionally, we emphasize the critical need for comprehensive system-level analyses, considering the inter-dependencies among algorithms, devices, circuit, and system parameters, crucial for optimal performance. An in-depth analysis leads to the identification of key system-level bottlenecks arising from device limitations, which can be addressed using SNN-specific algorithm–hardware co-design techniques. This review underscores the imperative for holistic device to system design-space co-exploration, highlighting the critical aspects of hardware and algorithm research endeavors for low-power neuromorphic solutions.

Physics↗

NASA NTRS1990

Development of shape memory metal as the actuator of a fail safe mechanism

A small, compact, lightweight device was developed using shape memory alloy (SMA) in wire form to actuate a pin-puller that decouples the flanges of two shafts. When the SMA is heated it contracts producing a useful force and stroke. As it cools, it can be reset (elongated in this case) by applying a relatively small force. Resistive heating is accomplished by running a current through the SMA wire for a controlled length of time. The electronics to drive the device are not elaborate or complicated, consisting of a timed current source. The total available contraction is 3 percent of the length of the wire. This device, the engineering properties of the SMA, and the tests performed to verify the design concept are described.

Ford, V. G.↗

NASA NTRS1990

Spatial light modulators and applications III; Proceedings of the Meeting, San Diego, CA, Aug. 7, 8, 1989

Recent advances in the technology and applications of spatial light modulators (SLMs) are discussed in review essays by leading experts. Topics addressed include materials for SLMs, SLM devices and device technology, applications to optical data processing, and applications to artificial neural networks. Particular attention is given to nonlinear optical polymers, liquid crystals, magnetooptic SLMs, multiple-quantum-well SLMs, deformable-mirror SLMs, three-dimensional optical memories, applications of photorefractive devices to optical computing, photonic neurocomputers and learning machines, holographic associative memories, SLMs as parallel memories for optoelectronic neural networks, and coherent-optics implementations of neural-network models.

Efron, Uzi↗

NASA NTRS2011

Users Guide on Scaled CMOS Reliability: NASA Electronic Parts and Packaging (NEPP) Program Office of Safety and Mission Assurance

Reliability of advanced CMOS technology is a complex problem that is usually addressed from the standpoint of specific failure mechanisms rather than overall reliability of a finished microcircuit. A detailed treatment of CMOS reliability in scaled devices can be found in Ref. 1; it should be consulted for a more thorough discussion. The present document provides a more concise treatment of the scaled CMOS reliability problem, emphasizing differences in the recommended approach for these advanced devices compared to that of less aggressively scaled devices. It includes specific recommendations that can be used by flight projects that use advanced CMOS. The primary emphasis is on conventional memories, microprocessors, and related devices.

Scaled CMOS↗

NASA NTRS1977

Development of a high capacity bubble domain memory element and related epitaxial garnet materials for application in spacecraft data recorders. Item 1: Development of a high capacity memory element

Several versions of the 100K bit chip, which is configured as a single serial loop, were designed, fabricated and evaluated. Design and process modifications were introduced into each succeeding version to increase device performance and yield. At an intrinsic field rate of 150 KHz the final design operates from -10 C to +60 C with typical bias margins of 12 and 8 percent, respectively, for continuous operation. Asynchronous operation with first bit detection on start-up produces essentially the same margins over the temperature range. Cost projections made from fabrication yield runs on the 100K bit devices indicate that the memory element cost will be less than 10 millicents/bit in volume production.

Besser, P. J.↗

NASA NTRS2007

Two-Way Communication Using RFID Equipment and Techniques

Equipment and techniques used in radio-frequency identification (RFID) would be extended, according to a proposal, to enable short-range, two-way communication between electronic products and host computers. In one example of a typical contemplated application, the purpose of the short-range radio communication would be to transfer image data from a user s digital still or video camera to the user s computer for recording and/or processing. The concept is also applicable to consumer electronic products other than digital cameras (for example, cellular telephones, portable computers, or motion sensors in alarm systems), and to a variety of industrial and scientific sensors and other devices that generate data. Until now, RFID has been used to exchange small amounts of mostly static information for identifying and tracking assets. Information pertaining to an asset (typically, an object in inventory to be tracked) is contained in miniature electronic circuitry in an RFID tag attached to the object. Conventional RFID equipment and techniques enable a host computer to read data from and, in some cases, to write data to, RFID tags, but they do not enable such additional functions as sending commands to, or retrieving possibly large quantities of dynamic data from, RFID-tagged devices. The proposal would enable such additional functions. The figure schematically depicts an implementation of the proposal for a sensory device (e.g., a digital camera) that includes circuitry that converts sensory information to digital data. In addition to the basic sensory device, there would be a controller and a memory that would store the sensor data and/or data from the controller. The device would also be equipped with a conventional RFID chipset and antenna, which would communicate with a host computer via an RFID reader. The controller would function partly as a communication interface, implementing two-way communication protocols at all levels (including RFID if needed) between the sensory device and the memory and between the host computer and the memory. The controller would perform power V

Jedry, Thomas↗

DOE OSTI2025

Ultra-Fast Non-Volatile Resistive Switching Devices with Over 512 Distinct and Stable Levels for Memory and Neuromorphic Computing

Low-current multilevel programmability with inherent non-volatility and high stability of resistance states is required for both multi-bit memory storage and deep learning accelerators but is difficult to achieve. Here, in a resistive switching system, this work realizes >512 (>9 bits) distinct non-volatile conductance levels with stable retention for each state with current levels down to the nanoampere range, highly promising for potential integration with small processing nodes with ultra-low power consumption requirements. This is achieved by demonstrating a new thin film design concept that encompasses three key features: an ultra-thin epitaxial oxygen ionic switching layer that provides a tunable energy barrier at the bottom electrode, an overcoat amorphous layer that acts as an ion migration barrier for stable state retention, and a partial conductive filament as a localized electronic transport channel to the epitaxial switching layer. A large dynamic resistance range of up to seven orders of magnitude is achieved with reset-free transitions among intermediate states, and programmability is demonstrated with ultra-fast (20 ns) pulses. Artificial neural network (ANN) simulations, based on the experimental performance and its non-idealities, demonstrate close-to-ideal inference accuracies for various Modified National Institute of Standards and Technology (MNIST) data sets.

36 MATERIALS SCIENCE↗

NASA NTRS2010

Reconfigurable Fault Tolerance for FPGAs

The invention allows a field-programmable gate array (FPGA) or similar device to be efficiently reconfigured in whole or in part to provide higher capacity, non-redundant operation. The redundant device consists of functional units such as adders or multipliers, configuration memory for the functional units, a programmable routing method, configuration memory for the routing method, and various other features such as block RAM, I/O (random access memory, input/output) capability, dedicated carry logic, etc. The redundant device has three identical sets of functional units and routing resources and majority voters that correct errors. The configuration memory may or may not be redundant, depending on need. For example, SRAM-based FPGAs will need some type of radiation-tolerant configuration memory, or they will need triple-redundant configuration memory. Flash or anti-fuse devices will generally not need redundant configuration memory. Some means of loading and verifying the configuration memory is also required. These are all components of the pre-existing redundant FPGA. This innovation modifies the voter to accept a MODE input, which specifies whether ordinary voting is to occur, or if redundancy is to be split. Generally, additional routing resources will also be required to pass data between sections of the device created by splitting the redundancy. In redundancy mode, the voters produce an output corresponding to the two inputs that agree, in the usual fashion. In the split mode, the voters select just one input and convey this to the output, ignoring the other inputs. In a dual-redundant system (as opposed to triple-redundant), instead of a voter, there is some means to latch or gate a state update only when both inputs agree. In this case, the invention would require modification of the latch or gate so that it would operate normally in redundant mode, and would separately latch or gate the inputs in non-redundant mode.

Shuler, Robert, Jr.↗

NASA NTRS1990

Data storage technology comparisons

The role of data storage and data storage technology is an integral, though conceptually often underestimated, portion of data processing technology. Data storage is important in the mass storage mode in which generated data is buffered for later use. But data storage technology is also important in the data flow mode when data are manipulated and hence required to flow between databases, datasets and processors. This latter mode is commonly associated with memory hierarchies which support computation. VLSI devices can reasonably be defined as electronic circuit devices such as channel and control electronics as well as highly integrated, solid-state devices that are fabricated using thin film deposition technology. VLSI devices in both capacities play an important role in data storage technology. In addition to random access memories (RAM), read-only memories (ROM), and other silicon-based variations such as PROM's, EPROM's, and EEPROM's, integrated devices find their way into a variety of memory technologies which offer significant performance advantages. These memory technologies include magnetic tape, magnetic disk, magneto-optic disk, and vertical Bloch line memory. In this paper, some comparison between selected technologies will be made to demonstrate why more than one memory technology exists today, based for example on access time and storage density at the active bit and system levels.

Katti, Romney R.↗

DOE OSTI2024

CG-Kit: Code Generation Toolkit for performant and maintainable variants of source code applied to Flash-X hydrodynamics simulations

CG-Kit is a new Code Generation tool-Kit that we have developed as a part of the solution for portability and maintainability for multiphysics computing applications. The development of CG-Kit is rooted in the urgent need created by the shifting landscape of high-performance computing platforms and the algorithmic complexities of a particular large-scale multiphysics application: Flash-X. To efficiently use computing resources on a heterogeneous node, an application must have a map of computation to resources and a mechanism to move the data and computation to the resources according to the map. Most existing performance portability solutions are focussed on abstracting the expression of computations so that a unified source code can be specialized to run on different resources. However, such an approach is insufficient for a code like Flash-X, which has a multitude of code components that can be assembled in various permutations and combinations to form different instances of applications. Similar challenges apply to any code that has composability, where a single specified way of apportioning work among devices may not be optimal. Additionally, use cases arise where the optimal control flow of computation may differ for different devices while the underlying numerics remain identical. This combination leads to unique challenges including handling an existing large code base in Fortran and/or C/C++, subdivision of code into a great variety of units supporting a wide range of physics and numerical methods, different parallelization techniques for distributed and shared memory systems and accelerator devices, and heterogeneity of computing platforms requiring coexisting variants of parallel algorithms. All of these challenges demand that scientific software developers apply existing knowledge about domain applications, algorithms, and computing platforms to determine custom abstractions and granularity for code generation. There is a critical lack of tools to tackle those problems. CG-Kit is designed to fill this gap by providing a user with the ability to express their desired control flow and computation-to-resource map in the form a pseudocode-like recipe. It consists of standalone tools that can be combined into highly specific and, we argue, highly effective portability and maintainability toolchains. Here we present the design of our new tools: parametrized source trees, control flow graphs, and recipes. The tools are implemented in Python. They are agnostic to the programming language of the source code targeted for code generation. In conclusion, we demonstrate the capabilities of the toolkit with two examples, first, multithreaded variants of the basic AXPY operation, and second, variants of parallel algorithms within a hydrodynamics solver, called Spark, from Flash-X that operates on block-structured adaptive meshes.

Algorithmic portability↗

NASA NTRS2016

Recent Advances in Commercial Memories and Potential Contribution to GN&C Miniaturation

The last few years have seen a surge in technology, device, and architecture introductions in commercial memories such as SDRAM and NAND driven by the explosion of handheld and portable electronics. Some of the resultant devices provide high density in very small and light packages, which may be possible to leverage for the miniaturization of future GN&C systems in addition to providing considerable memory capacity to enable advanced capabilities such as image-based navigation or adaptive/autonomous operations. We will show that these advanced SDRAM and NAND technologies are worth serious consideration for the next generation of GN&C needs by highlighting reliability and radiation effects results from some of these devices.

Yang-Scharlotta, Jean Y.↗