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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 271 records · Page 15
All sourcesNASA NTRSDOE OSTI
NASA NTRS2003

Curved Focal-Plane Arrays Using Back-Illuminated High-Purity Photodetectors

Curved-focal-plane arrays of back-illuminated silicon-based photodetectors are being developed. The basic idea is to improve the performance of an imaging instrument and simplify the optics needed to obtain a given level of performance by making an image sensor (e.g., a photographic film or an array of photodetectors) conform to a curved focal surface, instead of following the customary practice of designing the optics to project an image onto a flat focal surface. Eyes are natural examples of optical systems that have curved focal surfaces on which image sensors (retinas) are located. One prior approach to implementation of this concept involves the use of curved-input-surface microchannel plates as arrays of photodetectors. In comparison with microchannel plates, these curved-focal-plane arrays would weigh less, operate at much lower voltages, and consume less power. It should also be possible to fabricate the proposed devices at lower cost. It would be possible to fabricate an array of photodetectors and readout circuitry in the form of a very-large-scale integrated (VLSI) circuit on a curved focal surface, but it would be difficult and expensive to do so. In a simple and inexpensive alternate approach, a device (see figure) would have (1) a curved back surface, onto which light would be focused; and (2) a flat front surface, on which VLSI circuitry would be fabricated by techniques that are well established for flat surfaces. The device would be made from ultrapure silicon, in which it is possible to form high-resistivity, thick photodetectors that are fully depleted through their thicknesses. (As used here, "thick means having a thickness between a fraction of a millimeter and a few millimeters.) The back surface would be polished to the curvature of the focal surface of the intended application. To enable the collection of charge carriers excited by photons near the back surface or in the bulk of the device, it would be necessary to form a transparent or semitransparent back-surface electrode, possibly by delta doping. [Delta doping is so named because its density-vs.-depth characteristic is reminiscent of the Dirac function (impulse function): the dopant is concentrated in a very thin layer - nominally, a single atomic layer.]

Nikzad, Shouleh↗
NASA NTRS2009

Sequential Principal Component Analysis -An Optimal and Hardware-Implementable Transform for Image Compression

This paper presents the JPL-developed Sequential Principal Component Analysis (SPCA) algorithm for feature extraction / image compression, based on "dominant-term selection" unsupervised learning technique that requires an order-of-magnitude lesser computation and has simpler architecture compared to the state of the art gradient-descent techniques. This algorithm is inherently amenable to a compact, low power and high speed VLSI hardware embodiment. The paper compares the lossless image compression performance of the JPL's SPCA algorithm with the state of the art JPEG2000, widely used due to its simplified hardware implementability. JPEG2000 is not an optimal data compression technique because of its fixed transform characteristics, regardless of its data structure. On the other hand, conventional Principal Component Analysis based transform (PCA-transform) is a data-dependent-structure transform. However, it is not easy to implement the PCA in compact VLSI hardware, due to its highly computational and architectural complexity. In contrast, the JPL's "dominant-term selection" SPCA algorithm allows, for the first time, a compact, low-power hardware implementation of the powerful PCA algorithm. This paper presents a direct comparison of the JPL's SPCA versus JPEG2000, incorporating the Huffman and arithmetic coding for completeness of the data compression operation. The simulation results show that JPL's SPCA algorithm is superior as an optimal data-dependent-transform over the state of the art JPEG2000. When implemented in hardware, this technique is projected to be ideally suited to future NASA missions for autonomous on-board image data processing to improve the bandwidth of communication.

Duong, Tuan A.↗
NASA NTRS1996

(abstract) A High Throughput 3-D Inner Product Processor

A particularily challenging image processing application is the real time scene acquisition and object discrimination. It requires spatio-temporal recognition of point and resolved objects at high speeds with parallel processing algorithms. Neural network paradigms provide fine grain parallism and, when implemented in hardware, offer orders of magnitude speed up. However, neural networks implemented on a VLSI chip are planer architectures capable of efficient processing of linear vector signals rather than 2-D images. Therefore, for processing of images, a 3-D stack of neural-net ICs receiving planar inputs and consuming minimal power are required. Details of the circuits with chip architectures will be described with need to develop ultralow-power electronics. Further, use of the architecture in a system for high-speed processing will be illustrated.

imaging parallel processing algorithms linear vect↗
NASA NTRS1994

Fluorine Implantation and Residual Stresses in Polysilicon Films

As microelectronic device dimensions are reduced below one micron, the hot carrier effect is a major barrier to continued scaling and VLSI reliability. Several reports have shown that fluorine diffusion into the device gate greatly enhances the resistance to hot carriers. There has been some disagreement as to the mechanism of influence; however, several reports have suggested that the polysilicon is physically modified by the fluorine implant and that the beneficial effects are at least in part due to stress relaxation in the polysilicon.

polysilicon fluorine microelectronic devices hot c↗
NASA NTRS1996

On-board Neural Processor Design for an Intelligent Multi-sensor Microspacecraft

A compact VLSI neural processor based on the Optimization Cellular Neural Network (OCNN)has been under development to provide a wide range of support for an intelligent remote sensing microspacecraft which requires both high bandwidth communication and high-performance computing for on-board data analysis, thematic data reduction, synergy of multiple types of sensors, and other smart-sensor functions. The OCNN architecture is a programmable multi-dimensional array of neurons which are locally connected with their local neurons. The OCNN operation theory, architecture, design and implementation, prototype chip, and system applications have been investigated in detail and presented in this paper.

array↗
DOE OSTI2024

Reliable edge machine learning hardware for scientific applications

Extreme data rate scientific experiments create massive amounts of data that require efficient ML edge processing. This leads to unique validation challenges for VLSI implementations of ML algorithms: enabling bit-accurate functional simulations for performance validation in experimental software frameworks, verifying those ML models are robust under extreme quantization and pruning, and enabling ultra-fine-grained model inspection for efficient fault tolerance. We discuss approaches to developing and validating reliable algorithms at the scientific edge under such strict latency, resource, power, and area requirements in extreme experimental environments. We study metrics for developing robust algorithms, present preliminary results and mitigation strategies, and conclude with an outlook of these and future directions of research towards the longer-term goal of developing autonomous scientific experimentation methods for accelerated scientific discovery.

Baldi, Tommaso↗
DOE OSTI2024

Post-processing of phase change material in a zero-change commercial silicon photonic process

Integration of phase change material (PCM) with photonic integrated circuits can transform large-scale photonic systems by providing non-volatile control over phase and amplitude. The next generation of commercial silicon photonic processes can benefit from the addition of PCM to enable ultra-low power, highly reconfigurable, and compact photonic integrated circuits for large-scale applications. Despite all the advantages of PCM-based photonics, today’s commercial foundries do not provide them in their silicon photonic processes yet. We demonstrate the first-ever electrically programmable PCM device that is monolithically post-processed in a commercial foundry silicon photonics process using a few fabrication steps and coarse-resolution photolithography. These devices achieved 1.4 dB/μm of amplitude switching contrast using a thin layer of 12.5 nm GeSbTe in this work. We have also characterized the reconfiguration speed as well as repeatability of these devices over 20,000 switching cycles. Our solution enables non-volatile photonic VLSI systems that can be fabricated at low cost and high reliability in a commercial foundry process, paving the way for the development of non-volatile programmable photonic integrated circuits for a variety of emerging applications.

Optics↗
NASA NTRS1978

A study of standard building blocks for the design of fault-tolerant distributed computer systems

This paper presents the results of a study that has established a standard set of four semiconductor VLSI building-block circuits. These circuits can be assembled with off-the-shelf microprocessors and semiconductor memory modules into fault-tolerant distributed computer configurations. The resulting multi-computer architecture uses self-checking computer modules backed up by a limited number of spares. A redundant bus system is employed for communication between computer modules.

Rennels, D. A.↗
NASA NTRS1981

Fault-tolerant computer study

A set of building block circuits is described which can be used with commercially available microprocessors and memories to implement fault tolerant distributed computer systems. Each building block circuit is intended for VLSI implementation as a single chip. Several building blocks and associated processor and memory chips form a self checking computer module with self contained input output and interfaces to redundant communications buses. Fault tolerance is achieved by connecting self checking computer modules into a redundant network in which backup buses and computer modules are provided to circumvent failures. The requirements and design methodology which led to the definition of the building block circuits are discussed.

Rennels, D. A.↗
NASA NTRS1981

Concepts for on-board satellite image registration. Volume 3: Impact of VLSI/VHSIC on satellite on-board signal processing

Anticipated major advances in integrated circuit technology in the near future are described as well as their impact on satellite onboard signal processing systems. Dramatic improvements in chip density, speed, power consumption, and system reliability are expected from very large scale integration. Improvements are expected from very large scale integration enable more intelligence to be placed on remote sensing platforms in space, meeting the goals of NASA's information adaptive system concept, a major component of the NASA End-to-End Data System program. A forecast of VLSI technological advances is presented, including a description of the Defense Department's very high speed integrated circuit program, a seven-year research and development effort.

Aanstoos, J. V.↗
NASA NTRS1979

High density circuit technology

Polyimide dielectric materials were acquired for comparative and evaluative studies in double layer metal processes. Preliminary experiments were performed. Also, the literature indicates that sputtered aluminum films may be successfully patterned using the left-off technique provided the substrate temperature remains low and the argon pressure in the chamber is relatively high at the time of sputtering. Vendors associated with dry processing equipment are identified. A literature search relative to future trends in VLSI fabrication techniques is described.

Wade, T. E.↗
NASA NTRS1981

Modular hardware synthesis using an HDL

Although hardware description languages (HDL) are becoming more and more necessary to automated design systems, their application is complicated due to the difficulty in translating the HDL description into an implementable format, nonfamiliarity of hardware designers with high-level language programming, nonuniform design methodologies and the time and costs involved in transfering HDL design software. Digital design language (DDL) suffers from all of the above problems and in addition can only by synthesized on a complete system and not on its subparts, making it unsuitable for synthesis using standard modules or prefabricated chips such as those required in LSI or VLSI circuits. The present paper presents a method by which the DDL translator can be made to generate modular equations that will allow the system to be synthesized as an interconnection of lower-level modules. The method involves the introduction of a new language construct called a Module which provides for the separate translation of all equations bounded by it.

Covington, J. A.↗
NASA NTRS1981

SAR processing on the MPP

The processing of synthetic aperture radar (SAR) signals using the massively parallel processor (MPP) is discussed. The fast Fourier transform convolution procedures employed in the algorithms are described. The MPP architecture comprises an array unit (ARU) which processes arrays of data; an array control unit which controls the operation of the ARU and performs scalar arithmetic; a program and data management unit which controls the flow of data; and a unique staging memory (SM) which buffers and permutes data. The ARU contains a 128 by 128 array of bit-serial processing elements (PE). Two-by-four surarrays of PE's are packaged in a custom VLSI HCMOS chip. The staging memory is a large multidimensional-access memory which buffers and permutes data flowing with the system. Efficient SAR processing is achieved via ARU communication paths and SM data manipulation. Real time processing capability can be realized via a multiple ARU, multiple SM configuration.

Batcher, K. E.↗
NASA NTRS1980

High density circuit technology

Acquisition of polyimide materials for inter-metal dielectrics was obtained from three vendors, with considerable evaluation conducted on the Dupont PI2550 material. Experimental results indicate this material can be patterned using contact printing to line width far below 0.1 mils. Optimum line width is acquired using plasma etch equipment. Metal lift-off experiments on thermal evaporated films were optimized for application to sputtered deposited films. Alternate metal-lift-off experiments are proposed for future investigation. Dry processing equipment studies and future trends in VLSI fabrication techniques are on-going.

Wade, T. E.↗
NASA NTRS1982

Design approach for a microprocessor-based GPS time transfer receiver

The design concept and characteristics of a self-contained microprocessor-based Global Positioning System time transfer receiver is described. A prototype of this unit is currently in the test phase. It employs two-bit digital baseband correlation rather than analog IF correlation of the signals with the reference code. The correlator, numerically controlled oscillators and code generator are implemented in a special-purpose digital signal processor. The time is recovered in the digital code tracking loop, and final corrections are applied in the control processor. Other features of this design are: (1) drift-free digital mechanization; (2) high reliability of digital circuits; (3) flexible control capability of the microprocessor; and (4) potential for a high degree of digital VLSI chip development leading to compact, low-cost units.

Ould, P. C.↗
NASA NTRS1981

Annual Conference on Nuclear and Space Radiation Effects, 18th, University of Washington, Seattle, WA, July 21-24, 1981, Proceedings

Single event upset phenomena are discussed, taking into account cosmic ray induced errors in IIL microprocessors and logic devices, single event upsets in NMOS microprocessors, a prediction model for bipolar RAMs in a high energy ion/proton environment, the search for neutron-induced hard errors in VLSI structures, soft errors due to protons in the radiation belt, and the use of an ion microbeam to study single event upsets in microcircuits. Basic mechanisms in materials and devices are examined, giving attention to gamma induced noise in CCD's, the annealing of MOS capacitors, an analysis of photobleaching techniques for the radiation hardening of fiber optic data links, a hardened field insulator, the simulation of radiation damage in solids, and the manufacturing of radiation resistant optical fibers. Energy deposition and dosimetry is considered along with SGEMP/IEMP, radiation effects in devices, space radiation effects and spacecraft charging, EMP/SREMP, and aspects of fabrication, testing, and hardness assurance.

Tasca, D. M.↗