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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 271 records · Page 15
All sourcesNASA NTRSDOE OSTI
NASA NTRS1988

Laser Doppler velocimeter multiplexer interface for simultaneous measured events

An Laser Doppler Velocimeter multiplexer interface (20) includes an event pulse synchronizer (162), which synchronizes data pulses from events A, B and C. Clock control (164) is connected to receive timing information on the data pushes from the synchronizer (162). Displays (24, 26, 28) are connected to receive clock signals from the clock control (164) for indicating a data rate for each of the measured events A, B and C. Display (3) is connected to receive clock signals form the clock control (164) to indicate a coincidence rate between data pulses for any selected combination of the measured events A, B and C. A multiplexer (156) receives the data pulses from the events A, B and C and rate data from the clock control (164). Multiplexer (156) has output (180) for supplying the data pulses and rate data to a single input of a data processing system. A multiplexer control (158) is connected to supply control signals to the multiplexer (156) for selecting the event data pulses and the rate data for output from the multiplexer (156). Multiplexer control (158) receives start signals from the pulse synchronizer (162) and user selected inputs for desired outputs from the multiplexer (156).

Dean R Harrison↗
DOE OSTI2025

RFSoC based digital low level RF control firmware and software suite (mimo_llrf) v1.0

It features a framework of a firmware and software architecture in support of building a digital low-level RF control system for accelerators, where precised digital RF generation and measurement are needed across many RF channels. It primarily supports the Xilinx RFSoC chips (xczu48dr, xczu47dr, xczu29dr) and their evaluation boards (zcu208, zcu216), for a highly integrated solution enabling the need for synchronous low-level RF systems, including: multi-tile synchronization, external reference for sampling clocks, deterministic delay, aligned NCO phase for digital mixers, and built-in EPICS IOC.

Du, Qiang [Lawrence Berkeley National Laboratory (↗
NASA NTRS1966

Electronic phase-locked-loop speed control system is stable

Phase locked-loop circuit is used for playback motors in digital tape recorders where the reproducer output remains in exact synchronism with an external reference clock over extended periods. It removes the motor dynamics from the control loop so that the loop is stable without damping.

Stone, F. A.↗
NASA NTRS1980

Redundant operation of counter modules

A technique for the redundant operation of counter modules is described. Redundant operation is maintained by detecting the zero state of each counter and clearing the other to that state, thus periodically resynchronizing the counters, and obtaining an output from both counters through AC coupled diode-OR gates. Redundant operation of counter flip flops is maintained in a similar manner, and synchronous operation of redundant squarewave clock generators of the feedback type is effected by connecting together the feedback inputs of the squarewave generators through a coupling resistor, and obtaining an output from both generators through AC coupled diode-OR gates.

Nagano, S.↗
NASA NTRS1991

Highly parallel computer architecture for robotic computation

In a computer having a large number of single instruction multiple data (SIMD) processors, each of the SIMD processors has two sets of three individual processor elements controlled by a master control unit and interconnected among a plurality of register file units where data is stored. The register files input and output data in synchronism with a minor cycle clock under control of two slave control units controlling the register file units connected to respective ones of the two sets of processor elements. Depending upon which ones of the register file units are enabled to store or transmit data during a particular minor clock cycle, the processor elements within an SIMD processor are connected in rings or in pipeline arrays, and may exchange data with the internal bus or with neighboring SIMD processors through interface units controlled by respective ones of the two slave control units.

Fijany, Amir↗
NASA NTRS1991

Personal communications via ACTS satellite HBR transponders

The concept of a fully meshed network of briefcase-sized terminals is presented for personal communications over Ka-band satellite transponders. In this concept, undesirable double-hop delays are avoided for voice communications. The bandwidth and power resources of the transponder are efficiently shared by users in a simple demand-assigned manner via code-division multiple access (CDMA). Voice, data, and facsimile are statistically multiplexed at each terminal. In order to minimize terminal costs, frequency-precorrected, and level-preadjusted continuous-wave tones are sent from the central network control station in each beam so that the terminals in each down-link beam can use these pilots as references for antenna acquisition and tracking, as reliable frequency sources, and as indicators of signal fade for up-link power control (ULPC). The potential CDMA 'near-far' problem due to up-link fades is mitigated by using ULPC. Quasi-burst mode transmission is employed to minimize the potential clock and pseudorandom number code synchronization.

Fang, Russell J. F.↗
NASA NTRS1992

A gallium-arsenide digital phase shifter for clock and control signal distribution in high-speed digital systems

The design, implementation, testing, and applications of a gallium-arsenide digital phase shifter and fan-out buffer are described. The integrated circuit provides a method for adjusting the phase of high-speed clock and control signals in digital systems, without the need for pruning cables, multiplexing between cables of different lengths, delay lines, or similar techniques. The phase of signals distributed with the described chip can be dynamically adjusted in eight different steps of approximately 60 ps per step. The IC also serves as a fan-out buffer and provides 12 in-phase outputs. The chip is useful for distributing high-speed clock and control signals in synchronous digital systems, especially if components are distributed over a large physical area or if there is a large number of components.

Fouts, Douglas J.↗
NASA NTRS1993

Asynchronous timing and Doppler recovery in DSP based DPSK modems for fixed and mobile satellite applications

While conventional analog modems employ some kind of clock wave regenerator circuit for synchronous timing recovery, in sampled modem receivers the timing is recovered asynchronously to the incoming data stream, with no adjustment being made to the input sampling rate. All timing corrections are accomplished by digital operations on the sampled data stream, and timing recovery is asynchronous with the uncontrolled, input A/D system. A good timing error measurement algorithm is a zero crossing tracker proposed by Gardner. Digital, speech rate (2400 - 4800 bps) M-PSK modem receivers employing Gardner's zero crossing tracker were implemented and tested and found to achieve BER performance very close to theoretical values on the AWGN channel. Nyguist pulse shaped modem systems with excess bandwidth factors ranging from 100 to 60 percent were considered. We can show that for any symmetric M-PSK signal set Gardner's NDA algorithm is free of pattern jitter for any carrier phase offset for rectangular pulses and for Nyquist pulses having 100 percent excess bandwidth. Also, the Nyquist pulse shaped system is studied on the mobile satellite channel, where Doppler shifts and multipath fading degrade the pi/4-DQPSK signal. Two simple modifications to Gardner's zero crossing tracker enable it to remain useful in the presence of multipath fading.

Koblents, B.↗
NASA NTRS1994

Highly parallel reconfigurable computer architecture for robotic computation having plural processor cells each having right and left ensembles of plural processors

In a computer having a large number of single-instruction multiple data (SIMD) processors, each of the SIMD processors has two sets of three individual processor elements controlled by a master control unit and interconnected among a plurality of register file units where data is stored. The register files input and output data in synchronism with a minor cycle clock under control of two slave control units controlling the register file units connected to respective ones of the two sets of processor elements. Depending upon which ones of the register file units are enabled to store or transmit data during a particular minor clock cycle, the processor elements within an SIMD processor are connected in rings or in pipeline arrays, and may exchange data with the internal bus or with neighboring SIMD processors through interface units controlled by respective ones of the two slave control units.

Fijany, Amir↗
NASA NTRS2009

Inter-Symbol Guard Time for Synchronizing Optical PPM

An inter-symbol guard time has been proposed as a means of synchronizing the symbol and slot clocks of an optical pulse-position modulation (PPM) receiver with the symbol and slot periods of an incoming optical PPM signal.The proposal is applicable to the low-flux case in which the receiver photodetector operates in a photon-counting mode and the count can include contributions from incidental light sources and dark current.

Far, William↗
NASA NTRS2018

International Space Station Future Correlation Analysis Improvements

Ongoing modal analyses and model correlation are performed on different configurations of the International Space Station (ISS). These analyses utilize on-orbit dynamic measurements collected using four main ISS instrumentation systems: External Wireless Instrumentation System (EWIS), Internal Wireless Instrumentation System (IWIS), Space Acceleration Measurement System (SAMS), and Structural Dynamic Measurement System (SDMS). Remote Sensor Units (RSUs) are network relay stations that acquire flight data from sensors. Measured data is stored in the Remote Sensor Unit (RSU) until it receives a command to download data via RF to the Network Control Unit (NCU). Since each RSU has its own clock, it is necessary to synchronize measurements before analysis. Imprecise synchronization impacts analysis results. A study was performed to evaluate three different synchronization techniques: (i) measurements visually aligned to analytical time-response data using model comparison, (ii) Frequency Domain Decomposition (FDD), and (iii) lag from cross-correlation to align measurements. This paper presents the results of this study.

time synchronization↗
NASA NTRSDate not supplied

Navigation Doppler Lidar Signal Processing Architecture and Algorithms

A coherent Doppler lidar has been developed to address the need for a high-performance, compact, and cost-effective velocity and altitude sensor onboard landing vehicles. One of the core subsystems within NDL is its signal processing architecture. The primary function of this subsystem is to digitize the analog output of the homodyned signal received from the photo-diode associated with each telescope, process this signal in the frequency domain, and then turn this information into velocity and range measurements. A secondary function of this subsystem is to setup and control the internal components within NDL and to enable the instrument to interface with external systems by receiving commands, sending telemetry, and synchronizing its measurements with external clocks and pulses. This paper will give an overview of the signal processing architecture within NDL. This will include a discussion on its fundamental processing components and the core signal processing algorithms. Command, telemetry and internal component controls will also be discussed as will how the signal processing architecture has also evolved over the years of development. We will discuss provisions for robust operation including Triple-Mode Redundancy (TMR) within NDL’s Field Programmable Gate Array (FPGA) and storage elements, a fault-tolerant boot process, and Error Detection and Correction (EDAC) on the Static Random-Access Memories (SRAMs). Finally, we conclude this paper with how this architecture could continue to evolve.

Doppler Lidar↗
NASA NTRS2023

LunaNet Position, Navigation, and Timing Services and Signal, Enabling the Future of Lunar Exploration

The International Space Exploration Coordination Group established in 2018 the 3rd edition of the Global Exploration Roadmap (ISECG, 2018) that aims to achieve Mars human surface activities and identifies the exploration of the Moon as a critical intermediate step. A supplement covering updates on surface exploration scenarios was released in 2020 (ISECG, 2020). The Artemis Accords (NASA Artemis, 2020), first signed in October 2020, now includes over two dozen nations, in an agreement on the principles for best practices, including interoperability. September 2022 introduced the National Aeronautics and Space Administration’s (NASA) Moon to Mars Objectives highlighting recurring tenets of collaboration with international and industry partners and interoperability, along with infrastructure objectives for Position, Navigation, and Timing (PNT). The successful Artemis 1 mission paved the way to the ambitious plans to establish a sustainable human presence on the Moon. Just a few months after Artemis 1 launch (NASA, 2022), iSpace HAKUTO-R Mission1 (iSpace, 2022) launched, being the first-ever commercial mission, launched by a commercial launch service provider, aiming to land on the lunar surface. The NASA Artemis programme plans initial crewed landings and traverses in 2025, supported by the Lunar Gateway, followed by regular launches to build the lunar systems (NASA Artemis Plan, 2020), (NASA, 2022). NASA’s contracts with Commercial Lunar Payload Services (CLPS, (NASA, n.d.)) to deliver science and technology to the Moon, with launches starting in November 2023. The European Space Agency (ESA) Argonaut (ESA Argonaut, 2022) programme plans to have recurrent missions to bring payloads to the lunar surface, supporting lunar exploration. These are just a few examples of planned missions that will target the Earth’s natural satellite in the next decade, with forecasts of tens of missions per year (NSR, 2022), (Euroconsult, 2020). The large number of missions and the complexity of landing and operating are expected to demand a change of paradigm from the current Earth-based communication and navigation services. In recent years, several agencies have proposed to deploy cislunar communication and navigation services to support lunar missions (NASA LCRNS, 2022), (ESA Moonlight, 2022), (JAXA, 2022)). All these proposals seek to deploy service-providing satellites in lunar orbit to ease the user missions’ operations. The PNT services objective is to support all types of lunar users (e.g.: orbiters, landers, ascent vehicles, and surface crew and rovers). At the same time, NASA and ESA initiated an effort to define a common framework to ensure interoperability among different service providers: the LunaNet framework. The LunaNet Interoperability Specification (NASA and ESA, 2023) covers communication, PNT, and auxiliary services, by establishing a common set of requirements to ensure interoperability. This conference contribution will present the LunaNet PNT services, focusing on the Lunar Augmented Navigation Service (LANS) that resembles the Global Navigation Satellite System (GNSS) concept on Earth: constellations of satellites broadcasting a radio navigation signal synchronized to a common reference clock, with augmentations to accommodate users’ needs in an environment away from Earth. This includes a description of the high-level LANS concept and the basic principles defined to ensure interoperability. In addition, it will describe the common S-band PNT Augmented Forward Signal (AFS) and common messages to be adopted for compliance with the LunaNet framework, and the justification of the selected approach.

LunaNet↗
NASA NTRS2023

Lunanet Position, Navigation, and Timing Services and Signals, Enabling the Future of Lunar Exploration

The International Space Exploration Coordination Group established in 2018 the 3rd edition of the Global Exploration Roadmap (ISECG, 2018) that aims to achieve Mars human surface activities and identifies the exploration of the Moon as a critical intermediate step. A supplement covering updates on surface exploration scenarios was released in 2020 (ISECG, 2020). The Artemis Accords (NASA Artemis, 2020), first signed in October 2020, now includes over two dozen nations, in an agreement on the principles for best practices, including interoperability. In September 2022 the National Aeronautics and Space Administration (NASA) introduced the Moon to Mars Objectives highlighting recurring tenets of collaboration with international and industry partners and interoperability, along with infrastructure objectives for Position, Navigation, and Timing (PNT). The successful Artemis 1 mission paved the way to the ambitious plans to establish a sustainable human presence on the Moon. Just a few months after Artemis 1 launch (NASA, 2022), iSpace HAKUTO-R Mission1 (iSpace, 2022) launched, being the first-ever mission launched by a commercial launch service provider aiming to land on the lunar surface. The NASA Artemis program plans initial crewed landings and surface traverses in 2025, supported by the Lunar Gateway. Regular launches will follow to build the lunar systems for a sustained presence as presented in the Artemis Plan (NASA Artemis Plan, 2020), (NASA, 2022). NASA’s contracts with commercial providers through the Commercial Lunar Payload Services program (CLPS, (NASA, n.d.)) will deliver science and technology demonstration missions to the Moon starting in November 2023. The European Space Agency (ESA) Argonaut (ESA Argonaut, 2022) program plans to have recurrent missions to bring payloads to the lunar surface, supporting lunar exploration. These are just a few examples of planned missions that will target Earth’s natural satellite in the next decade, with forecasts of tens of missions per year (NSR, 2022), (Euroconsult, 2020). The large number of missions and the complexity of landing and operating are expected to demand a change of paradigm from the current Earth-based communication and navigation services, that may be combined with onboard sensors. In recent years, several agencies have proposed to deploy cislunar communication and navigation services to support lunar missions (NASA LCRNS, 2022), (ESA Moonlight, 2022), (JAXA, 2022)). All these proposals seek to deploy service-providing satellites in lunar orbit to ease the user missions’ operations. The PNT services objective is to support all types of lunar users (e.g.: orbiters, landers, ascent vehicles, surface crew, rovers, and deployed science payloads). At the same time, NASA and ESA initiated an effort to define a common framework to ensure interoperability among different service providers: the LunaNet framework. The LunaNet Interoperability Specification (NASA and ESA, 2023) covers communication, PNT, and auxiliary services, by establishing a common set of requirements to ensure interoperability. This conference contribution will present the LunaNet PNT services, focusing on the Lunar Augmented Navigation Service (LANS) that would be provided by a system that resembles the Global Navigation Satellite System (GNSS) concept on Earth: constellations of satellites broadcasting a radio navigation signal synchronized to a common reference clock, with augmentations to accommodate users’ needs in an environment away from Earth. This paper includes a description of the high-level LANS concept, and the basic principles defined to ensure interoperability. In addition, it will describe the common S-band PNT Augmented Forward Signal (AFS) and common messages to be adopted for compliance with the LunaNet framework, and the justification of the selected approach.

LunaNet↗
NASA NTRS1979

Multiple speed expandable bit synchronizer

A multiple speed bit synchronizer was designed for installation in an inertial navigation system data decoder to extract non-return-to-zero level data and clock signal from biphase level data. The circuit automatically senses one of four pre-determined biphase data rates and synchronizes the proper clock rate to the data. Through a simple expansion of the basic design, synchronization of more than four binarily related data rates can be accomplished. The design provides an easily adaptable, low cost, low power alternative to external bit synchronizers with additional savings in size and weight.

Bundinger, J. M.↗
DOE OSTI2025

Center for Alternate Synchronization and Timing (CAST) PTP Network Monitoring Report

The Oak Ridge National Laboratory Center for Alternative Synchronization and Timing (CAST) performs research, development, testing, and evaluation of alternative terrestrial-based timing and synchronization infrastructure for the US power grid and other critical infrastructures. Alternative timing options reduce reliance on GPS and enhance the overall resilience of critical infrastructures. CAST infrastructure uses Precision Time Protocol (PTP) as the primary conduit for delivery of synchronization packets. CAST deploys PTP over long terrestrial links to synchronize a multitude of remote boundary clocks and downstream power grid components with the authoritative grand master clocks. Network traffic issues can severely degrade PTP accuracy. This report focuses on examining network traffic anomalies and their effects on PTP operation as well as the potential implications to CAST’s high-precision remote synchronization operations.

24 POWER TRANSMISSION AND DISTRIBUTION↗
NASA NTRS1995

Network time synchronization servers at the US Naval Observatory

Responding to an increased demand for reliable, accurate time on the Internet and Milnet, the U.S. Naval Observatory Time Service has established the network time servers, tick.usno.navy.mil and tock.usno.navy.mil. The system clocks of these HP9000/747i industrial work stations are synchronized to within a few tens of microseconds of USNO Master Clock 2 using VMEbus IRIG-B interfaces. Redundant time code is available from a VMEbus GPS receiver. UTC(USNO) is provided over the network via a number of protocols, including the Network Time Protocol (NTP) (DARPA Network Working Group Report RFC-1305), the Daytime Protocol (RFC-867), and the Time protocol (RFC-868). Access to USNO network time services is presently open and unrestricted. An overview of USNO time services and results of LAN and WAN time synchronization tests will be presented.

Schmidt, Richard E.↗
NASA NTRS2012

Radiation-Hard SpaceWire/Gigabit Ethernet-Compatible Transponder

A radiation-hard transponder was developed utilizing submicron/nanotechnology from IBM. The device consumes low power and has a low fabrication cost. This device utilizes a Plug-and-Play concept, and can be integrated into intra-satellite networks, supporting SpaceWire and Gigabit Ethernet I/O. A space-qualified, 100-pin package also was developed, allowing space-qualified (class K) transponders to be delivered within a six-month time frame. The novel, optical, radiation-tolerant transponder was implemented as a standalone board, containing the transponder ASIC (application specific integrated circuit) and optical module, with an FPGA (field-programmable gate array) friendly parallel interface. It features improved radiation tolerance; high-data-rate, low-power consumption; and advanced functionality. The transponder utilizes a patented current mode logic library of radiation-hardened-by-architecture cells. The transponder was developed, fabricated, and radhard tested up to 1 MRad. It was fabricated using 90-nm CMOS (complementary metal oxide semiconductor) 9 SF process from IBM, and incorporates full BIT circuitry, allowing a loop back test. The low-speed parallel LVCMOS (lowvoltage complementary metal oxide semiconductor) bus is compatible with Actel FPGA. The output LVDS (low-voltage differential signaling) interface operates up to 1.5 Gb/s. Built-in CDR (clock-data recovery) circuitry provides robust synchronization and incorporates two alarm signals such as synch loss and signal loss. The ultra-linear peak detector scheme allows on-line control of the amplitude of the input signal. Power consumption is less than 300 mW. The developed transponder with a 1.25 Gb/s serial data rate incorporates a 10-to-1 serializer with an internal clock multiplication unit and a 10-1 deserializer with internal clock and data recovery block, which can operate with 8B10B encoded signals. Three loop-back test modes are provided to facilitate the built-in-test functionality. The design is based on a proprietary library of differential current switching logic cells implemented in the standard 90-nm CMOS 9SF technology from IBM. The proprietary low-power LVDS physical interface is fully compatible with the SpaceWire standard, and can be directly connected to the SFP MSA (small form factor pluggable Multiple Source Agreement) optical transponder. The low-speed parallel interfaces are fully compatible with the standard 1.8 V CMOS input/output devices. The utilized proprietary annular CMOS layout structures provide TID tolerance above 1.2 MRad. The complete chip consumes less than 150 mW of power from a single 1.8-V positive supply source.

Katzman, Vladimir↗