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A custom designed SRAM was used to measure the thickness of integrated circuit over layers and the epi-layer thickness using alpha particles and a test SRAM. The over layer consists of oxide, nitride, metal, and junction regions.
The flight focal plane array (FPA) for the Thermal Infrared Sensor 2 (TIRS-2) instrument, to be flown on Landsat 9, was built and characterized at NASA Goddard Space Flight Center (GSFC). The FPA was assembled using GaAs quantum well infrared photodetector (QWIP) arrays from the same lot as the TIRS instrument on Landsat 8. Each QWIP array is hybridized to an Indigo ISC9803 readout integrated circuit (ROIC) with 640 x 512, 25µm by 25µm pixels. Each QWIP hybrid was tested at the NASA/GSFC Detector Characterization Laboratory (DCL) as a single sensor chip assembly (SCA). The best SCAs in terms of performance were then built up into an FPA consisting of three SCAs, required to provide the necessary 15-degree field of view of the instrument. The FPA was tested to determine if project requirements were being met as a fully assembled unit. The performance of the QWIP SCAs and the fully assembled, NASA flight-qualified FPA will be reviewed.
An adjustable planar imbedding circuit based on coplanar transmission lines is presented to deal with the impedance mismatch associated with the use of the Superconductor-Insulator-Superconductor tunnel junction. The planar embedding circuit is developed with movable noncontacting shorting elements that consist of thin metallic plates with optimized arrangements of rectangular holes. The rectangular holes are placed along the insulated metallic transmission line to provide a periodic variation of the line impedance. A large reflection coefficient is demonstrated with a scale model of the sliding backshort, and values of more than -0.5 dB are reported. The shorting elements are incorporated into a low-frequency tuning circuit to test the practical tuning ranges. The backshort can be used to fashion tuning stubs with variable post-fabrication electrical lengths which relaxes the design constraints of planar integrated circuits.
As integrated circuits become more sensitive to charged particles and neutrons, anomalous performance due to single event effects (SEE) is a concern and requires experimental verification and quantification. The Center for Applied Radiation Research (CARR) at Prairie View A&M University has developed experiments as a participant in the NASA ER-2 Flight Program, the APEX balloon flight program and the Student Launch Program. Other high altitude and ground level experiments of interest to DoD and commercial applications are being developed. The experiment characterizes the SEE behavior of high speed and high density SRAM's. The system includes a PC-104 computer unit, an optical drive for storage, a test board with the components under test, and a latchup detection and reset unit. The test program will continuously monitor the stored checkerboard data pattern in the SW and record errors. Since both the computer and the optical drive contain integrated circuits, they are also vulnerable to radiation effects. A latchup detection unit with discrete components will monitor the test program and reset the system when necessary. The first results will be obtained from the NASA ER-2 flights, which are now planned to take place in early 1998 from Dryden Research Center in California. The series of flights, at altitudes up to 70,000 feet, and a variety of flight profiles should yield a distribution of conditions for correlating SEES. SEE measurements will be performed from the time of aircraft power-up on the ground throughout the flight regime until systems power-off after landing.
As demand for high-speed, on-board, digital-processing integrated circuits on spacecraft increases (field-programmable gate arrays and digital signal processors in particular), the need for the next generation point-of-load (POL) regulator becomes a prominent design issue. Shrinking process nodes have resulted in core rails dropping to values close to 1.0 V, drastically reducing margin to standard switching converters or regulators that power digital ICs. The goal of this task is to perform SET characterization of several commercial POL converters, and provide a discussion of the impact of these results to state-of-the-art digital processing IC through laser and heavy ion testing
As demand for high-speed, on-board, digital-processing integrated circuits on spacecraft increases (field-programmable gate arrays and digital signal processors in particular), the need for the next generation point-of-load (POL) regulator becomes a prominent design issue. Shrinking process nodes have resulted in core rails dropping to values close to 1.0 V, drastically reducing margin to standard switching converters or regulators that power digital ICs. The goal of this task is to perform SET characterization of several commercial POL converters, and provide a discussion of the impact of these results to state-of-the-art digital processing IC through laser and heavy ion testing
This paper discusses single-event upset (SEU) in memories and microprocessors that are the "drivers" of highly scaled commercial integrated circuits. Despite the decrease in critical charge that occurs for highly scaled CMOS devices, recent test data has shown that SEU rates are actually somewhat lower for scaled devices compared to older devices with larger feature size. Hard errors, which are increasingly important for memories, are discussed along with conventional soft errors. Functional errors in memories and microprocessors are particularly significant, and tend to dominate the response of highly scaled devices from an application standpoint. Predictions for future devices are made using the Semiconductor Industry Roadmap along with recent modeling and radiation test results.
Researchers at NASA Glenn Research Center have been investigating shunted piezoelectric circuits as potential damping treatments for turbomachinery rotor blades. This effort seeks to determine the effects of centrifugal loading on passively-shunted piezoelectric - damped plates. Passive shunt circuit parameters are optimized for the plate's third bending mode. Tests are performed both non-spinning and in the Dynamic Spin Facility to verify the analysis, and to determine the effectiveness of the damping under centrifugal loading. Results show that a resistive shunt circuit will reduce resonant vibration for this configuration. However, a tuned shunt circuit will be required to achieve the desired damping level. The analysis and testing address several issues with passive shunt circuit implementation in a rotating system, including piezoelectric material integrity under centrifugal loading, shunt circuit implementation, and tip mode damping.
Orbital Research, Inc., developed, built, and tested three high-temperature components for use in the design of a data concentrator module in distributed turbine engine control. The concentrator receives analog and digital signals related to turbine engine control and communicates with a full authority digital engine control (FADEC) or high-level command processor. This data concentrator follows the Distributed Engine Controls Working Group (DECWG) roadmap for turbine engine distributed controls communication development that operates at temperatures at least up to 225 C. In Phase I, Orbital Research developed detailed specifications for each component needed for the system and defined the total system specifications. This entailed a combination of system design, compiling existing component specifications, laboratory testing, and simulation. The results showed the feasibility of the data concentrator. Phase II of this project focused on three key objectives. The first objective was to update the data concentrator design modifications from DECWG and prime contractors. Secondly, the project defined requirements for the three new high-temperature, application-specific integrated circuits (ASICs): one-time programmable (OTP), transient voltage suppression (TVS), and 3.3V. Finally, the project validated each design by testing over temperature and under load.
We present here the design, development and test of an integrated sub-millimeter front-end featuring a 520-600 GHz sub-harmonic mixer and a 260-300 GHz frequency tripler in a single cavity. Both devices used GaAs MMIC membrane planar Schottky diode technology. The sub-harmonic mixer/tripler circuit has been tested using conventional machined as well as silicon micro-machined blocks. Measurement results on the metal block give best DSB mixer noise temperature of 2360 K and conversion losses of 7.7 dB at 520 GHz. Preliminary results on the silicon micro-machined blocks give a DSB mixer noise temperature of 4860 K and conversion losses of 12.16 dB at 540 GHz. The LO input power required to pump the integrated tripler/sub-harmonic mixer for both packages is between 30 and 50 mW.
Switching and amplifying characteristics of a newly developed monolithic InGaAs Active Pixel Imager Array are presented. The sensor array is fabricated from InGaAs material epitaxially deposited on an InP substrate. It consists of an InGaAs photodiode connected to InP depletion-mode junction field effect transistors (JFETs) for low leakage, low power, and fast control of circuit signal amplifying, buffering, selection, and reset. This monolithically integrated active pixel sensor configuration eliminates the need for hybridization with silicon multiplexer. In addition, the configuration allows the sensor to be front illuminated, making it sensitive to visible as well as near infrared signal radiation. Adapting the existing 1.55 micrometer fiber optical communication technology, this integration will be an ideal system of optoelectronic integration for dual band (Visible/IR) applications near room temperature, for use in atmospheric gas sensing in space, and for target identification on earth. In this paper, two different types of small 4 x 1 test arrays will be described. The effectiveness of switching and amplifying circuits will be discussed in terms of circuit effectiveness (leakage, operating frequency, and temperature) in preparation for the second phase demonstration of integrated, two-dimensional monolithic InGaAs active pixel sensor arrays for applications in transportable shipboard surveillance, night vision, and emission spectroscopy.
The proposed technology allows use of the latest microcircuit technology with lowest power and fastest speed, with minimal delay and engineering costs, through new Radiation Hardened by Design (RHBD) techniques that do not require extensive process characterization, technique evaluation and re-design at each Moore's Law generation. The separation of critical node groups is explicitly parameterized so it can be increased as microcircuit technologies shrink. The technology will be open access to radiation tolerant circuit vendors. INNOVATION: This technology would enhance computation intensive applications such as autonomy, robotics, advanced sensor and tracking processes, as well as low power applications such as wireless sensor networks. OUTCOME / RESULTS: 1) Simulation analysis indicates feasibility. 2)Compact voting latch 65 nanometer test chip designed and submitted for fabrication -7/2016. INFUSION FOR SPACE / EARTH: This technology may be used in any digital integrated circuit in which a high level of resistance to Single Event Upsets is desired, and has the greatest benefit outside low earth orbit where cosmic rays are numerous.
The NASA Lewis Research Center in Cleveland, Ohio, has developed the electronics for a free-space, direct-detection laser communications system demonstration. Under the High-Speed Laser Integrated Terminal Electronics (Hi-LITE) Project, NASA Lewis has built a prototype full-duplex, dual-channel electronics transmitter and receiver operating at 325 megabit S per second (Mbps) per channel and using quaternary pulse-position modulation (QPPM). This paper describes the integration and testing of the transmitter portion for future application in free-space, direct-detection laser communications. A companion paper reviews the receiver portion of the prototype electronics. Minor modifications to the transmitter were made since the initial report on the entire system, and this paper addresses them. The digital electronics are implemented in gallium arsenide integrated circuits mounted on prototype boards. The fabrication and implementation issues related to these high-speed devices are discussed. The transmitter's test results are documented, and its functionality is verified by exercising all modes of operation. Various testing issues pertaining to high-speed circuits are addressed. A description of the transmitter electronics packaging concludes the paper.
The Vorago Technologies RH-OBC-1 is a CubeSat Kit Bus compatible single board computer with a Vorago VA10820 ARM Cortex-M0 microcontroller at its core. The board also includes a set of common peripheral integrated circuits, like voltage regulators, non-volatile memories (NVM), an analog-to-digital converter (ADC), a watchdog/supervisor, and a Controller Area Network (CAN) bus transceiver. High-energy proton (200 MeV) testing was conducted at both board and component levels to investigate single-event effects.
The world s first silicon-based complementary metal oxide/semiconductor (CMOS) integrated-circuit voltage-controlled oscillator (VCO) operating in a frequency range around 324 GHz has been built and tested. Concomitantly, equipment for measuring the performance of this oscillator has been built and tested. These accomplishments are intermediate steps in a continuing effort to develop low-power-consumption, low-phase-noise, electronically tunable signal generators as local oscillators for heterodyne receivers in submillimeter-wavelength (frequency > 300 GHz) scientific instruments and imaging systems. Submillimeter-wavelength imaging systems are of special interest for military and law-enforcement use because they could, potentially, be used to detect weapons hidden behind clothing and other opaque dielectric materials. In comparison with prior submillimeter- wavelength signal generators, CMOS VCOs offer significant potential advantages, including great reductions in power consumption, mass, size, and complexity. In addition, there is potential for on-chip integration of CMOS VCOs with other CMOS integrated circuitry, including phase-lock loops, analog- to-digital converters, and advanced microprocessors.
This summary provides the general engineering community with the accumulated experience from ALERT reports issued by NASA and the Government-Industry. Data Exchange Program, and related experience gained by Government and industry. It provides expanded information on selected topics by relating the problem area (failure) to the cause, the investigation and findings, the suggestions for avoidance (inspections, screening tests, proper part applications, requirements for manufacturer's plant facilities, etc.), and failure analysis procedures. Diodes, integrated circuits, and transistors are covered in this volume.
A plasma interaction analysis in support of the solar electric propulsion subsystem examined the effects of a large high voltage solar array interacting with an ion thruster produced plasma. Two solar array test modules consisting of 36 large area wraparound contact solar cells welded to a flexible Kapton integrated circuit substrate were abricated. The modules contained certain features of the effects of insulation, din-holes, and bonding of the cell to the substrate and a ground plane. The possibility of a significant power loss occurring due to the collection of charged particles on the solar array interconnects was the focus of the research.
Random-fault densities measured in array of standard structures. Test pattern is array of standard circuit elements built into circuit chip along with, or in lieu of, integrated circuit objective process. Measurements on ray made and interpreted so fabrication process can be corrected as necessary.