Search NASA⌕ Search

SEARCH · Search NASA

Results for “system on a chip”

Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

Quote a phrase for an exact phrase match. Source license links do not imply unrestricted reuse.

At least 271 records · Page 15

High-Performance Spaceflight Computing (HPSC) Middleware Overview

High Performance Spacecraft Computing (HPSC) is a joint project between the National Aeronautics and Space Administration (NASA) and Air Force Research Lab (AFRL) to develop a high-performance multi-core radiation hardened flight processor. HPSC offers a new flight computing architecture to meet the needs of NASA missions through 2030 and beyond. Providing on the order of 100X the computational capacity of current flight processors for the same amount of power, the multicore architecture of the HPSC processor, or "Chiplet" provides unprecedented flexibility in a flight computing system by enabling the operating point to be set dynamically, trading among needs for computational performance, energy management and fault tolerance. The HPSC Chiplet is being developed by Boeing under contract to NASA, and is expected to provide prototypes in 2021. The HPSC Chiplet prototypes will be delivered with an evaluation board, system emulators, comprehensive system software, and a software development kit. In addition to the vendor deliverables, the AFRL is funding the development of a flexible Middleware to be developed by NASA Jet Propulsion Laboratory and NASA Goddard Space Flight Center. The HPSC Middleware provides a suite of thirteen high level services to manage the compute, memory and I/O resources of this complex device.This presentation will provide an overview of the HPSC project, including a hardware overview, system software overview, Middleware overview, and mission use cases. The hardware overview will provide a look at the 8 core High Performance Processing Subsystem (HPPS), the Real Time Processing Subsystem (RTPS), the Chiplet Configuration Management Subsystem, on chip peripherals, and high speed I/O. The system software overview will introduce the boot loaders, operating systems, device drivers, and software development environment. The Middleware overview will provide insight into the high-level services that will be provided to help mission developers manage the many resources and configurations made possible with the Chiplet. Finally, the presentation will provide a brief look at the mission use cases that can be enabled with this next generation architecture.

middleware↗

Packaging concept for LSI beam lead integrated circuits

Development of packaging system for mounting beam lead integrated chip circuit on lead frame is discussed. Process for fabricating large scale integration circuits is described. Diagrams illustrating method of construction are included.

Kennedy, B. W.↗

Demonstration program for Omega receiver prototype microcomputer data processing

The JOLT (TM) commercial microcomputer, based on the MOS Technology 6502 processor chip, for use in Omega navigation system is evaluated. A computer program was prepared in hand-assembled code to demonstrate receiver operation. The processor provides binary processing with interrupts enabled, a carriage return is given to initialize the teleprinter, and a jump is performed to enter the program loop to wait for an interrupt. The program loop operates continuously testing the interrupt flag. The interrupt routine reads the receiver status word and determines whether the current time-slot is the A slot. If so, the interrupt flag, which is also the data index pointer, is reset to zero. The status word is stored in the status buffer. If the time-slot is not A, the interrupt flag/pointer is incremented by one to index the phase and status to the proper buffer words for later use by the print routine.

Lilley, R. W.↗

Fast Holographic Comparator

Comparator is integrated-optical system constructed on a LiNb03sub. waveguide chip. Only the laser, lens and detector are external to chip. Aluminized surface gratings serve as input coupler and beam splitter. Light beams striking edges are returned by ordinary total internal reflection. Three operating modes are possible: A "screening" mode, an "identification" mode and a novel "self-subtraction" mode.

Vahey, D. W.↗

Programmable synaptic chip for electronic neural networks

A binary synaptic matrix chip has been developed for electronic neural networks. The matrix chip contains a programmable 32X32 array of 'long channel' NMOSFET binary connection elements implemented in a 3-micron bulk CMOS process. Since the neurons are kept off-chip, the synaptic chip serves as a 'cascadable' building block for a multi-chip synaptic network as large as 512X512 in size. As an alternative to the programmable NMOSFET (long channel) connection elements, tailored thin film resistors are deposited, in series with FET switches, on some CMOS test chips, to obtain the weak synaptic connections. Although deposition and patterning of the resistors require additional processing steps, they promise substantial savings in silicon area. The performance of synaptic chip in a 32-neuron breadboard system in an associative memory test application is discussed.

Moopenn, A.↗

CIAO: Chandra Interactive Analysis of Observations

Presentations and demonstrations of parts of CIAO, include the new GUIs developed for "FirstLook" analysis, data filtering and browsing; SHERPA, the multi-dimensional, multi-missions modelling and fitting application; CHIPS, the Chandra Imaging and Plotting System; generic data manipulation tools and other applications.

Fruscione, Antonella↗

A Report of Bethune-Cookman College NASA JOVE Projects

This document is the final report for the Joint Venture (JOVE) in Space Sciences, and describes the tasks, performed with the support of the contract. These tasks include work in: (1) interfacing microprocessor systems to high performance parallel interface chips, SCSI drive and memory, needed for the implementation of a Space Optical Data Recorder; (2) designing a digital interface architecture for a microprocessor controlled sensors monitoring unit for a NASA Jitter Attenuation and Dynamics Experiment (JADE) project; (3) developing an enhanced back-propagation training algorithm; (4) studying the effect of simulated spaceflight on Aortic Contractility; (5) developing a course in astronomy; and (6) improving internet access by running cables, and installing hubs in various places on the campus; and (7) researching the characteristics of Nd:YALO laser resonator.

Agba, Lawrence C.↗

Preliminary Examination of Sahara 99555: Mineralogy and Experimental Studies of a New Angrite

A 2710 g meteorite, Sahara 99555 (Sah99), was recently recovered from the Sahara and reported to be the 5th angrite. It is the largest angrite ever found and may offer useful information to better understand the unusual petrogeneses of this rare achondrite group. It may also allow us to examine the chronological record of igneous activity in the very early solar system. We obtained a 2.6 g chip of Sah99 and here present a preliminary report of its petrology and mineralogy in conjunction with a crystallization experiment on an analogue composition.

Mikouchi, T.↗

Battling Brittle Bones

The accuDEXA(R) Bone Mineral Density Assessment System, manufactured by Schick Technologies, Inc., utilizes "camera on a chip" sensor technology invented and developed by NASA's Jet Propulsion Laboratory. Schick's accuDEXA system offers several advantages over traditional osteoporosis tests, which assess bone density loss in the hip and spine, and require specialized personnel to conduct. With accuDEXA, physicians can test the entire body's bone density at a peripheral site, such as the finger, without applying gels or having patients remove garments. Results are achieved in 30 seconds and printed out in less than a minute, compared to the estimated exam time of 15 minutes for hip and spine density analyses. Schick has also applied the CMOS APS technology to a new software product that performs dental radiography using up to 90 percent less radiation exposure than conventional X-rays. Called Computed Dental Radiography(R), the new digital imaging product utilizes an electronic sensor in place of X-ray film to generate sharp and clear images that appear on a computer screen within 3 seconds, and can be enlarged and enhanced to identify problems.

Source record↗

Molecular Basis of Mechano-Signal Transduction in Vascular Endothelial Cells

Simulated microgravity studies using a random positioning machine (RPM). One RPM machine has been built for us by Fokker Science in Netherland. Using the device, we have developed an in vitro system to examine the effect of simulated microgravity on osteoblastic bone cells. Using this system, we have carried out gene chip studies to determine the gene expression profiles of osteoblasts cultured under simulated microgravity conditions in comparison to static controls. From this study, we have identified numerous genes, some of which are expected ones inducing bone loss, but many of which are unexpected and unknown. These findings are being prepared for publications.

Jo, Hanjoong↗

Spiral Chip Implantable Radiator and Printed Loop External Receptor for RF Telemetry in Bio-Sensor Systems

The paper describes the operation of a patented wireless RF telemetry system, consisting of a bio-MEMS implantable sensor and an external hand held unit, operating over the frequency range of few hundreds of MHz. A MEMS capacitive pressure sensor integrated with a miniature inductor/antenna together constitute the implantable sensor. Signal processing circuits collocated with a printed loop antenna together form the hand held unit, capable of inductively powering and also receiving the telemetry signals from the sensor. The paper in addition, demonstrates a technique to enhance the quality factor and inductance of the inductor in the presence of a lower ground plane and also presents the radiation characteristics of the loop antenna.

Simons, Rainee N.↗

Using SPEEDES to simulate the blue gene interconnect network

JPL and the Center for Advanced Computer Architecture (CACR) is conducting application and simulation analyses of BG/L in order to establish a range of effectiveness for the Blue Gene/L MPP architecture in performing important classes of computations and to determine the design sensitivity of the global interconnect network in support of real world ASCI application execution.

SPEEDES BlueGene/L BG/L system-on-a-chip↗

Future Avionics for X2K

The JPL X2000 program is for the delivery of advanced avionics systems, cutting edge technologies, and avionics components to spacecraft/orbiter, micro/nano-spacecraft, and in-situ missions. The objective is to develop and deliver avionics systems that will serve a multitude of future missions over the next 12 to 15 years.

DSST X2000 Micro/Nano Spacecraft Avionics distribu↗

Robust Bioinformatics Recognition with VLSI Biochip Microsystem

A microsystem architecture for real-time, on-site, robust bioinformatic patterns recognition and analysis has been proposed. This system is compatible with on-chip DNA analysis means such as polymerase chain reaction (PCR)amplification. A corresponding novel artificial neural network (ANN) learning algorithm using new sigmoid-logarithmic transfer function based on error backpropagation (EBP) algorithm is invented. Our results show the trained new ANN can recognize low fluorescence patterns better than the conventional sigmoidal ANN does. A differential logarithmic imaging chip is designed for calculating logarithm of relative intensities of fluorescence signals. The single-rail logarithmic circuit and a prototype ANN chip are designed, fabricated and characterized.

bioinformatics↗