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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 289 records · Page 16

Highly parallel sparse Cholesky factorization

Several fine grained parallel algorithms were developed and compared to compute the Cholesky factorization of a sparse matrix. The experimental implementations are on the Connection Machine, a distributed memory SIMD machine whose programming model conceptually supplies one processor per data element. In contrast to special purpose algorithms in which the matrix structure conforms to the connection structure of the machine, the focus is on matrices with arbitrary sparsity structure. The most promising algorithm is one whose inner loop performs several dense factorizations simultaneously on a 2-D grid of processors. Virtually any massively parallel dense factorization algorithm can be used as the key subroutine. The sparse code attains execution rates comparable to those of the dense subroutine. Although at present architectural limitations prevent the dense factorization from realizing its potential efficiency, it is concluded that a regular data parallel architecture can be used efficiently to solve arbitrarily structured sparse problems. A performance model is also presented and it is used to analyze the algorithms.

Gilbert, John R.↗

Nuclear Science Symposium, 30th, and Symposium on Nuclear Power Systems, 15th, San Francisco, CA, October 19-21, 1983, Proceedings

The range of disciplines covered includes physics instrumentation, data acquisition, FASTBUS, radiation detectors, scintillators, photomultipliers and optical detectors, subnanosecond 2-D imaging, medical and health instrumentation, reactor instrumentation, and space instrumentation. Cerenkov detectors, the prevention and rate capability of breakdown processes in wire chambers, and an interactive parallel processor for data analysis are studied. Attention is also given to bismuth germanate's role in gamma-ray spectroscopy, and the construction of a broadband universal sampling head is described. Gamma-ray imaging with a rotating hexagonal uniform redundant array, and broadband X-ray astronomical spectrometry are considered.

Nakamura, M.↗

Multi-terabyte image storage and distribution for NASA's Hubble Space Telescope

The modular architecture, functionality, and key components of the Hubble Space Telescope Data Archive Distribution Service (DADS) are presented. DADS functions comprise archive management, catalog management, and user interface. The distributed modular architecture utilized is made up of four subsystems, including the archive, host, catalog, and the Science Operations ground System/DADS Interface Processor. All data generated by the HST are archived in DADS on 12-in. optical disks. DADS is a permanent archive with a data capacity of 30 terabytes that can be expanded to 68 terabytes. Supplementary information and stellar observations will be instantly accessible through DADS, which can collect and archive more than 3 gigabytes per day of image and support data over the lifetime of the HST. Electronic and physical media will be accessible through 140 network connections, with a catalogue to assist in data set selection.

Weller, H. W., Jr.↗

A VLSI Processor Design of Real-Time Data Compression for High-Resolution Imaging Radar

For the high-resolution imaging radar systems, real-time data compression of raw imaging data is required to accomplish the science requirements and satisfy the given communication and storage constraints. The Block Adaptive Quantizer (BAQ) algorithm and its associated VLSI processor design have been developed to provide a real-time data compressor for high-resolution imaging radar systems.

data compression VLSI processor design imaging rad↗

TOGA - A GNSS Reflections Instrument for Remote Sensing Using Beamforming

Remotely sensing the Earth's surface using GNSS signals as bi-static radar sources is one of the most challenging applications for radiometric instrument design. As part of NASA's Instrument Incubator Program, our group at JPL has built a prototype instrument, TOGA (Time-shifted, Orthometric, GNSS Array), to address a variety of GNSS science needs. Observing GNSS reflections is major focus of the design/development effort. The TOGA design features a steerable beam antenna array which can form a high-gain antenna pattern in multiple directions simultaneously. Multiple FPGAs provide flexible digital signal processing logic to process both GPS and Galileo reflections. A Linux OS based science processor serves as experiment scheduler and data post-processor. This paper outlines the TOGA design approach as well as preliminary results of reflection data collected from test flights over the Pacific ocean. This reflections data demonstrates observation of the GPS L1/L2C/L5 signals.

GPS↗

Animated computer graphics models of space and earth sciences data generated via the massively parallel processor

The capability was developed of rapidly producing visual representations of large, complex, multi-dimensional space and earth sciences data sets via the implementation of computer graphics modeling techniques on the Massively Parallel Processor (MPP) by employing techniques recently developed for typically non-scientific applications. Such capabilities can provide a new and valuable tool for the understanding of complex scientific data, and a new application of parallel computing via the MPP. A prototype system with such capabilities was developed and integrated into the National Space Science Data Center's (NSSDC) Pilot Climate Data System (PCDS) data-independent environment for computer graphics data display to provide easy access to users. While developing these capabilities, several problems had to be solved independently of the actual use of the MPP, all of which are outlined.

Treinish, Lloyd A.↗

Goldstone R/D High Speed Data Acquisition System

A digital data acquisition system that meets the requirements of several users (initially the planetary radar program) is planned for general use at Deep Space Station 14 (DSS 14). The system, now partially complete, is controlled by VAX 11/780 computer that is programmed in high level languages. A DEC Data Controller is included for moderate-speed data acquisition, low speed data display, and for a digital interface to special user-provided devices. The high-speed data acquisition is performed in devices that are being designed and built at JPL. Analog IF signals are converted to a digitized 50 MHz real signal. This signal is filtered and mixed digitally to baseband after which its phase code (a PN sequence in the case of planetary radar) is removed. It may then be accumulated (or averaged) and fed into the VAX through an FPS 5210 array processor. Further data processing before entering the VAX is thus possible (computation and accumulation of the power spectra, for example). The system is to be located in the research and development pedestal at DSS 14 for easy access by researchers in radio astronomy as well as telemetry processing and antenna arraying.

Deutsch, L. J.↗

Compiling global name-space parallel loops for distributed execution

Distributed memory machines do not provide hardware support for a global address space. Thus programmers are forced to partition the data across the memories of the architecture and use explicit message passing to communicate data between processors. The compiler support required to allow programmers to express their algorithms using a global name-space is examined. A general method is presented for analysis of a high level source program and its translation into a set of independently executing tasks communicating via messages. If the compiler has enough information, this translation can be carried out at compile time. Otherwise, run-time code is generated to implement the required data movement. The analysis required in both situations is described and the performance of the generated code on the Intel iPSC/2 is presented.

Koelbel, Charles↗

Compiling global name-space programs for distributed execution

Distributed memory machines do not provide hardware support for a global address space. Thus programmers are forced to partition the data across the memories of the architecture and use explicit message passing to communicate data between processors. The compiler support required to allow programmers to express their algorithms using a global name-space is examined. A general method is presented for analysis of a high level source program and along with its translation to a set of independently executing tasks communicating via messages. If the compiler has enough information, this translation can be carried out at compile-time. Otherwise run-time code is generated to implement the required data movement. The analysis required in both situations is described and the performance of the generated code on the Intel iPSC/2 is presented.

Koelbel, Charles↗

Apollo remote site computer programming

Much has been written about the hardware to be used for Apollo mission support on the Manned Space Flight Network (MSFN). This article concerns itself with the software necessary to integrate hardware subsystems into a unique tool for mission control.

Computer programming↗

A fast microprocessor communication network design for interprocessor communications for an integrated flight control system

A node design with connectivity four is presented whose communication processor handles data at four million bits/sec on each of the four channels into the node, and on each of the four channels out of the node, for a total node capacity of 32 million bits/sec. An integrated flight control system real-time application of this communication network design is discussed. It is shown that such high speed node communication hardware, arranged in the topological configuration of a minimum diameter graph with connectivity four and all links active, has good potential for real time control applications requiring reliability, availability, and survivability characteristics.

Kelly, G. L.↗

A research program in advanced information systems

Topics addressed cover: identification of large space structure dynamics; special-purpose architectures for computational fluid dynamics; fault-tolerant processor architectures; data flow techniques; software specification and verification tools; management of software development; software environment for concurrent computing; and parallel algorithms and architectures for the solution of partial differential equations.

Vandervelde, Wallace E.↗

Voyager image data compression and block encoding

Telemetry enhancement techniques used by Voyager-2 to reduce telemetry transmission rates by over 50 percent compared to those used at Saturn, with negligible loss in information return, are described. The use of the Reed-Solomon encoder is discussed, and the principles and implementation of an Image Data Compressor algorithm for noiseless coding techniques are addressed. Parallel operation of the redundant Flight Data Subsystem processors is discussed.

Urban, Michael G.↗