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At least 289 records · Page 16

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NASA NTRS2004

High-Temperature Probe Station Developed to Characterize Microwave Devices Through 500 C

A photograph and a block diagram of the high-temperature probe station are shown. The system consists of the ceramic heater mounted on a NASA shuttle tile insulator, a direct current power supply, a personal-computer-based data acquisition and temperature controller, microwave probes, a microscope, and a network analyzer. The ability to perform microwave tests at high temperatures is becoming necessary. There is now a need for sensors and communication circuits that can operate at 500 C and above for aircraft engine development and monitoring during flight. To address this need, researchers have fabricated devices using wide bandgap semiconductors such as SiC with targeted operating temperatures of 500 to 600 C. However, the microwave properties of these devices often change drastically with temperature, so any designs that are intended to be used in such an environment must be characterized at high temperatures. For some reliability, lifetime, and direct-current testing, the device under test can be packaged and characterized in an oven. However, for RF and microwave measurements, it is usually not possible to establish a calibrated reference plane at the device terminals within a package. In addition, the characteristics of the package would vary over a 500 C temperature range, and this would have to be accounted for when the data were analyzed. A high temperature probe station allows circuits and devices to be characterized through on wafer measurements across a broad temperature range with known reference plane. The conventional, commercially available thermal wafer-probe stations that are used to evaluate microwave devices across a controlled temperature range have a typical upper limit of 200 C. Standalone thermal heating chucks are available with an extended upper temperature range of 300 to 400 C. To effectively characterize devices at temperatures up to and surpassing 500 C, Glenn researchers developed a custom probe station. In the past, custom probe stations have been developed to test devices under other extreme environments, such as cryogenic temperatures as low as 37 K. Similarly, this custom probe station was specifically modified for high-temperature use. It allows devices to be measured quickly and flexibly, without the use of wire bonds and test fixtures. The probe station is shown making scattering parameter measurements from 1 to 50 GHz with a Hewlett-Packard 8510C Network Analyzer. There is a half-wafer of silicon directly on top of the heater to provide a uniform heated platform for our sample. A quarter wafer of silicon carbide forms the substrate for our test circuit of several transmission lines.

Downey, Alan N.↗

NASA NTRS2006

Large format imaging arrays for the Atacama Cosmology Telescope

We describe progress in the fabrication, characterization, and production of detector arrays for the Atacama Cosmology Telescope (ACT). The completed ACT instrument is specified to image simultaneously at 145, 225, and 265 GHz using three 32x32 filled arrays of superconducting transition edge sensors (TES) read out with time-division-multiplexed SQUID amplifiers. We present details of the pixel design and testing including the optimization of the electrical parameters for multiplexed readout. Using geometric noise suppression and careful tuning of operation temperature and device bias resistance, the excess noise in the TES devices is balanced with detector speed for interfacing with the ACT optics. The design also accounts for practical tolerances such as transition temperature gradients and scatter that occur in the production of multiple wafers to populate fully the kilopixel cameras. We have developed an implanted absorber layer compatible with our silicon-on-insulator process that allows for tunable optical resistance with requisite on-wafer uniformity and wafer-to-wafer reproducibility. Arrays of 32 elements have been tested in the laboratory environment including electrical, optical, and multiplexed performance. Given this pixel design, optical tests and modeling are used to predict the performance of the filled array under anticipated viewing conditions. Integration of the filled array of pixels with a tuned backshort and dielectric plate in front of the array maximize absorption and the focal plane and suppress reflections. A mechanical design for the build of the full structure is completed and we report on progress toward the construction of a prototype array for first light on the ACT.

Chervenak, J. A.↗

NASA NTRS2007

Materials Development for Auxiliary Components for Large Compact Mo/Au TES Arrays

We describe our current fabrication process for arrays of superconducting transition edge sensor microcalorimeters, which incorporates superconducting Mo/Au bilayers and micromachined silicon structures. We focus on materials and integration methods for array heatsinking with our bilayer and micromachining processes. The thin superconducting molybdenum bottom layer strongly influences the superconducting behavior and overall film characteristics of our molybdenum/gold transition-edge sensors (TES). Concurrent with our successful TES microcalorimeter array development, we have started to investigate the thin film properties of molybdenum monolayers within a given phase space of several important process parameters. The monolayers are sputtered or electron-beam deposited exclusively on LPCVD silicon nitride coated silicon wafers. In our current bilayer process, molybdenum is electron-beam deposited at high wafer temperatures in excess of 500 degrees C. Identifying process parameters that yield high quality bilayers at a significantly lower temperature will increase options for incorporating process-sensitive auxiliary array components (AAC) such as array heat sinking and electrical interconnects into our overall device process. We are currently developing two competing technical approaches for heat sinking large compact TES microcalorimeter arrays. Our efforts to improve array heat sinking and mitigate thermal cross-talk between pixels include copper backside deposition on completed device chips and copper-filled micro-trenches surface-machined into wafers. In addition, we fabricated prototypes of copper through-wafer microvias as a potential way to read out the arrays. We present an overview on the results of our molybdenum monolayer study and its implications concerning our device fabrication. We discuss the design, fabrication process, and recent test results of our AAC development.

Finkbeiner, F. m.↗

NASA NTRS2007

Multiple internal seal right micro-electro-mechanical system vacuum package

A Multiple Internal Seal Ring (MISR) Micro-Electro-Mechanical System (MEMS) vacuum package that hermetically seals MEMS devices using MISR. The method bonds a capping plate having metal seal rings to a base plate having metal seal rings by wafer bonding the capping plate wafer to the base plate wafer. Bulk electrodes may be used to provide conductive paths between the seal rings on the base plate and the capping plate. All seals are made using only metal-to-metal seal rings deposited on the polished surfaces of the base plate and capping plate wafers. However, multiple electrical feed-through metal traces are provided by fabricating via holes through the capping plate for electrical connection from the outside of the package through the via-holes to the inside of the package. Each metal seal ring serves the dual purposes of hermetic sealing and providing the electrical feed-through metal trace.

Hayworth, Ken J.↗

NASA NTRS2008

Multiple internal seal ring micro-electro-mechanical system vacuum packaging method

A Multiple Internal Seal Ring (MISR) Micro-Electro-Mechanical System (MEMS) vacuum packaging method that hermetically seals MEMS devices using MISR. The method bonds a capping plate having metal seal rings to a base plate having metal seal rings by wafer bonding the capping plate wafer to the base plate wafer. Bulk electrodes may be used to provide conductive paths between the seal rings on the base plate and the capping plate. All seals are made using only metal-to-metal seal rings deposited on the polished surfaces of the base plate and capping plate wafers. However, multiple electrical feed-through metal traces are provided by fabricating via holes through the capping plate for electrical connection from the outside of the package through the via-holes to the inside of the package. Each metal seal ring serves the dual purposes of hermetic sealing and providing the electrical feed-through metal trace.

Hayworth, Ken J.↗

NASA NTRS2009

Alternative Packaging for Back-Illuminated Imagers

An alternative scheme has been conceived for packaging of silicon-based back-illuminated, back-side-thinned complementary metal oxide/semiconductor (CMOS) and charge-coupled-device image-detector integrated circuits, including an associated fabrication process. This scheme and process are complementary to those described in "Making a Back-Illuminated Imager With Back-Side Connections" (NPO-42839), NASA Tech Briefs, Vol. 32, No. 7 (July 2008), page 38. To avoid misunderstanding, it should be noted that in the terminology of imaging integrated circuits, "front side" or "back side" does not necessarily refer to the side that, during operation, faces toward or away from a source of light or other object to be imaged. Instead, "front side" signifies that side of a semiconductor substrate upon which the pixel pattern and the associated semiconductor devices and metal conductor lines are initially formed during fabrication, and "back side" signifies the opposite side. If the imager is of the type called "back-illuminated," then the back side is the one that faces an object to be imaged. Initially, a back-illuminated, back-side-thinned image-detector is fabricated with its back side bonded to a silicon handle wafer. At a subsequent stage of fabrication, the front side is bonded to a glass wafer (for mechanical support) and the silicon handle wafer is etched away to expose the back side. The frontside integrated circuitry includes metal input/output contact pads, which are rendered inaccessible by the bonding of the front side to the glass wafer. Hence, one of the main problems is to make the input/output contact pads accessible from the back side, which is ultimately to be the side accessible to the external world. The present combination of an alternative packaging scheme and associated fabrication process constitute a solution of the problem.

Pain, Bedabrata↗

DOE OSTI2025

One-Step Transfer of Symmetric and Asymmetric Contacts for Large-Scale 2D Electronics and Optoelectronics

Two-dimensional (2D) semiconductors are highly promising candidates for thin-film transistor applications due to their scalability, transferability, atomic thickness, and relatively high carrier mobility. However, a substantial performance gap remains between individual devices based on single-crystalline 2D films and wafer-scale integrated circuits, primarily due to defects introduced during conventional fabrication processes. Here, we report a diamond-assisted electrode transfer technique for the van der Waals integration of wafer-scale prefabricated electrode arrays onto 2D materials, enabling scalable electronics and optoelectronics. Implemented on metal–organic chemical vapor deposition-grown monolayer molybdenum disulfide, this method forms ultraclean metal–semiconductor interfaces, yielding field-effect transistors with excellent ohmic contacts, a low contact resistance of 400 Ω·μm, and a Schottky barrier height of only 9 meV. Furthermore, we demonstrate a scalable transistor array on monolayer molybdenum disulfide with excellent device performance uniformity, achieving an average field-effect mobility of 30 cm 2 V –1 s –1 and an on/off current ratio exceeding 105. Additionally, high photocurrent and responsivity were demonstrated in the array devices, showing their potential for excellent image detection. We further demonstrate the versatility of this technique by fabricating a Schottky diode array through a single-step transfer of asymmetric electrodes─low work function aluminum and high work function gold─onto monolayer tungsten diselenide. This approach provides a clean, effective solution for contact engineering in 2D materials, offering a viable pathway toward wafer-scale, high-performance 2D electronics, optoelectronics, and integrated circuits.

2D electronics↗

DOE OSTI2025

Resistivity distribution and donor properties of antimony-doped n -type Czochralski silicon ingots

We investigate antimony (Sb)-doped Czochralski-grown silicon as an alternative n-type substrate for photovoltaic applications, and characterize their axial resistivity distribution, donor properties, and mechanical strength. We find that Sb-doped ingots can achieve a more uniform resistivity distribution along the axial direction compared to P-doped counterparts. Dopant concentration profiles in P-doped ingots can be accurately modelled using the standard Scheil's equation, accounting only for dopant segregation during solidification. In contrast, modelling Sb-doped ingots requires consideration of both dopant segregation and evaporation effects to fit the dopant distribution accurately. Using electron paramagnetic resonance spectroscopy at 9 K, we observe two hyperfine lines in P-doped samples, and six hyperfine lines for Sb 121 and eight for Sb 123 isotopes, with the number of hyperfine lines governed by the nuclear spins. We further identify two-atom Sb clustering in the Sb-doped wafers, confirmed through simulations of the additional weak electron paramagnetic resonance peaks. Finally, we find that 140 μm as-cut planar Sb-doped wafers exhibit slightly higher mechanical strength compared to P-doped wafers.

14 SOLAR ENERGY↗

DOE OSTI2026

Development of a Flow-through Cell for Ultrasonic Extraction (UE)─Single Particle (SP)─ICP-MS─an Approach for Nano/Microparticle Elemental and Isotopic Analysis

Nanotechnology is a salient part of the scientific landscape, and analytical approaches are rapidly evolving to enable small-scale characterization of nano- and microparticle compositions and impurities. Here, a flow-through sonicating cell was developed for direct particle extraction from a silicon wafer and integrated with an inductively coupled plasma–mass spectrometer (ICP-MS) for subsequent elemental and isotopic characterization of the released particles. Ultrasonic extraction (UE)─single particle (SP)─ICP-MS offers controlled particle mobilization from solid substrates and allows for increased sample throughput by eliminating the need for pre-extraction of particles and decreasing sample preparation steps. Coupling this device to an ICP-MS with a time-of-flight (TOF) mass analyzer, it is possible to distinguish unique isotopic compositions of the particles. Both tungsten and nickel isotopically tagged particles, which were deposited on Si wafers, are presented here with analysis via UE─SP─ICP-MS. This approach could support efforts in the fields of particle synthesis, nuclear safeguards and forensics, environmental monitoring, and semiconductor industries in which the detection of particles from substrates and wafers is critical.

Paul, Molly [ORNL] (ORCID:0009000009672055)↗

DOE OSTI2024

Voltage waveform tailoring for high aspect ratio plasma etching of SiO 2 using Ar/CF 4 /O 2 mixtures: Consequences of low fundamental frequency biases

The use of non-sinusoidal waveforms in low pressure capacitively coupled plasmas intended for microelectronics fabrication has the goal of customizing ion and electron energy and angular distributions to the wafer. One such non-sinusoidal waveform uses the sum of consecutive harmonics of a fundamental sinusoidal frequency, f 0 , having a variable phase offset between the fundamental and even harmonics. In this paper, we discuss results from a computational investigation of the relation between ion energy and DC self-bias when varying the fundamental frequency f 0 for capacitively coupled plasmas sustained in Ar/CF 4 /O 2 and how those trends translate to a high aspect ratio etching of trenches in SiO 2 . The fundamental frequency, f 0 , was varied from 1 to 10 MHz and the relative phase from 0° to 180°. Two distinct regimes were identified. Average ion energy onto the wafer is strongly correlated with the DC self-bias at high f 0 , with there being a maximum at φ = 0° and minimum at φ = 180°. In the low frequency regime, this correlation is weak. Average ion energy onto the wafer is instead dominated by dynamic transients in the applied voltage waveforms, with a maximum at φ = 180° and minimum at φ = 0°. The trends in ion energy translate to etch properties. In both, the high and low frequency regimes, higher ion energies translate to higher etch rates and generally preferable final features, though behaving differently with phase angle.

36 MATERIALS SCIENCE↗

NASA NTRS1972

Erase-mode recording characteristics of photochromic CaF2, SrTiO3, and CaTiO3 crystals.

Erase-mode optical recording characteristics of photochromic crystal wafers of CaF2:La,Na; CaF2:Ce,Na; SrTiO3:Ni,Mo,Al; and CaTiO3:Ni,Mo have been measured. An argon laser operating at 5145 A was used for both optical recording and optical readout. Sensitometric curves of optical-density change versus logarithm of exposure are shown for a number of erase-beam intensities between 0.2 mW/sq cm and 2 W/sq cm. In this range, time-intensity reciprocity holds for the CaF2 materials but fails for the titanates, particularly at low intensities. The dependences of sensitivity, gamma, and maximum transmission contrast ratio on wafer thickness and material are discussed. Wafers of SrTiO3, CaTiO3, and CaF2 exhibiting approximately equal maximum contrast ratios have relative sensitivities approximately in the ratio 5:2:1, respectively, at an erase intensity of 1 W/sq cm.

Duncan, R. C., Jr.↗

NASA NTRS1971

Development of a plan for automating integrated circuit processing

The operations analysis and equipment evaluations pertinent to the design of an automated production facility capable of manufacturing beam-lead CMOS integrated circuits are reported. The overall plan shows approximate cost of major equipment, production rate and performance capability, flexibility, and special maintenance requirements. Direct computer control is compared with supervisory-mode operations. The plan is limited to wafer processing operations from the starting wafer to the finished beam-lead die after separation etching. The work already accomplished in implementing various automation schemes, and the type of equipment which can be found for instant automation are described. The plan is general, so that small shops or large production units can perhaps benefit. Examples of major types of automated processing machines are shown to illustrate the general concepts of automated wafer processing.

Source record↗

NASA NTRS1976

Slicing of silicon into sheet material: Silicon sheet growth development for the large area silicon sheet task of the low cost silicon solar array project

Multiblade slurry sawing is used to slice 10 cm diameter silicon ingots into wafers 0.024 cm thick using 0.050 cm of silicon per slice (0.026 cm kerf loss). Total slicing time is less than twenty hours, and 143 slices are produced simultaneously. Productivity (slice area per hour per blade) is shown as a function or blade load and thickness, and abrasive size. Finer abrasive slurries cause a reduction in slice productivity, and thin blades cause a reduction of wafer accuracy. Sawing induced surface damage is found to extend 18 microns into the wafer.

Holden, S. C.↗

NASA NTRS1977

X-ray topography as a process control tool in semiconductor and microcircuit manufacture

A bent wafer camera, designed to identify crystal lattice defects in semiconductor materials, was investigated. The camera makes use of conventional X-ray topographs and an innovative slightly bent wafer which allows rays from the point source to strike all portions of the wafer simultaneously. In addition to being utilized in solving production process control problems, this camera design substantially reduces the cost per topograph.

Parker, D. L.↗

NASA NTRS1978

Array automated assembly, phase 2

An analysis was made of cost tradeoffs for shaping modified square wafers from cylindrical crystals. Tests were conducted of the effectiveness of texture etching for removal of surface damage on sawed wafers. A single step texturing etch appeared adequate for removal of surface damage on wafers cut with multiple blade reciprocating slurry saws.

Taylor, W. E.↗

NASA NTRS1978

Preliminary evaluation of Glass Resin materials for solar cell cover use

The glass resins were deposited by several techniques on 200 micron thick cells and on 50 microns thick wafers. The covered cells were exposed to ultraviolet light in vacuum to an intensity of 10 UV energy-equivalent solar constants at air mass zero for 728 hr. The exposure was followed by a single long thermal cycle from ambient temperature to -150 C. Visual inspection of the samples indicated that all samples had darkened to varying degrees. The loss in short-circuit current was found to range from 8 to 24%, depending on the resin formulation. In another test over 40 glass resin-coated silicon wafers withstood 15 thermal cycles from 100 to-196 C in one or more of the thicknesses tested. Several of the resin-coated wafers were tested at 65 C and 90% relative humidity for 170 hr. No change in physical appearance was detected.

Marsik, S. J.↗

NASA NTRS1979

The Establishment of a Production-ready Manufacturing Process Utilizing Thin Silicon Substrates for Solar Cells

During the months of February and March, work towards the goals of the contract were started as scheduled. The first shipment of thin substrates were received and wafer processing was initiated. The objective of the contract is to investigate, develop and characterize the methods for establishing a production-ready manufacturing process which utilizes thin silicon substrates for solar cells. The thin substrates to be manufactured are three inches diameter, p-type Czochralski wafers of approximately 1 Omega cm resistivity. The wafers are prepared by sawing directly to thickness of 8 mils and 5 mils. To ensure removal of residual saw damage, most substrates are chemically etched to final thicknesses of 7 mils and 4 mils. The thin substrates are used to fabricate solar cells by standard processing techniques.

Pryor, R. A.↗

NASA NTRS1978

The effects of copper and titanium on silicon solar cells

Copper-doped N/P silicon solar cells fabricated from the Czochralski grown single-crystal wafers were found to have good electrical characteristics, but the titanium-doped N/P silicon solar cells has considerably lower conversion efficiency. However, in the copper/titanium-doped solar cells, copper seems to mitigate the unfavorable effects of titanium. To explain this behavior, microstructural tests were performed on silicon wafers and solar cells doped with copper, titanium and copper/titanium. Dark forward and reverse I-V measurements were performed on the solar cells to correlate the microstructural defects with the p-n junction properties. It was found that copper precipitates were formed in the copper-doped and copper/titanium-doped wafers and cells. There was a significant voltage drop in the dark reverse I-V measurements of the titanium solar cells. Also, there were some electronically active defects in the depletion region of some titanium-doped cells. Reasons that lead to the above results are given in detail.

Salama, A. M.↗