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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 289 records · Page 16
All sourcesNASA NTRSDOE OSTI
NASA NTRS1992

Comparison of immersed liquid and air cooling of NASA's Airborne Information Management System

The Airborne Information Management System (AIMS) is currently under development at NASA Dryden Flight Research Facility. The AIMS is designed as a modular system utilizing surface mounted integrated circuits in a high-density configuration. To maintain the temperature of the integrated circuits within manufacturer's specifications, the modules are to be filled with Fluorinert FC-72. Unlike ground based liquid cooled computers, the extreme range of the ambient pressures experienced by the AIMS requires the FC-72 be contained in a closed system. This forces the latent heat absorbed during the boiling to be released during the condensation that must take within the closed module system. Natural convection and/or pumping carries the heat to the outer surface of the AIMS module where the heat transfers to the ambient air. This paper will present an evaluation of the relative effectiveness of immersed liquid cooling and air cooling of the Airborne Information Management System.

Hoadley, A. W.↗
NASA NTRS1993

Photodetector Array For Neural Network

Integrated circuit performs 1,024 threshold operations in parallel. Designed for use in postprocessing output of optical correlator in optoelectronic neural network. Overall function of device to put out digital signals indicative of location(s) of bright spot(s) on detector plane. Response time less than commercial charge-coupled-device (CCD) imaging detector operating at standard television frame rate.

Langenbacher, Harry↗
NASA NTRS2006

Multichannel X-Band Dielectric-Resonator Oscillator

A multichannel dielectric-resonator oscillator (DRO), built as a prototype of a local oscillator for an X-band transmitter or receiver, is capable of being electrically tuned among and within 26 adjacent frequency channels, each 1.16 MHz wide, in a band ranging from 7,040 to 7,070 GHz. The tunability of this oscillator is what sets it apart from other DROs, making it possible to use mass-produced oscillator units of identical design in diverse X-band applications in which there are requirements to use different fixed frequencies or to switch among frequency channels. The oscillator (see figure) includes a custom-designed voltage-controlled-oscillator (VCO) monolithic microwave integrated circuit (MMIC), a dielectric resonator disk (puck), and two varactor-coupling circuits, all laid out on a 25-mil (0.635-mm)-thick alumina substrate having a length and width of 17.8 mm. The resonator disk has a diameter of 8.89 mm and a thickness of 4.01 mm. The oscillator is mounted in an 8.9-mm-deep cavity in a metal housing. The VCO MMIC incorporates a negative- resistance oscillator amplifier along with a buffer amplifier. The resonator disk is coupled to a microstrip transmission line connected to the negative-resistance port of the VCO MMIC. The two varactor-coupling circuits include microstrip lines, laid out orthogonally to each other, for coupling with the resonator disk. Each varactor microstrip line is DC-coupled to an external port via a microwave choke. One varactor is used for coarse tuning to select a channel; the other varactor is used (1) for fine tuning across the 1.16-MHz width of each channel and (2) as a feedback port for a phase-lock loop. The resonator disk is positioned to obtain (1) the most desirable bandwidth, (2) relatively tight coupling with the microstrip connected to the coarse-tuning varactor, and (3) relatively loose coupling with the microstrip connected to the fine-tuning varactor. Measurements of performance showed that the oscillator can be switched among any of the 26 channels and can be phase-locked to a nominal frequency in any channel. The degree of nonlinearity of tuning was found not to exceed 2.5 percent. The tuning sensitivity was found to be 6.15 MHz/V at a bias offset of -2 V on the phase-lock-loop varactor. The phase noise of the oscillator in free-running operation was found to be -107 dBc/Hz (where dBc signifies decibels relative to the carrier signal) at 100 kHz away from the carrier frequency.

Mysoor, Narayan↗
NASA NTRS2013

A Cross-Track Cloud-Scanning Dual-Frequency Doppler (C2D2) Radar for the Proposed ACE Mission and Beyond

The National Resource Council’s Earth Science Decadal Survey” (NRCDS) has identified the Aerosol/Climate/Ecosystems (ACE) Mission as a priority mission for NASA Earth science. The NRC recommended the inclusion of "a cross-track scanning cloud radar with channels at 94 GHz and possibly 34 GHz for measurement of cloud droplet size, glaciation height, and cloud height". Several radar concepts have been proposed that meet some of the requirements of the proposed ACE mission but none have provided scanning capability at both 34 and 94 GHz due to the challenge of constructing scanning antennas at 94 GHz. In this paper, we will describe a radar design that leverages new developments in microwave monolithic integrated circuits (MMICs) and micro-machining to enable an electronically-scanned radar with both Ka-band (35 GHz) and W-band (94-GHz) channels. This system uses a dual-frequency linear active electronically-steered array (AESA) combined with a parabolic cylindrical reflector. This configuration provides a large aperture (3m x 5m) with electronic-steering but is much simpler than a two-dimension AESA of similar size. Still, the W-band frequency requires element spacing of approximately 2.5 mm, presenting significant challenges for signal routing and incorporation of MMICs. By combining (Gallium Nitride) GaN MMIC technology with micro-machined radiators and interconnects and silicon-germanium (SiGe) beamforming MMICs, we are able to meet all the performance and packaging requirements of the linear array feed and enable simultaneous scanning of Ka-band and W-band radars over swath of up to 100 km.

Aerosol/Climate/Ecosystems (ACE) Mission↗
NASA NTRS2016

Cryogenic Low Noise MMIC Amplifiers for U-Band (40-60 GHz)

In this work, we describe monolithic millimeter-wave integrated circuit (MMIC) Low Noise Amplifier (LNA) and mixer designs for U-Band, also known as the WR19 waveguide band (40-60 GHz). The LNAs were fabricated in NGC’s 35 nm InP HEMT MMIC process. The MMICs were packaged in WR19 waveguide housings and tested for noise, both at room temperature and cryogenically. We present the results, including a comparison to the state-of-the-art, and discuss applications for amplifiers in this frequency range. To date, these are the first cryogenic 35 nm InP MMIC results covering the 40-60 GHz range. We achieved a noise temperature less than 30 K over the 40-60 GHz range, when the amplifiers were cryogenically cooled. These results are comparable with other results in the literature, and we believe are the lowest reported for MMICs in the 50-60 GHz range.

MMIC↗
NASA NTRS2018

Engineering Trade-off Considerations Regarding Design-for-Security, Design-for-Verification, and Design-for-Test

The United States government has identified that application specific integrated circuit (ASIC) and field programmable gate array (FPGA) hardware are at risk from a variety of adversary attacks. This finding affects system security and trust. Consequently, processes are being developed for system mitigation and countermeasure application. The scope of this tutorial pertains to potential vulnerabilities and countermeasures within the ASIC/FPGA design cycle. The presentation demonstrates how design practices can affect the risk for the adversary to: change circuitry, steal intellectual property, and listen to data operations. An important portion of the design cycle is assuring the design is working as specified or as expected. This is accomplished by exhaustive testing of the target design. Alternatively, it has been shown that well established schemes for test coverage enhancement (design-for-verification (DFV) and design-for-test (DFT)) can create conduits for adversary accessibility. As a result, it is essential to perform a trade between robust test coverage versus reliable design implementation. The goal of this tutorial is to explain the evolution of design practices; review adversary accessibility points due to DFV and DFT circuitry insertion (back door circuitry); and to describe common engineering trade-off considerations for test versus adversary threats.

Design for reliability (DFR)↗
NASA NTRS1987

VLSI-Chip Tester

Compact test set integrated in computer-aided design system. Test set performs functional tests on very-large-scale integrated (VLSI) circuits. Makes tests from points within VLSI chip as well as at input and output pins. Used for quality control and design; in latter capacity, checks internal logic functions on chip and feed results directly to computer-aided design system for correction. Also simulates operation of chip design before chip is made. VLSI Tester contains three power supplies, control logic, and standard multibus circuit board in aluminum chassis. Chassis fits under platform of microprobe station. Multibus board links tester to interactive terminals and to host computer.

Deutsch, Leslie J.↗
NASA NTRS2010

Integral Battery Power Limiting Circuit for Intrinsically Safe Applications

A circuit topology has been designed to guarantee the output of intrinsically safe power for the operation of electrical devices in a hazardous environment. This design uses a MOSFET (metal oxide semiconductor field-effect transistor) as a switch to connect and disconnect power to a load. A test current is provided through a separate path to the load for monitoring by a comparator against a preset threshold level. The circuit is configured so that the test current will detect a fault in the load and open the switch before the main current can respond. The main current passes through the switch and then an inductor. When a fault occurs in the load, the current through the inductor cannot change immediately, but the voltage drops immediately to safe levels. The comparator detects this drop and opens the switch before the current in the inductor has a chance to respond. This circuit protects both the current and voltage from exceeding safe levels. Typically, this type of protection is accomplished by a fuse or a circuit breaker, but in order for a fuse or a circuit breaker to blow or trip, the current must exceed the safe levels momentarily, which may be just enough time to ignite anything in a hazardous environment. To prevent this from happening, a fuse is typically current-limited by the addition of the resistor to keep the current within safe levels while the fuse reacts. The use of a resistor is acceptable for non-battery applications where the wasted energy and voltage drop across the resistor can be tolerated. The use of the switch and inductor minimizes the wasted energy. For example, a circuit runs from a 3.6-V battery that must be current-limited to 200 mA. If the circuit normally draws 10 mA, then an 18-ohm resistor would drop 180 mV during normal operation, while a typical switch (0.02 ohm) and inductor (0.97 ohm) would only drop 9.9 mV. From a power standpoint, the current-limiting resistor protection circuit wastes about 18 times more power than the switch and the inductor configuration. In the fault condition, both the resistor and the inductor react immediately. The resistor reacts by allowing more current to flow and dropping the voltage. Initially, the inductor reacts by dropping the voltage, and then by not allowing the current to change. When the comparator detects the drop in voltage, it opens the switch, thus preventing any further current flow. The inductor alone is not sufficient protection, because after the voltage drop has settled, the inductor would then allow the current to change, in this example, the current would be 3.7 A. In the fault condition, the resistor is flowing 200 mA until the fuse blows (anywhere from 1 ms to 100 s), while the switch and inductor combination is flowing about 2 A test current while monitoring for the fault to be corrected. Finally, as an additional safety feature, the circuit can be configured to hold the switch opened until both the load and source are disconnected.

Burns, Bradley M.↗
NASA NTRS1979

An introduction to the BANNING design automation system for shuttle microelectronic hardware development

The BANNING MOS design system is presented. It complements rather than supplant the normal design activities associated with the design and fabrication of low-power digital electronic equipment. BANNING is user-oriented and requires no programming experience to use effectively. It provides the user a simulation capability to aid in his circuit design and it eliminates most of the manual operations involved in the layout and artwork generation of integrated circuits. An example of its operation is given and some additional background reading is provided.

Mcgrady, W. J.↗
NASA NTRS1994

JTEC Panel report on microelectromechanical systems in Japan

This report summarizes recent activities in the development of microelectromechanical systems (MEMS) in Japan. For the purposes of this study, 'MEMS' means batch-fabricated miniature devices that convert physical parameters to or from electrical signals and that depend on mechanical structures or parameters in important ways for their operation. The report covers advanced materials and process technology; sensors and sensing microstructures; microactuators and actuation mechanisms; sensor-circuit integration and system partitioning; advanced packaging, microassembly, and testing technologies; and MEMS design techniques, applications, and infrastructure. The panel found that Japanese industry is emphasizing approaches to MEMS that are similar to those taken by U.S. industry (i.e., approaches based on silicon integrated-circuit technology); these efforts are comparable in their level of development to those in the United States. However, the ten-year, $250 million, MITI-sponsored program in micromachines emphasizes the miniaturization of more traditional (nonlithographic) machining processes, an area in which there is no comparable U.S. effort. Packaging technology and applications for batch-fabricated MEMS devices is considered a major challenge in both countries. The panel concluded that these and other issues will require global leadership and international cooperation to realize the benefits of MEMS in a timely way.

Wise, Kensall D.↗
NASA NTRS2004

Digital circuits using universal logic gates

According to the invention, a digital circuit design embodied in at least one of a structural netlist, a behavioral netlist, a hardware description language netlist, a full-custom ASIC, a semi-custom ASIC, an IP core, an integrated circuit, a hybrid of chips, one or more masks, a FPGA, and a circuit card assembly is disclosed. The digital circuit design includes first and second sub-circuits. The first sub-circuits comprise a first percentage of the digital circuit design and the second sub-circuits comprise a second percentage of the digital circuit design. Each of the second sub-circuits is substantially comprised of one or more kernel circuits. The kernel circuits are comprised of selection circuits. The second percentage is at least 5%. In various embodiments, the second percentage could be at least 10%, 20%, 30%, 40%, 50%, 60%, 70%, 80%, 90%, or 95%.

Whitaker, Sterling R.↗
NASA NTRS2010

Special Component Designs for Differential-Amplifier MMICs

Special designs of two types of electronic components transistors and transmission lines have been conceived to optimize the performances of these components as parts of waveguide-embedded differential-amplifier monolithic microwave integrated circuits (MMICs) of the type described in the immediately preceding article. These designs address the following two issues, the combination of which is unique to these particular MMICs: Each MMIC includes a differential double-strip transmission line that typically has an impedance between 60 and 100 W. However, for purposes of matching of impedances, transmission lines having lower impedances are also needed. The transistors in each MMIC are, more specifically, one or more pair(s) of InP-based high-electron-mobility transistors (HEMTs). Heretofore, it has been common practice to fabricate each such pair as a single device configured in the side-to-side electrode sequence source/gate/drain/gate/source. This configuration enables low-inductance source grounding from the sides of the device. However, this configuration is not suitable for differential operation, in which it is necessary to drive the gates differentially and to feed the output from the drain electrodes differentially. The special transmission-line design provides for three conductors, instead of two, in places where lower impedance is needed. The third conductor is a metal strip placed underneath the differential double-strip transmission line. The third conductor increases the capacitance per unit length of the transmission line by such an amount as to reduce the impedance to between 5 and 15 W. In the special HEMT-pair design, the side-to-side electrode sequence is changed to drain/gate/source/gate/ drain. In addition, the size of the source is reduced significantly, relative to corresponding sizes in prior designs. This reduction is justified by the fact that, by virtue of the differential configuration, the device has an internal virtual ground, and therefore there is no need for a low-resistance contact between the source and the radio-frequency circuitry. The source contact is needed only for DC biasing. These designs were implemented in a single-stage-amplifier MMIC. In a test at a frequency of 305 GHz, the amplifier embedded in a waveguide exhibited a gain of 0 dB; after correcting for the loss in the waveguide, the amplifier was found to afford a gain of 0.9 dB. In a test at 220 GHz, the overall gain of the amplifier- and-waveguide assembly was found to be 3.5 dB.

Kangaslahti, Pekka↗
NASA NTRS2025

System for Long-Duration Electrical Testing of SiC IC Generation 12 Chips at 500 °C

The system described in this report is an improved testing rig designed to enhance measurement flexibility, provide a compact oven footprint, and reduce costs for parallel oven-testing silicon carbide (SiC) integrated circuit devices at 500 °C for long durations (greater than 100 h). The testing rig design was characterized in terms of the ovens’ internal and external temperatures, system noise, and the leakage properties of their substrate/inner boards, where the devices under test (DUTs) reside. The test rig employs a National Instruments (NI) Peripheral Component Interconnect eXtensions for Instrumentation (PXI) measurement system, room-temperature pin-switching/customizing boards, and high-temperature compact ovens.

Stephanie Booth↗
NASA NTRS1972

A very high speed hard decision sequential decoder.

Description of a 40-Mbps hard-decision sequential decoder for high-data-rate coding systems for earth-orbiting space missions with power-limited links. A prototype decoder has been designed and fabricated using the fastest commercially available digital integrated circuits, MECL III. Thus far, an internal computational rate of 70 million computations per second has been achieved. Computational efficiency of the decoding algorithm was greatly improved by incorporating two modifications to the Fano algorithm - 'double quick threshold loosening' and 'diagonal steps.' Preliminary results indicate that an output error rate of 0.00001 can be achieved with E sub b/N sub zero less than 5.4 dB at data rates up to 40 Mbps. At lower data rates, even less signal energy is required. This decoder is believed to be at least five times faster than any previous sequential decoder.

Gilhousen, K. S.↗
NASA NTRS1977

Annual Conference on Nuclear and Space Radiation Effects, 14th, College of William and Mary, Williamsburg, Va., July 12-15, 1977, Proceedings

Topics related to processing and hardness assurance are considered, taking into account the radiation hardening of CMOS technologies, technological advances in the manufacture of radiation-hardened CMOS integrated circuits, CMOS hardness assurance through process controls and optimized design procedures, the application of operational amplifiers to hardened systems, a hard off-the-shelf SG1524 pulse width modulator, and the gamma-induced voltage breakdown anomaly in a Schottky diode. Basic mechanisms are examined, giving attention to chemical and structural aspects of the irradiation behavior of SiO2 films on silicon, experimental observations of the chemistry of the SiO2/Si interface, leakage current phenomena in irradiated SOS devices, the avalanche injection of holes into SiO2, the low-temperature radiation response of Al2O3 gate insulators, and neutron damage mechanisms in silicon at 10 K. Other subjects discussed are related to radiation effects in devices and circuits, space radiation effects, and aspects of simulation, energy deposition, and dosimetry.

Stahl, R. H.↗
NASA NTRS1991

Programmable digital modem

The design of the Programmable Digital Modem (PDM) is outlined. The PDM will be capable of operating with numerous modulation techniques including: 2-, 4-, 8- and 16-ary phase shift keying (PSK), minimum shift keying (MSK), and 16-ary quadrature amplitude modulation (QAM), with spectral occupancy from 1.2x to 2x the data symbol rate. It will also be programmable for transmission rates ranging from 2.34 to 300 Mbit/s, where the maximum symbol rate is 75 Msymbol/s. Furthermore, these parameters will be executable in independent burst, dependent burst, or continuous mode. In dependent burst mode the carrier and clock oscillator sources are common from burst to burst. To achieve as broad a set of requirements as these, it is clear that the essential signal processing must be digital. In addition, to avoid hardware changes when the operational parameters are changed, a fixed interface to an analog intermediate frequency (IF) is necessary for transmission; and, common system level architectures are necessary for the modulator and demodulator. Lastly, to minimize size and power, as much of the design as possible will be implemented with application specific integrated circuit (ASIC) chips.

Poklemba, John J.↗
NASA NTRS1991

An experiment in remote manufacturing using the advanced communications technology satellite

The goal of the completed project was to develop an experiment in remote manufacturing that would use the capabilities of the ACTS satellite. A set of possible experiments that could be performed using the Advanced Communications Technology Satellite (ACTS), and which would perform remote manufacturing using a laser cutter and an integrated circuit testing machine are described in detail. The proposed design is shown to be a feasible solution to the offered problem and it takes into consideration the constraints that were placed on the experiment. In addition, we have developed two more experiments that are included in this report: backup of rural telecommunication networks, and remote use of Synthetic Aperture Radar (SAR) data analysis for on-site collection of glacier scattering data in the Antarctic.

Tsatsoulis, Costas↗
NASA NTRS2002

Fly-By-Light/Power-By-Wire Fault-Tolerant Fiber-Optic Backplane

The design and development of a fault-tolerant fiber-optic backplane to demonstrate feasibility of such architecture is presented. The simulation results of test cases on the backplane in the advent of induced faults are presented, and the fault recovery capability of the architecture is demonstrated. The architecture was designed, developed, and implemented using the Very High Speed Integrated Circuits (VHSIC) Hardware Description Language (VHDL). The architecture was synthesized and implemented in hardware using Field Programmable Gate Arrays (FPGA) on multiple prototype boards.

Malekpour, Mahyar R.↗