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At least 307 records · Page 17

Search properties of some sequential decoding algorithms.

Sequential decoding procedures are studied in the context of selecting a path through a tree. Several algorithms are considered, and their properties are compared. It is shown that the stack algorithm introduced by Zigangirov (1966) and by Jelinek (1969) is essentially equivalent to the Fano algorithm with regard to the set of nodes examined and the path selected, although the description, implementation, and action of the two algorithms are quite different. A modified Fano algorithm is introduced, in which the quantizing parameter is eliminated. It can be inferred from limited simulation results that, at least in some applications, the new algorithm is computationally inferior to the old. However, it is of some theoretical interest since the conventional Fano algorithm may be considered to be a quantized version of it.

Geist, J. M.↗

A 1-1/2-level on-chip-decoding bubble memory chip design

Design includes multi-channel replicator which can reduce chip-writing requirement, selective annihilating switch which can effectively annihilate bubbles with minimum delay, and modified transfer switch which can be used as selective steering-type decoder.

Chen, T. T.↗

Simulation and modeling of the deep space receiver interaction with channel decoding performance

Computer models were developed in an attempt to reproduce the sequential decoder computation curve of Deep Space Network (DSN) ground station receivers, by simulation of the binary data output of the Gaussian channel with the carrier phaselock loop and the subcarrier demodulator assembly. Simulations were run at bit rates equal to the powers of 2 from 8 to 2,048, and agreement with DSN data was generally good above 32 bits per second. Simulation results at data rates of 8, 16, and 32 bits per second did not closely match experimental data. This simulation provides a more accurate prediction of DSN computation lengths than either current mathematical models or simulations without both the subcarrier demodulator and carrier loop.

Jones, H. W., Jr.↗

Maximum likelihood convolutional decoding (MCD) performance due to system losses

A model for predicting the computational performance of a maximum likelihood convolutional decoder (MCD) operating in a noisy carrier reference environment is described. This model is used to develop a subroutine that will be utilized by the Telemetry Analysis Program to compute the MCD bit error rate. When this computational model is averaged over noisy reference phase errors using a high-rate interpolation scheme, the results are found to agree quite favorably with experimental measurements.

Webster, L.↗

Sequential decoding in the presence of a noisy carrier reference

A new model for predicting the computational performance of a sequential decoder operating in a noisy carrier reference environment is described. The major difference between this model and previous models is that the new model characterizes the number of computations per frame as the sum of the computations resulting from a number of independent searches. This number of independent searches can then be considered as an effective frame length. When this computational model is averaged over noisy reference phase errors using a medium-rate interpolation scheme, the results are found to agree quite favorably with experimental measurements.

Lesh, J. R.↗

Sequential decoding in the presence of a noisy carrier reference

A new model for predicting the computational performance of a sequential decoder operating in a noisy carrier reference environment is described. The major difference between this model and previous models is that the new model characterizes the number of computations per frame as the sum of the computations resulting from a number of independent searches. This number of independent searches can then be considered as an effective frame length. When this computational model is averaged over noisy reference phase errors using a medium-rate interpolation scheme, the results are found to agree quite favorably with experimental measurements.

Lesh, J. R.↗

Implementation of a maximum likelihood convolutional decoder in the DSN

The development status of the decoder and the factors which were considered in defining the specific functional requirements are described. The design is discussed to the block diagram level. A description of the detailed design is provided, along with a description of the test software developed and a brief summary of the performance evaluation testing completed so far.

Alberda, M. E.↗

An iterative algorithm for decoding block codes transmitted over a memoryless channel

An algorithm was developed which optimally decodes a block code for minimum probability of symbol error in an iterative manner. The initial estimate is made by looking at each bit independently and is improved by considering bits related to it through the parity check equations. The dependent bits are considered in order of interesting probability of error. Since the computation proceeds in a systematic way with the bits having the greatest effect being used first, the algorithm approaches the optimum estimate after only a fraction of the parity check equations were used.

Greenberger, H. J.↗

Soft decision decoding of block codes

The performance of certain block codes on a Gaussian channel is evaluated. The BCH codes are markedly superior to convolutional codes currently used for deep space missions. The algorithm is used to derive results, which provides a basis for a simple, almost optimum procedure for decoding these codes.

Baumert, L. D.↗

A maximum likelihood convolutional decoder model vs experimental data comparison

This article describes the comparison of a maximum likelihood convolutional decoder (MCD) prediction model and the actual performance of the MCD at the Madrid Deep Space Station. The MCD prediction model is used to develop a subroutine that has been utilized by the Telemetry Analysis Program (TAP) to compute the MCD bit error rate for a given signal-to-noise ratio. The results indicate that that the TAP can predict quite well compared to the experimental measurements. An optimal modulation index also can be found through TAP.

Chen, R. Y.↗

Quasi-optimal decoding of linear block codes using soft decision detection

A simple but effective decoding procedure, applicable to any (n,k) linear block code with symbols from GF(q), is described. The technique involves a transformation of the parity check equations which focuses the code's correction power on the soft symbol set while still retaining the capability to correct one symbol error from outside this set. The soft symbol set is defined to be the n-k least reliably detected code symbol positions whose parity check row-spaces are linearly independent. The process generates a number of error vector screening candidates, each a solution to the parity check equations, and the maximum-likelihood candidate is accepted.

Greene, E. P.↗

Soft decision decoding of block codes

Using a general decoding technique of Solomon we evaluate the performance of certain block codes on a Gaussian channel. Quadratic residue codes of lengths 48 and 80 as well as BCH codes of length 128 and rates 1/2 and 1/3 are considered. All four of these codes perform quite favorably with respect to the constraint-length 7 rate 1/2 convolutional code presently used on NASA's Mariner-class spacecraft.

Baumert, L. D.↗

On decoding of Reed-Solomon codes over GF/32/ and GF/64/ using the transform techniques of Winograd

An algorithm based on the Winograd (1976) method is developed to compute a Fourier-like transform over Galois field GF(2 exp n) for n equal to 5 and 6. It is shown that this transform algorithm requires fewer multiplications than the more conventional fast transform algorithm described by Gentleman (1968). Such a transform can be used to encode and decode Reed-Solomon codes of length (2 exp n) -1.

Reed, I. S.↗

Independent synchronizer for digital decoders

Logic circuit synchronizes branches of any convolution code-decoder at low signal to noise ratios. Parity checks determine correct node synchronization. Device maintains synchrony as low as -3 dB. Circuit consists of 15 stage shift register, three up down counters, and some logic gates.

Stiffler, J. J.↗

11-Line to 512-line decoder

CMOS decoder is assembled from standard 4-line to 16-line decoder/demultiplexer IC's. Matrix may also be used to generate 256 latched-on or latched-off logic signals instead of 512 discrete unlatched signals. By using conventional CMOS IC's, circuit consumes only about 30 milliwatts.

Miller, W. N.↗

Telemetry degradation due to a CW RFI induced carrier tracking error for the block IV receiving system with maximum likelihood convolution decoding

Models to characterize the behavior of the Deep Space Network (DSN) Receiving System in the presence of a radio frequency interference (RFI) are considered. A simple method to evaluate the telemetry degradation due to the presence of a CW RFI near the carrier frequency for the DSN Block 4 Receiving System using the maximum likelihood convolutional decoding assembly is presented. Analytical and experimental results are given.

Sue, M. K.↗