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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 325 records · Page 18
All sourcesNASA NTRSDOE OSTI
DOE OSTI2020

Processor and method of weighted feature importance estimation

A method includes determining a feature importance ranking for each pair of clusters of a plurality of clusters to generate a first plurality of feature importance rankings. The method further includes determining a feature importance ranking between a particular data element and each cluster to generate a second plurality of feature importance rankings. A distance value associated with each pair of clusters of the plurality of clusters is determined to generate a plurality of distance values, and a probability value associated with each data element is determined to generate a plurality of probability values. The method further includes weighting the first plurality of feature importance rankings based on the plurality of distance values to determine a first plurality of weighted feature importance rankings and weighting the second plurality of feature importance rankings based on the plurality of probability values to determine a second plurality of weighted feature importance rankings.

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2021

Computational processor-in-memory with enhanced strided memory access

A computational memory for a computer. The memory includes a memory bank having a selected-row buffer and being configured to store records up to a number, K. The memory also includes an accumulator connected to the memory bank, the accumulator configured to store up to K records. The memory also includes an arithmetic and logic unit (ALU) connected to the accumulator and to the selected row buffer of the memory bank, the ALU having an indirect network of 2K ports for reading and writing records in the memory bank and the accumulator, and the ALU further physically configured to operate as a sorting network. The memory also includes a controller connected to the memory bank, the ALU, and the accumulator, the controller being hardware configured to direct operation of the ALU.

DeBenedictis, Erik↗
DOE OSTI2021

Arrangements for communicating data in a computing system using multiple processors

Systems and methods for reducing data movement in a computer system. The systems and methods use information or knowledge about the structure of an algorithm, operations to be executed at a receiving processing unit, variables or subsets or groups of variables in a distributed algorithm, or other forms of contextual information, for reducing the number of bits transmitted from at least one transmitting processing unit to at least one receiving processing unit or storage device.

Gonzalez, Juan Guillermo↗
DOE OSTI2021

Runtime localized cooling of high-performance processors

A plurality of thermal electric cooler (TEC) elements are formed in a TEC grid structure. Control logic dynamically varies a supply current supplied to each TEC element (or group of TEC elements) in the TEC grid based on changes in power density respectively associated with areas cooled by each of the TEC elements or group of TEC elements.

Rao, Karthik↗