Self-repair - Fault detection and automatic reconfiguration
Automation techniques for self-repairing digital computers in spaceborne multiprocessor systems
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Automation techniques for self-repairing digital computers in spaceborne multiprocessor systems
Design and development of input/output processor and voter-comparator switch concept of guidance and control computer for space stations - Vol. 4
System analysis and computer requirements derivation of guidance and control computer for space station applications - Vol. 5
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The history of failure detection and redundancy management in aircraft applications is reviewed. To date, techniques related to that subject have been based mainly on hardware duplication of like components with failure monitoring and switchover or averaging for redundancy management. Specific examples of these techniques are discussed as they have been applied to the NASA F-8 Digital Fly-by-Wire aircraft and are to be applied to the space shuttle vehicle in the near future.
Emulation techniques are proposed as a solution to a difficulty arising in the analysis of the reliability of highly reliable computer systems for future commercial aircraft. The difficulty, viz., the lack of credible precision in reliability estimates obtained by analytical modeling techniques are established. The difficulty is shown to be an unavoidable consequence of: (1) a high reliability requirement so demanding as to make system evaluation by use testing infeasible, (2) a complex system design technique, fault tolerance, (3) system reliability dominated by errors due to flaws in the system definition, and (4) elaborate analytical modeling techniques whose precision outputs are quite sensitive to errors of approximation in their input data. The technique of emulation is described, indicating how its input is a simple description of the logical structure of a system and its output is the consequent behavior. The use of emulation techniques is discussed for pseudo-testing systems to evaluate bounds on the parameter values needed for the analytical techniques.
The core electronics subsystems on unmanned spacecraft, which have been sent over the last 20 years to investigate the moon, Mars, Venus, and Mercury, have progressed through an evolution from simple fixed controllers and analog computers in the 1960's to general-purpose digital computers in current designs. This evolution is now moving in the direction of distributed computer networks. Current Voyager spacecraft already use three on-board computers. One is used to store commands and provide overall spacecraft management. Another is used for instrument control and telemetry collection, and the third computer is used for attitude control and scientific instrument pointing. An examination of the control logic in the instruments shows that, for many, it is cost-effective to replace the sequencing logic with a microcomputer. The Unified Data System architecture considered consists of a set of standard microcomputers connected by several redundant buses. A typical self-checking computer module will contain 23 RAMs, two microprocessors, one memory interface, three bus interfaces, and one core building block.
Emulation techniques applied to the analysis of the reliability of highly reliable computer systems for future commercial aircraft are described. The lack of credible precision in reliability estimates obtained by analytical modeling techniques is first established. The difficulty is shown to be an unavoidable consequence of: (1) a high reliability requirement so demanding as to make system evaluation by use testing infeasible; (2) a complex system design technique, fault tolerance; (3) system reliability dominated by errors due to flaws in the system definition; and (4) elaborate analytical modeling techniques whose precision outputs are quite sensitive to errors of approximation in their input data. Next, the technique of emulation is described, indicating how its input is a simple description of the logical structure of a system and its output is the consequent behavior. Use of emulation techniques is discussed for pseudo-testing systems to evaluate bounds on the parameter values needed for the analytical techniques. Finally an illustrative example is presented to demonstrate from actual use the promise of the proposed application of emulation.
The ground communications facility (GCF) central communications terminal and network operations control center (NOCC) hardware was rearranged, supplemented, and modified, and software programs changed to provide an improved GCF and NOCC operational environment and capability. Control center operations section activities required to make the changeover from the old to the new GCF and NOCC configuration are addressed.
A redundancy management system is described wherein input signals from a sensor are provided redundantly in parallel so that a primary control signal may be selected. Median value signals for groups of three sensors are detected in median value selectors of selection filter. The detected median value signals are then also compared in a subtractor/comparator to determine whether any of them exceed the others by an amount greater than the signal level for a failed sensor. If so, the exceeding detected medium value signal is sent to a control computer as the primary control signal. If not, the lowest level detected medium value signal is sent as the primary control signal.
The integrated application of reliability, failure effects and system simulator methods in establishing the airworthiness of a flight critical digital flight control system (DFCS) is demonstrated. The emphasis was on the mutual reinforcement of the methods in demonstrating the system safety.
Flight control system (FCS) reliability is discussed in terms of sensors, computers and actuators. The servo/actuation bottleneck is discussed. FCS survivability is considered. Preliminary survivability issues. A Grumman study vehicle, R-14, and YF-16 aircraft configurations are studied. Goals of control are reviewed.
An initial design for the Bit Processor (BP) referred to in prior reports as the Processing Element or PE has been completed. Eight BP's, together with their supporting random-access memory, a 64 k x 9 ROM to perform addition, routing logic, and some additional logic, constitute the components of a single stage. An initial stage design is given. Stages may be combined to perform high-speed fixed or floating point arithmetic. Stages can be configured into a range of arithmetic modules that includes bit-serial one or two-dimensional arrays; one or two dimensional arrays fixed or floating point processors; and specialized uniprocessors, such as long-word arithmetic units. One to eight BP's represent a likely initial chip level. The Stage would then correspond to a first-level pluggable module. As both this project and VLSI CAD/CAM progress, however, it is expected that the chip level would migrate upward to the stage and, perhaps, ultimately the box level. The BP RAM, consisting of two banks, holds only operands and indices. Programs are at the box (high-level function) and system level. At the system level initial effort has been concentrated on specifying the tools needed to evaluate design alternatives.
Computer aided design and computer aided manufacturing have the potential for greatly reducing the cost and lead time in the development of VLSI components. This potential paves the way for the design and fabrication of a wide variety of economically feasible high level functional units. It was observed that current computer systems have only a limited capacity to absorb new VLSI component types other than memory, microprocessors, and a relatively small number of other parts. The first purpose is to explore a system design which is capable of effectively incorporating a considerable number of VLSI part types and will both increase the speed of computation and reduce the attendant programming effort. A second purpose is to explore design techniques for VLSI parts which when incorporated by such a system will result in speeds and costs which are optimal. The proposed work may lay the groundwork for future efforts in the extensive simulation and measurements of the system's cost effectiveness and lead to prototype development.
The initial control and programming philosophies of the RELAPSE are discussed. A block diagram showing the relationship of the Arithmetic Units (composed of Stages and Bit Processors), to the Functional Units, and other components of the RELAPSE is used to guide this discussion. The latest version of the Bit Processor design is presented. Included is a detailed discussion of the Bit Processor's new scratch pad memory component. The section also clarifies the usage of the Bit Processor's processing registers, and Input/Output functions. The final design phase of the Arithmetic Unit is underway by a study of the Proposed IEEE Floating Point Standard. The decisions on conformation to this standard will be used as inputs into the finalization of the designs of the Bit Processor, Stage, and Arithmetic Units of the RELAPSE.
Artificial intelligence techniques were used along with statistical hpyothesis testing and modern control theory, to help the pilot cope with the issues of information, knowledge, and capability in the event of a failure. An intelligent flight control system is being developed which utilizes knowledge of cause and effect relationships between all aircraft components. It will screen the information available to the pilots, supplement his knowledge, and most importantly, utilize the remaining flight capability of the aircraft following a failure. The list of failure types the control system will accommodate includes sensor failures, actuator failures, and structural failures.
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The longitudinal and radial distribution of 103 substorm dipolarization events in the equatorial nightside magnetosphere from low altitude to about 9 R(E) observed by AMPTE/CCE is examined. The center of the distribution was located near midnight. For Kp of 3- or less, the distribution peak shifted toward the premidnight region, whereas for Kp of 4+ and higher, the distribution peak was inside the postmidnight region. The substorm frequency for the high-Kp case was about four times larger than the low-to-moderate-Kp case. The occurrence frequency of events increased with increasing radial distance, and no events were observed inside of 6.4 R(E). This radial distribution suggests that, on average, the substorm initiation region is greater than about 8 R(E). In addition, the average radial position of the signatures decreased with increasing Kp.