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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 325 records · Page 18
All sourcesNASA NTRSDOE OSTI
NASA NTRS1976

Mini-O, simple Omega receiver hardware for user education

A problem with the Omega system is a lack of suitable low cost hardware for the small user community. A collection of do it yourself circuit modules are under development intended for use by educational institutions, small boat owners, aviation enthusiasts, and others who have some skills in fabricating their own electronic equipment. Applications of the hardware to time frequency standards measurements, signal propagation monitoring, and navigation experiments are presented. A family of Mini-O systems have been constructed varying from the simplest RF preamplifiers and narrowband filters front-ends, to sophisticated microcomputer interface adapters.

Burhans, R. W.↗
NASA NTRS1978

Visual simulation requirements and hardware

Requirements for any out-of-the-cockpit visual simulation system can easily lead to a set of system specifications which are clearly beyond the visual scene that can be produced by current technology. Therefore, the requirements of any proposed system must be assessed in light of the expected simulated aircraft and missions, experiments on pilot response, and available image generation and display hardware. A review is made of some of the recent experiments, and the results are related to aircraft and missions with particular emphasis on research and development simulators. Recent visual simulation hardware is considered in light of extending the range of applications of piloted aircraft simulators, and a method of design approach is proposed.

Dusterberry, J. C.↗
NASA NTRS1979

Computer hardware description languages - A tutorial

The paper introduces hardware description languages (HDL) as useful tools for hardware design and documentation. The capabilities and limitations of HDLs are discussed along with the guidelines needed in selecting an appropriate HDL. The directions for future work are provided and attention is given to the implementation of HDLs in microcomputers.

Shiva, S. G.↗
NASA NTRS1980

Hardware synthesis from DDL description

The details of digital systems can be conveniently input into the design automation system by means of hardware description language (HDL). The computer aided design and test (CADAT) system at NASA MSFC is used for the LSI design. The digital design language (DDL) was selected as HDL for the CADAT System. DDL translator output can be used for the hardware implementation of the digital design. Problems of selecting the standard cells from the CADAT standard cell library to realize the logic implied by the DDL description of the system are addressed.

Shiva, S. G.↗
NASA NTRS1980

Outline of a fast hardware implementation of Winograd's DFT algorithm

The main characteristics of the discrete Fourier transform (DFT) algorithm considered by Winograd (1976) is a significant reduction in the number of multiplications. Its primary disadvantage is a higher structural complexity. It is, therefore, difficult to translate the reduced number of multiplications into faster execution of the DFT by means of a software implementation of the algorithm. For this reason, a hardware implementation is considered in the current study, taking into account a design based on the algorithm prescription discussed by Zohar (1979). The hardware implementation of a FORTRAN subroutine is proposed, giving attention to a pipelining scheme in which 5 consecutive data batches are being operated on simultaneously, each batch undergoing one of 5 processing phases.

Zohar, S.↗
NASA NTRS1981

Hardware synthesis from DDL

The details of the digital systems can be conveniently input into the design automation system by means of Hardware Description Languages (HDL). The Computer Aided Design and Test (CADAT) system at NASA MSFC is used for the LSI design. The Digital Design Language (DDL) has been selected as HDL for the CADAT System. DDL translator output can be used for the hardware implementation of the digital design. This paper addresses problems of selecting the standard cells from the CADAT standard cell library to realize the logic implied by the DDL description of the system.

Shah, A. M.↗
NASA NTRS1981

Modular hardware synthesis using an HDL

Although hardware description languages (HDL) are becoming more and more necessary to automated design systems, their application is complicated due to the difficulty in translating the HDL description into an implementable format, nonfamiliarity of hardware designers with high-level language programming, nonuniform design methodologies and the time and costs involved in transfering HDL design software. Digital design language (DDL) suffers from all of the above problems and in addition can only by synthesized on a complete system and not on its subparts, making it unsuitable for synthesis using standard modules or prefabricated chips such as those required in LSI or VLSI circuits. The present paper presents a method by which the DDL translator can be made to generate modular equations that will allow the system to be synthesized as an interconnection of lower-level modules. The method involves the introduction of a new language construct called a Module which provides for the separate translation of all equations bounded by it.

Covington, J. A.↗
NASA NTRS1981

Hardware survey for the avionics test bed

A survey of maor hardware items that could possibly be used in the development of an avionics test bed for space shuttle attached or autonomous large space structures was conducted in NASA Johnson Space Center building 16. The results of the survey are organized to show the hardware by laboratory usage. Computer systems in each laboratory are described in some detail.

Cobb, J. M.↗
NASA NTRS1980

The assembly of large structures in space - An evaluation of hardware configurations and assembly techniques through neutral buoyancy simulation

The implementation of NASA's Space Transportation System (STS) presents the opportunity for the on-orbit assembly of structures which, before the advent of multi-launch missions, were not possible because of their physical size. This report presents the results of an eight-month effort in the investigation of assembly techniques and hardware configurations used in assembly of the basic tetrahedral cell by A7LB pressure-suited subjects in Marshall Space Flight Center's Neutral Buoyancy Simulator. Eleven subjects participated in assembly procedures which investigated two types of structural members and two configurations of attachment hardware. The assembly was accomplished through extra-vehicular activity (EVA) only, EVA with simulated manned maneuvering unit (MMU), and EVA with simulated MMU and simulated remote manipulator system (RMS). Assembly times as low as 10.20 minutes per tetrahedron were achieved.

Loughead, T. E.↗
NASA NTRS1984

Hardware Fault Simulator Generates Test Vectors For Complex IC's

Report describes technique using fault simulator implemented entirely in hardware to generate and optimize test vectors for microprocessor. Hardware fault simulator approach reduces test time, while maintaining high reliability in detecting faults.

Timoc, C. C.↗
NASA NTRS1981

Energy efficient engine low-pressure compressor component test hardware detailed design report

The aerodynamic and mechanical design description of the low pressure compressor component of the Energy Efficient Engine were used. The component was designed to meet the requirements of the Flight Propulsion System while maintaining a low cost approach in providing a low pressure compressor design for the Integrated Core/Low Spool test required in the Energy Efficient Engine Program. The resulting low pressure compressor component design meets or exceeds all design goals with the exception of surge margin. In addition, the expense of hardware fabrication for the Integrated Core/Low Spool test has been minimized through the use of existing minor part hardware.

Michael, C. J.↗
NASA NTRS1983

Decoding: Codes and hardware implementation

The MST radars vary considerably from one installation to the next in the type of hardware, operating schedule and associated personnel. Most such systems do not have the computing power to decode in software when the decoding must be performed for each received pulse, as is required for certain sets of phase codes. These sets provide the best signal to sidelobe ratio when operating at the minimum band length allowed by the bandwidth of the transmitter. The development of the hardware phase decoder, and the applicability of each to decoding MST radar signals are discussed. A new design for a decoder which is very inexpensive to build, easy to add to an existing system and is capable of decoding on each received pulse using codes with a band length as short as one microsecond is presented.

Sulzer, M. P.↗
NASA NTRS1984

Land Mobile Satellite Service (LMSS) channel simulator: An end-to-end hardware simulation and study of the LMSS communications links

The design and implementation of the Land Mobile Satellite Service (LMSS) channel simulator as a facility for an end to end hardware simulation of the LMSS communications links, primarily with the mobile terminal is described. A number of studies are reported which show the applications of the channel simulator as a facility for validation and assessment of the LMSS design requirements and capabilities by performing quantitative measurements and qualitative audio evaluations for various link design parameters and channel impairments under simulated LMSS operating conditions. As a first application, the LMSS channel simulator was used in the evaluation of a system based on the voice processing and modulation (e.g., NBFM with 30 kHz of channel spacing and a 2 kHz rms frequency deviation for average talkers) selected for the Bell System's Advanced Mobile Phone Service (AMPS). The various details of the hardware design, qualitative audio evaluation techniques, signal to channel impairment measurement techniques, the justifications for criteria of different parameter selection in regards to the voice processing and modulation methods, and the results of a number of parametric studies are further described.

Salmasi, A. B.↗
NASA NTRS1984

Development of robotics facility docking test hardware

Design and fabricate test hardware for NASA's George C. Marshall Space Flight Center (MSFC) are reported. A docking device conceptually developed was fabricated, and two docking targets which provide high and low mass docking loads were required and were represented by an aft 61.0 cm section of a Hubble space telescope (ST) mockup and an upgrading of an existing multimission modular spacecraft (MSS) mockup respectively. A test plan is developed for testing the hardware.

Loughead, T. E.↗
NASA NTRS1985

Space shuttle main engine hardware simulation

The Huntsville Simulation Laboratory (HSL) provides a simulation facility to test and verify the space shuttle main engine (SSME) avionics and software system using a maximum complement of flight type hardware. The HSL permits evaluations and analyses of the SSME avionics hardware, software, control system, and mathematical models. The laboratory has performed a wide spectrum of tests and verified operational procedures to ensure system component compatibility under all operating conditions. It is a test bed for integration of hardware/software/hydraulics. The HSL is and has been an invaluable tool in the design and development of the SSME.

Vick, H. G.↗
NASA NTRS1985

Circulation control lift generation experiment: Hardware development

A circulation control airfoil and its accompanying hardware were developed to allow the investigation of lift generation that is independent of airfoil angle of attack and relative flow velocity. The test equipment, designed for use in a water tunnel, includes the blown airfoil, the support systems for both flow visualization and airfoil load measurement, and the fluid control system, which utilizes hydraulic technology. The primary design tasks, the selected solutions, and the unforseen problems involved in the development of these individual components of hardware are described.

Panontin, T. L.↗
NASA NTRS1985

Development of space telescope non-ORU hardware

Since 1979 work has progressed in the development of the Hubble Space Telescope (HST) mockup. Underwater simulations to evaluate proposed on-orbit servicing tasks have also been done. These tasks involve the planned changeout of scientific instruments and the unscheduled changeout of other orbital replacement units (ORUs) such as batteries and computers. The HST components and subsystems that originally were designated ORUs were the items that were mission critical and were designed for easy changeout. Mockups of 14 non-ORU items were designed and fabricated for the purpose of evaluating the EVA changetasks in the MSFC Neutral Buoyancy Simulator (NBS). The objectives of this design/fabrication/test activity were to design and fabricate the potential ORUs so they contained realistic interfaces and were compatible with the NBS environments. The attachment of the mockup hardware to the spacecraft mockup was similar to the flight version. Also, the hardware connectors were flight-like.

Robertson, K. B.↗
NASA NTRS1986

Hardware configuration for a real-time multiprocessor simulator

The Real-Time Multiprocessor Simulator (RTMPS) is a multiple microcomputer system used to investigate the application of parallel-processing concepts to real-time simulation. This users manual describes the set-up and installation considerations for the RTMPS hardware. Any modifications or further improvements to the RTMPS hardware will be documented in an addendum to this manual.

Blech, R. A.↗