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At least 325 records · Page 18

Investigation of the applicability of a functional programming model to fault-tolerant parallel processing for knowledge-based systems

In a fault-tolerant parallel computer, a functional programming model can facilitate distributed checkpointing, error recovery, load balancing, and graceful degradation. Such a model has been implemented on the Draper Fault-Tolerant Parallel Processor (FTPP). When used in conjunction with the FTPP's fault detection and masking capabilities, this implementation results in a graceful degradation of system performance after faults. Three graceful degradation algorithms have been implemented and are presented. A user interface has been implemented which requires minimal cognitive overhead by the application programmer, masking such complexities as the system's redundancy, distributed nature, variable complement of processing resources, load balancing, fault occurrence and recovery. This user interface is described and its use demonstrated. The applicability of the functional programming style to the Activation Framework, a paradigm for intelligent systems, is then briefly described.

Harper, Richard↗

Low velocity instrumented impact testing of four new damage tolerant carbon/epoxy composite systems

Low velocity drop weight instrumented impact testing was utilized to examine the damage resistance of four recently developed carbon fiber/epoxy resin systems. A fifth material, T300/934, for which a large data base exists, was also tested for comparison purposes. A 16-ply quasi-isotropic lay-up configuration was used for all the specimens. Force/absorbed energy-time plots were generated for each impact test. The specimens were cross-sectionally analyzed to record the damage corresponding to each impact energy level. Maximum force of impact versus impact energy plots were constructed to compare the various systems for impact damage resistance. Results show that the four new damage tolerant fiber/resin systems far outclassed the T300/934 material. The most damage tolerant material tested was the IM7/1962 fiber/resin system.

Lance, D. G.↗

A model for the analysis of fault-tolerant signal processing architectures

This paper develops a new model, using matrices, for the analysis of fault-tolerant multiprocessor systems. The relationship between processors computing useful data, the output data, and the check processors is defined in terms of matrix entries. Unlike the matrix-based models proposed previously for the analysis of digital systems, this model uses only numerical computations rather than logical operations for the analysis of a system. Algorithms to evaluate the fault detection and location capability of the system are proposed which are much less complex than the existing ones. The new model is used to analyze some fault-tolerant architectures proposed for signal-processing applications.

Nair, V. S. S.↗

Effect of braiding process on the damage tolerance of 3-D braided graphite/epoxy composites

One of the key advantages of three-dimensional braided composite materials is their high impact damage tolerance comparing with laminated composites, due to their fully integrated fibrous substrates. In this paper, the effect of different processing methods on the impact damage tolerance of braided graphite/epoxy composite is experimentally assessed. The test specimens are prepared using both of the two existing three-dimensional braiding techniques (the 4-step and the 2-step processes). After the specimens are impacted under controlled impact energy, the damage introduced is studied. Then a compression test is conducted to evaluate the compression strength of the specimens after impact.

El-Shiekh, Aly↗

Real-number codes for fault-tolerant matrix operations on processor arrays

A generalization of existing real number codes is proposed. It is proven that linearity is a necessary and sufficient condition for codes used for fault-tolerant matrix operations such as matrix addition, multiplication, transposition, and LU decomposition. It is also proven that for every linear code defined over a finite field, there exists a corresponding linear real-number code with similar error detecting capabilities. Encoding schemes are given for some of the example codes which fall under the general set of real-number codes. With the help of experiments, a rule is derived for the selection of a particular code for a given application. The performance overhead of fault tolerance schemes using the generalized encoding schemes is shown to be very low, and this is substantiated through simulation experiments.

Nair, V. S. S.↗

Overview of error-tolerant cockpit research

The objectives of research in intelligent cockpit aids and intelligent error-tolerant systems are stated. In intelligent cockpit aids research, the objective is to provide increased aid and support to the flight crew of civil transport aircraft through the use of artificial intelligence techniques combined with traditional automation. In intelligent error-tolerant systems, the objective is to develop and evaluate cockpit systems that provide flight crews with safe and effective ways and means to manage aircraft systems, plan and replan flights, and respond to contingencies. A subsystems fault management functional diagram is given. All information is in viewgraph form.

Abbott, Kathy↗

MAFT: The Multicomputer Architecture for Fault-Tolerance

Multicomputer Architecture for Fault-Tolerance (MAFT) is a loosely coupled multiprocessor system designed to achieve an unreliability of less than 10(exp -10)/hr in flight-critical real time applications. The MAFT design objectives and architecture are presented. The fault-tolerance implementation of major functions in MAFT is also presented, including communication; task scheduling; reconfiguration; clock synchronization; and data handling and voting. The need for Byzantine agreement or approximate agreement in various functions is discussed. Different methods were selected to achieve agreement in various subsystems. These methods are illustrated by a more detailed description of the task scheduling and error handling subsystems.

Kieckhafer, Roger M.↗

The design and proof of correctness of a fault-tolerant circuit

The flowing achievements are presented in view graph form: (1) a formal statement of interactive consistency conditions in the Boyer-Moore logic; (2) a formal statement of the oral messages (OM) algorithm in the Boyer-Moore logic; (3) a mechanically checked proof that OM satisfies the interactive consistency conditions; (4) a mechanically checked proof of the optimality result--no algorithm can tolerate fewer faults than OM yet still achieve interactive consistency; (5) the use of OM in a functional specification for a fault-tolerant device; (6) a formal description of the design of the device; (7) a mechanically checked proof that the device design satisfies the specification; and (8) an implementation of the design in programmable logic arrays.

Bevier, William R.↗

A damage tolerance comparison of IM7/8551 and IM8G/8553 carbon/epoxy composites

A damage tolerance study of two new toughened carbon fiber/epoxy resin systems was undertaken as a continuation of ongoing work into screening new opposites for resistance to foreign object impact. This report is intended to be a supplement to NASA TP 3029 in which four new fiber/resin systems were tested for damage tolerance. Instrumented drop weight impact testing was used to inflict damage to 16-ply quasi-isotropic specimens. Instrumented output data and cross-sectional examinations of the damage zone were utilized to quantify the damage. It was found that the two fiber/resin systems tested in this study were much more impact resistant than an untoughened composite such as T300/934, but were not as impact resistant as other materials previously studied.

Lance, D. G.↗

Verification of the FtCayuga fault-tolerant microprocessor system. Volume 2: Formal specification and correctness theorems

Presented here is a formal specification and verification of a property of a quadruplicately redundant fault tolerant microprocessor system design. A complete listing of the formal specification of the system and the correctness theorems that are proved are given. The system performs the task of obtaining interactive consistency among the processors using a special instruction on the processors. The design is based on an algorithm proposed by Pease, Shostak, and Lamport. The property verified insures that an execution of the special instruction by the processors correctly accomplishes interactive consistency, providing certain preconditions hold, using a computer aided design verification tool, Spectool, and the theorem prover, Clio. A major contribution of the work is the demonstration of a significant fault tolerant hardware design that is mechanically verified by a theorem prover.

Bickford, Mark↗

Verification of the FtCayuga fault-tolerant microprocessor system. Volume 1: A case study in theorem prover-based verification

The design and formal verification of a hardware system for a task that is an important component of a fault tolerant computer architecture for flight control systems is presented. The hardware system implements an algorithm for obtaining interactive consistancy (byzantine agreement) among four microprocessors as a special instruction on the processors. The property verified insures that an execution of the special instruction by the processors correctly accomplishes interactive consistency, provided certain preconditions hold. An assumption is made that the processors execute synchronously. For verification, the authors used a computer aided design hardware design verification tool, Spectool, and the theorem prover, Clio. A major contribution of the work is the demonstration of a significant fault tolerant hardware design that is mechanically verified by a theorem prover.

Srivas, Mandayam↗

Materials and processes laboratory composite materials characterization task, part 1. Damage tolerance

A test run was performed on IM6/3501-6 carbon-epoxy in which the material was processed, machined into specimens, and tested for damage tolerance capabilities. Nondestructive test data played a major role in this element of composite characterization. A time chart was produced showing the time the composite material spent within each Branch or Division in order to identify those areas which produce a long turnaround time. Instrumented drop weight testing was performed on the specimens with nondestructive evaluation being performed before and after the impacts. Destructive testing in the form of cross-sectional photomicrography and compression-after-impact testing were used. Results show that the processing and machining steps needed to be performed more rapidly if data on composite material is to be collected within a reasonable timeframe. The results of the damage tolerance testing showed that IM6/3501-6 is a brittle material that is very susceptible to impact damage.

Nettles, A. T.↗

Simulated fault injection - A methodology to evaluate fault tolerant microprocessor architectures

A simulation-based fault-injection method for validating fault-tolerant microprocessor architectures is described. The approach uses mixed-mode simulation (electrical/logic analysis), and injects transient errors in run-time to assess the resulting fault impact. As an example, a fault-tolerant architecture which models the digital aspects of a dual-channel real-time jet-engine controller is used. The level of effectiveness of the dual configuration with respect to single and multiple transients is measured. The results indicate 100 percent coverage of single transients. Approximately 12 percent of the multiple transients affect both channels; none result in controller failure since two additional levels of redundancy exist.

Choi, Gwan S.↗

Reliability of voting in fault-tolerant software systems for small output spaces

Under a voting strategy in a fault-tolerant software system there is a difference between correctness and agreement. An independent N-version programming reliability model is proposed for treating small output spaces which distinguishes between correctness and agreement. System reliability is investigated using analytical relationships and simulation. A consensus majority voting stratey is proposed and its performance is analyzed and compared with other voting strategies. A consensus voting strategy automatically adapts the voting to diffeerent component reliability and output space cardinality characteristics. It is shown that absolute majority voting strategy provides a lower bound on the reliability provided by the consensus majority, and the 2-of-n voting strategy an upper bound. If r is the cardinality of output space it is proved that 1/r is a lower bound on the average reliability of fault-tolerant system components below which the system reliability begins to deteriorate as more versions are added.

Mcallister, David F.↗

Synthesis of structural/control systems robust with respect to design variable tolerances

A methodology is presented for the synthesis of control augmented structures which can be modeled as an assemblage of beam, truss, and nonstructural mass elements augmented by a robust noncollocated direct output feedback control system. The control system is robust in the sense that it can tolerate manufacturing and realization errors. The robust control system is synthesized using a constraint buffering technique in conjunction with the approximation concepts approach to system synthesis. All of the design constraints on the system, including the dynamic stability, are buffered by a nonlinear quantity that is a function of acceptable tolerances on the design variables and the sensitivity of the constraints to changes in these design variables. Numerical results which illustrate the effectiveness of the method presented are given.

Thomas, H. L.↗

Fault recovery characteristics of the fault tolerant multi-processor

The fault handling performance of the fault tolerant multiprocessor (FTMP) was investigated. Fault handling errors detected during fault injection experiments were characterized. In these fault injection experiments, the FTMP disabled a working unit instead of the faulted unit once every 500 faults, on the average. System design weaknesses allow active faults to exercise a part of the fault management software that handles byzantine or lying faults. It is pointed out that these weak areas in the FTMP's design increase the probability that, for any hardware fault, a good LRU (line replaceable unit) is mistakenly disabled by the fault management software. It is concluded that fault injection can help detect and analyze the behavior of a system in the ultra-reliable regime. Although fault injection testing cannot be exhaustive, it has been demonstrated that it provides a unique capability to unmask problems and to characterize the behavior of a fault-tolerant system.

Padilla, Peter A.↗

Fault tolerant, radiation hard, high performance digital signal processor

An architecture has been developed for a high-performance VLSI digital signal processor that is highly reliable, fault-tolerant, and radiation-hard. The signal processor, part of a spacecraft receiver designed to support uplink radio science experiments at the outer planets, organizes the connections between redundant arithmetic resources, register files, and memory through a shuffle exchange communication network. The configuration of the network and the state of the processor resources are all under microprogram control, which both maps the resources according to algorithmic needs and reconfigures the processing should a failure occur. In addition, the microprogram is reloadable through the uplink to accommodate changes in the science objectives throughout the course of the mission. The processor will be implemented with silicon compiler tools, and its design will be verified through silicon compilation simulation at all levels from the resources to full functionality. By blending reconfiguration with redundancy the processor implementation is fault-tolerant and reliable, and possesses the long expected lifetime needed for a spacecraft mission to the outer planets.

Holmann, Edgar↗

Fault-tolerance techniques for high-speed fiber-optic networks

Four fiber optic network topologies (linear bus, ring, central star, and distributed star) are discussed relative to their application to high data throughput, fault tolerant networks. The topologies are also examined in terms of redundancy and the need to provide for single point, failure free (or better) system operation. Linear bus topology, although traditionally the method of choice for wire systems, presents implementation problems when larger fiber optic systems are considered. Ring topology works well for high speed systems when coupled with a token passing protocol, but it requires a significant increase in protocol complexity to manage system reconfiguration due to ring and node failures. Star topologies offer a natural fault tolerance, without added protocol complexity, while still providing high data throughput capability.

Deruiter, John↗