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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 343 records · Page 19

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NASA NTRS1986

Ultraviolet spectrometer and polarimeter (UVSP) software development and hardware tests for the solar maximum mission

The Ultraviolet Spectrometer/Polarimeter Instrument (UVSP) for the Solar Maximum Mission (SMM) was based on the re-use of the engineering model of the high resolution ultraviolet spectrometer developed for the OSO-8 mission. Lockheed assumed four distinct responsibilities in the UVSP program: technical evaluation of the OSO-8 engineering model; technical consulting on the electronic, optical, and mechanical modifications to the OSO-8 engineering model hardware; design and development of the UVSP software system; and scientific participation in the operations and analysis phase of the mission. Lockheed also provided technical consulting and assistance with instrument hardware performance anomalies encountered during the post launch operation of the SMM observatory. An index to the quarterly reports delivered under the contract are contained, and serves as a useful capsule history of the program activity.

Bruner, M. E.↗

NASA NTRS1987

Hardware fault insertion and instrumentation system: Mechanization and validation

Automated test capability for extensive low-level hardware fault insertion testing is developed. The test capability is used to calibrate fault detection coverage and associated latency times as relevant to projecting overall system reliability. Described are modifications made to the NASA Ames Reconfigurable Flight Control System (RDFCS) Facility to fully automate the total test loop involving the Draper Laboratories' Fault Injector Unit. The automated capability provided included the application of sequences of simulated low-level hardware faults, the precise measurement of fault latency times, the identification of fault symptoms, and bulk storage of test case results. A PDP-11/60 served as a test coordinator, and a PDP-11/04 as an instrumentation device. The fault injector was controlled by applications test software in the PDP-11/60, rather than by manual commands from a terminal keyboard. The time base was especially developed for this application to use a variety of signal sources in the system simulator.

Benson, J. W.↗

NASA NTRS1988

Design guidelines for robotically serviceable hardware

Research being conducted at the Goddard Space Flight Center into the development of guidelines for the design of robotically serviceable spaceflight hardware is described. A mock-up was built based on an existing spaceflight system demonstrating how these guidelines can be applied to actual hardware. The report examines the basic servicing philosophy being studied and how this philosophy is reflected in the formulation of design guidelines for robotic servicing. A description of the mock-up is presented with emphasis on the design features that make it robot friendly. Three robotic servicing schemes fulfilling the design guidelines were developed for the mock-up. These servicing schemes are examined as to how their implementation was affected by the constraints of the spacecraft system on which the mock-up is based.

Gordon, Scott A.↗

NASA NTRS1989

Study of a unified hardware and software fault-tolerant architecture

A unified architectural concept, called the Fault Tolerant Processor Attached Processor (FTP-AP), that can tolerate hardware as well as software faults is proposed for applications requiring ultrareliable computation capability. An emulation of the FTP-AP architecture, consisting of a breadboard Motorola 68010-based quadruply redundant Fault Tolerant Processor, four VAX 750s as attached processors, and four versions of a transport aircraft yaw damper control law, is used as a testbed in the AIRLAB to examine a number of critical issues. Solutions of several basic problems associated with N-Version software are proposed and implemented on the testbed. This includes a confidence voter to resolve coincident errors in N-Version software. A reliability model of N-Version software that is based upon the recent understanding of software failure mechanisms is also developed. The basic FTP-AP architectural concept appears suitable for hosting N-Version application software while at the same time tolerating hardware failures. Architectural enhancements for greater efficiency, software reliability modeling, and N-Version issues that merit further research are identified.

Lala, Jaynarayan↗

NASA NTRS1988

A hardware implementation of a relaxation algorithm to segment images

Relaxation labelling is a mathematical technique frequently applied in image processing algorithms. In particular, it is extensively used for the purpose of segmenting images. The paper presents a hardware implementation of a segmentation algorithm, for images consisting of two regions, based on relaxation labelling. The algorithm determines, for each pixel, the probability that it should be labelled as belonging to a particular region, for all regions in the image. The label probabilities (labellings) of every pixel are iteratively updated, based on those of the pixel's neighbors, until they converge. The pixel is then assigned to the region correspondent to the maximum label probability. The system consists of a control unit and of a pipeline of segmentation stages. Each segmentation stage emulates in the hardware an iteration of the relaxation algorithm. The design of the segmentation stage is based on commercially available digital signal processing integrated circuits. Multiple iterations are accomplished by stringing stages together or by looping the output of a stage, or string of stages, to its input. The system interfaces with a generic host computer. Given the modularity of the architecture, performance can be enhanced by merely adding segmentation stages.

Loda, Antonio G.↗

NASA NTRS1989

Returned Solar Max hardware degradation study results

The Solar Maximum Repair Mission returned with the replaced hardware that had been in low Earth orbit for over four years. The materials of this returned hardware gave the aerospace community an opportunity to study the realtime effects of atomic oxygen, solar radiation, impact particles, charged particle radiation, and molecular contamination. The results of these studies are summarized.

Triolo, Jack J.↗

NASA NTRS1988

Hardware and software fault tolerance - A unified architectural approach

The loss of hardware fault tolerance which often arises when design diversity is used to improve the fault tolerance of computer software is considered analytically, and a unified design approach is proposed to avoid the problem. The fundamental theory of fault-tolerant (FT) architectures is reviewed; the current status of design-diversity software development is surveyed; and the FT-processor/attached-processor (FTP/AP) architecture developed by Lala et al. (1986) is described in detail and illustrated with diagrams. FTP/AP is shown to permit efficient implementation of N-version FT software while still tolerating random hardware failures with very high coverage; the reliability is found to be significantly higher than that of conventional majority-vote N-version software.

Lala, Jaynarayan H.↗

NASA NTRS1989

The aerospace energy systems laboratory: Hardware and software implementation

For many years NASA Ames Research Center, Dryden Flight Research Facility has employed automation in the servicing of flight critical aircraft batteries. Recently a major upgrade to Dryden's computerized Battery Systems Laboratory was initiated to incorporate distributed processing and a centralized database. The new facility, called the Aerospace Energy Systems Laboratory (AESL), is being mechanized with iAPX86 and iAPX286 hardware running iRMX86. The hardware configuration and software structure for the AESL are described.

Glover, Richard D.↗

NASA NTRS1989

Development of inspection techniques for quantitatively measuring surface contamination on SRM hardware

A contaminant is any material or substance which is potentially undesirable or which may adversely affect any part, component, or assembly. Contamination control of SRM hardware surfaces is a serious concern, for both Thiokol and NASA, with particular concern for contaminants which may adversely affect bonding surfaces. The purpose of this study is to develop laboratory analytical techniques which will make it possible to certify the cleanliness of any designated surface, with special focus on particulates (dust, dirt, lint, etc.), oils (hydrocarbons, silicones, plasticizers, etc.), and greases (HD-2, fluorocarbon grease, etc.). The hardware surfaces of concern will include D6AC steel, aluminum alloys, anodized aluminum alloys, glass/phenolic, carbon/phenolic, NBR/asbestos-silica, and EPDM rubber.

Law, R. D.↗

NASA NTRS1989

The use of real-time, hardware-in-the-loop simulation in the design and development of the new Hughes HS601 spacecraft attitude control system

Realtime simulation and hardware-in-the-loop testing is being used extensively in all phases of the design, development, and testing of the attitude control system (ACS) for the new Hughes HS601 satellite bus. Realtime, hardware-in-the-loop simulation, integrated with traditional analysis and pure simulation activities is shown to provide a highly efficient and productive overall development program. Implementation of high fidelity simulations of the satellite dynamics and control system algorithms, capable of real-time execution (using applied Dynamics International's System 100), provides a tool which is capable of being integrated with the critical flight microprocessor to create a mixed simulation test (MST). The MST creates a highly accurate, detailed simulated on-orbit test environment, capable of open and closed loop ACS testing, in which the ACS design can be validated. The MST is shown to provide a valuable extension of traditional test methods. A description of the MST configuration is presented, including the spacecraft dynamics simulation model, sensor and actuator emulators, and the test support system. Overall system performance parameters are presented. MST applications are discussed; supporting ACS design, developing on-orbit system performance predictions, flight software development and qualification testing (augmenting the traditional software-based testing), mission planning, and a cost-effective subsystem-level acceptance test. The MST is shown to provide an ideal tool in which the ACS designer can fly the spacecraft on the ground.

Slafer, Loren I.↗

NASA NTRS1989

A few modeling and rendering techniques for computer graphics and their implementation on ultra hardware

Ultra network is a recently installed very high speed graphic hardware at NASA Langley Research Center. The Ultra Network interfaced to Voyager through its HSX channel is capable of transmitting up to 800 million bits of information per second. It is capable of displaying fifteen to twenty frames of precomputed images of size 1024 x 2368 with 24 bits of color information per pixel per second. Modeling and rendering techniques are being developed in computer graphics and implemented on Ultra hardware. A ray tracer is being developed for use at the Flight Software and Graphic branch. Changes were made to make the ray tracer compatible with Voyager.

Bidasaria, Hari↗

NASA NTRS1984

Energy Efficient Engine combustor test hardware detailed design report

The Energy Efficient Engine (E3) Combustor Development effort was conducted as part of the overall NASA/GE E3 Program. This effort included the selection of an advanced double-annular combustion system design. The primary intent was to evolve a design which meets the stringent emissions and life goals of the E3 as well as all of the usual performance requirements of combustion systems for modern turbofan engines. Numerous detailed design studies were conducted to define the features of the combustion system design. Development test hardware was fabricated, and an extensive testing effort was undertaken to evaluate the combustion system subcomponents in order to verify and refine the design. Technology derived from this development effort will be incorporated into the engine combustion system hardware design. This advanced engine combustion system will then be evaluated in component testing to verify the design intent. What is evolving from this development effort is an advanced combustion system capable of satisfying all of the combustion system design objectives and requirements of the E3. Fuel nozzle, diffuser, starting, and emissions design studies are discussed.

Burrus, D. L.↗

NASA NTRS1989

Hardware impacts to software development strategies - The history of the development of the Mars Observer Payload Data Subsystem embedded real-time software

Ways in which parallel hardware development and high level requirements changes have influenced Mars Observer Payload Data Subsystem (PDS) flight software development are discussed. Particular attention is given to ways in which the evolving hardware product and changing requirements have led to repeated modification to software requirements, design, code, and test tools and a delay in the closure of corresponding phases of the software development life cycle. Design and implementation problems which were encountered during the PDS software development effort are described.

Elson, Anne B.↗

NASA NTRS1990

ACTS Hardware - A Pictorial

The salient features of the Advanced Communiations Technology Satellite (ACTS) that is being presently developed under NASA sponsorship and is now in the stage of flight hardware assembly and integration, are described. Particular attention is given to the hardware components of the spacecraft, the engineering model communication package, and special test equipment. The ACTS is being prepared for a launch in May of 1992.

Gargione, Frank↗

NASA NTRS1990

Hardware-assisted software clock synchronization for homogeneous distributed systems

A clock synchronization scheme that strikes a balance between hardware and software solutions is proposed. The proposed is a software algorithm that uses minimal additional hardware to achieve reasonably tight synchronization. Unlike other software solutions, the guaranteed worst-case skews can be made insensitive to the maximum variation of message transit delay in the system. The scheme is particularly suitable for large partially connected distributed systems with topologies that support simple point-to-point broadcast algorithms. Examples of such topologies include the hypercube and the mesh interconnection structures.

Ramanathan, P.↗

NASA NTRS1989

Automated power distribution system hardware

An automated power distribution system testbed for the space station common modules has been developed. It incorporates automated control and monitoring of a utility-type power system. Automated power system switchgear, control and sensor hardware requirements, hardware design, test results, and potential applications are discussed. The system is designed so that the automated control and monitoring of the power system is compatible with both a 208-V, 20-kHz single-phase AC system and a high-voltage (120 to 150 V) DC system.

Anderson, Paul M.↗

NASA NTRS1990

Health monitoring system for the SSME - Hardware architecture study

This paper presents a hardware architecture for a health monitoring system (HMS) for the SSME. The architecture study was conducted in conjunction with a NASA sponsored program to develop a framework for SSME HMS for (1) ground test and, potentially (2) flight applications. The requirements for both systems are both stated and analyzed. A multiprocessor distributed VME system is envisioned for the ground-test hardware. By repackaging the boards, the same concept is shown to be usable for the flight system. The paper concludes with an analysis of weight, power, and reliability with respect to variations in functionality.

Kamenetz, Jeffry K.↗

NASA NTRS1990

Hardware verification at Computational Logic, Inc.

The following topics are covered in viewgraph form: (1) hardware verification; (2) Boyer-Moore logic; (3) core RISC; (4) the FM8502 fabrication, implementation specification, and pinout; (5) hardware description language; (6) arithmetic logic generator; (7) near term expected results; (8) present trends; (9) future directions; (10) collaborations and technology transfer; and (11) technology enablers.

Brock, Bishop C.↗