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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 343 records · Page 19
All sourcesNASA NTRSDOE OSTI
NASA NTRS1982

Simplification of power electronics for ion thruster neutralizers

A need exists for less complex and lower cost ion thruster systems. Design approaches and the demonstration of neutralizer power electronics for relaxed neutralizer keeper, tip heater, and vaporizer requirements are discussed. The neutralizer circuitry is operated from a 200 to 400 V bus and demonstrates an order of magnitude reduction in parts count. Furthermore, a new technique is described for regulating tip heater power and automatically switching over to provide keeper power with only four additional components. A new design to control the flow rate of the neutralizer with one integrated circuit is also presented.

Gruber, R. P.↗
NASA NTRS1986

DSP-based non-coherent dual detector demodulator for land mobile radio channels

This paper outlines the development of a digital demodulator suitable for the non-coherent detection of various modulation formats including: Phase Shift Keying (PSK), Continuous Phase Frequency Shift Keying (CPFSK) and Frequency Modulation (FM). The demodulator design concept has been derived with a view towards a single integrated circuit (IC) implementation. Two detectors, one non-coherent and one differentially coherent, operate concurrently, providing data detection and automatic frequency control (AFC). Bit error rate results are provided which illustrate the receiver performance in white Gaussian noise.

Saulnier, Gary J.↗
NASA NTRS1989

Study of advanced InSb arrays for SIRTF (Space Infrared Telescope Facility)

The Santa Barbara Research Center has completed a study leading to the development of advanced Indium Antimonide detector arrays for the Space Infrared Telescope Facility (SIRTF) Focal Plane Array Detector (FPAD) Subsystem of the Infrared Array Camera (IRAC) Band 1. The overall goal of the study was to perform design tradeoff studies, analysis and research to develop a Direct Readout Integrated Circuit to be hybridized to an advanced, high performance InSb detector array that would satisfy the technical requirements for Band 1 as specified in the IRAC Instrument Requirements Document (IRD), IRAC-202. The overall goal of the study was divided into both a near-term goal and a far-term goal. The near-term goal identifies current technology available that approaches, and in some cases meets the program technological goals as specified in IRAC-202. The far-term goal identifies technology development required to completely achieve SIRTF program goals. Analyses of potential detector materials indicates that InSb presently meets all Band 1 requirements and is considered to be the baseline approach due to technical maturity. The major issue with regard to photovoltaic detectors such as InSb and HgCdTe is to achieve a reduction in detector capacitance.

Hoffman, Alan↗
NASA NTRS1991

Cross-Quint-Bridge Resistor

Integrated-circuit conductive test pattern intended to provide data on effects of design widths and design spacings upon actual widths of conductive lines. Provides for electrical measurements both on lines of unknown width and on features having known dimensions. Data from measurements on five bridges used to determine four parameters of mathematical model describing system. In principle, pattern determines effects of width and spacing and interaction between them.

Hannaman, David J.↗
NASA NTRS1991

Designing Accelerated Tests Of Electromigration

Method for design of accelerated tests of electromigration (as in microscopic conductors in integrated circuits) based partly on simplified mathematical model of electromigration and partly on error analysis. Objective to determine quickly operating life of tested components under normal operating conditions by extrapolation from lifetime measurements at operating stresses greater than normal. Involves compromise between reducing testing time by increasing stresses and reducing uncertainty in extrapolated lifetime by decreasing stresses.

Buehler, Martin G.↗
NASA NTRS1993

Predicting Lifetimes Of CMOS ASIC's From Test Data

Concise report discusses recent developments in use of semiempirical mathematical models to predict rates of failure and operating lifetimes of complementary metal oxide/semiconductor (CMOS) application-specific integrated circuits (ASIC's). Each model represents specific mechanism of failure. Once failure mechanisms and models relevant to given ASIC chosen, adjustable parameters in models fitted to life-test data acquired from representative integrated-circuit structures on test coupons fabricated along with ASIC's. Then design parameters of ASIC's incorporated into models, and models yield lifetimes.

Buehler, Martin G.↗
NASA NTRS1991

An application specific integrated circuit based multi-anode microchannel array readout system

Size reduction of two new multi-anode microchannel array (MAMA) readout systems is described. The systems are based on two analog and one digital application specific integrated circuits (ASICs). The new readout systems reduce volume over previous discrete designs by 80 percent while improving electrical performance on virtually every significant parameter. Emphasis is made on the packaging used to achieve the volume reduction. Surface mount technology (SMT) is combined with modular construction for the analog portion of the readout. SMT reliability concerns and the board area impact of MIL SPEC SMT components is addressed. Package selection for the analog ASIC is discussed. Future sytems will require even denser packaging and the volume reduction progression is shown.

Smeins, Larry G.↗
NASA NTRS1994

Simulation of materials processing: Fantasy or reality?

This experiment introduces students to the application of computer-aided design (CAD) and analysis of materials processing in the context of integrated circuit (IC) fabrication. The fabrication of modern IC's is a complex process which consists of several sequential steps. These steps involve the precise control of processing variables such as temperature, humidity, and ambient gas composition. In essence, the particular process employed during the fabrication becomes a 'recipe'. Due to economic and other considerations, CAD is becoming an indispensable part of the development of new recipes for IC fabrication. In particular, this experiment permits the students to explore the CAD of the thermal oxidation of silicon.

Jenkins, Thomas J.↗
NASA NTRS1998

Use of SX Series Devices and IEEE 1149.1 JTAG Circuitry

This report summarizes the use of SX series devices and their JTAG 1149.1 circuitry. 'JTAG' circuitry was originally designed to standardize testing of boards via a simple control port interface electrically without having to use devices such as a bed of nails tester. JTAG is also used for other functions such as executing built-in-test sequences, identifying devices, or, through custom instructions, other functions designed in by the chip designer. The JTAG circuitry is designed for test only; it has no functional use in the integrated circuit during normal operations. The JTAG circuitry and the mode of the device is controlled by a circuit block known as the 'TAP controller,' which is a sixteen-state state machine along with various registers. The controller is normally in an operational state known as TEST-LOGIC-RESET. In this state, the device is held in a fully functional, operating mode. However, a Single Event Upset (SEU) may remove the TAP controller from this state, causing a loss of control of the integrated circuit, unless certain precautions are taken, such as grounding the optional JTAG TRST signal.

Katz, Richard B.↗
NASA NTRS1998

Use of SX Series Devices and IEEE 1149.1 JTAG Circuitry

This report summarizes the use of SX series devices and their JTAG 1149.1 circuitry. 'JTAG' circuitry was originally designed to standardize testing of boards via a simple control port interface electrically without having to use devices such as a bed of nails tester. JTAG is also used for other functions such as executing built-in-test sequences, identifying devices, or, through custom instructions, other functions designed in by the chip designer. The JTAG circuitry is designed for test only; it has no functional use in the integrated circuit during normal operations. The JTAG circuitry and the mode of the device is controlled by a circuit block known as the 'TAP controller,' which is a sixteen-state state machine along with various registers. The controller is normally in an operational state known as TEST-LOGIC-RESET. In this state, the device is held in a fully functional, operational mode. However, a Single Event Upset (SEU) may remove the TAP controller from this state, causing a loss of control of the integrated circuit, unless certain precautions are taken, such as grounding the optional JTAG TRST signal.

Katz, Richard B.↗
NASA NTRS1993

A 128 x 128 CMOS Active Pixel Image Sensor for Highly Integrated Imaging Systems

A new CMOS-based image sensor that is intrinsically compatible with on-chip CMOS circuitry is reported. The new CMOS active pixel image sensor achieves low noise, high sensitivity, X-Y addressability, and has simple timing requirements. The image sensor was fabricated using a 2 micrometer p-well CMOS process, and consists of a 128 x 128 array of 40 micrometer x 40 micrometer pixels. The CMOS image sensor technology enables highly integrated smart image sensors, and makes the design, incorporation and fabrication of such sensors widely accessible to the integrated circuit community.

Mendis, Sunetra K.↗
NASA NTRS2007

Imaging Spectrometer on a Chip

A proposed visible-light imaging spectrometer on a chip would be based on the concept of a heterostructure comprising multiple layers of silicon-based photodetectors interspersed with long-wavelength-pass optical filters. In a typical application, this heterostructure would be replicated in each pixel of an image-detecting integrated circuit of the active-pixel-sensor type (see figure). The design of the heterostructure would exploit the fact that within the visible portion of the spectrum, the characteristic depth of penetration of photons increases with wavelength. Proceeding from the front toward the back, each successive long-wavelength-pass filter would have a longer cutoff wavelength, and each successive photodetector would be made thicker to enable it to absorb a greater proportion of incident longer-wavelength photons. Incident light would pass through the first photodetector and encounter the first filter, which would reflect light having wavelengths shorter than its cutoff wavelength and pass light of longer wavelengths. A large portion of the incident and reflected shorter-wavelength light would be absorbed in the first photodetector. The light that had passed through the first photodetector/filter pair of layers would pass through the second photodetector and encounter the second filter, which would reflect light having wavelengths shorter than its cutoff wavelength while passing light of longer wavelengths. Thus, most of the light reflected by the second filter would lie in the wavelength band between the cutoff wavelengths of the first and second filters. Thus, further, most of the light absorbed in the second photodetector would lie in this wavelength band. In a similar manner, each successive photodetector would detect, predominantly, light in a successively longer wavelength band bounded by the shorter cutoff wavelength of the preceding filter and the longer cutoff wavelength of the following filter.

Wang, Yu↗
NASA NTRS2017

Characterization of Low Mass Deformable Mirrors and ASIC Driver for High-Contrast Imaging

The development of compact, high performance Deformable Mirrors (DMs) is one of the most important techno-logical challenges for high-contrast imaging on space missions. Microscale Inc. has fabricated and characterized piezoelectric stack actuator deformable mirrors (PZT-DMs) and Application-Speci c Integrated Circuit (ASIC) drivers for direct integration. The DM-ASIC system is designed to eliminate almost all cables, enabling a very compact optical system with low mass and low power consumption. We report on the optical tests used to evaluate the performance of the DM and ASIC units. We also compare the results to the requirements for space-based high-contrast imaging of exoplanets. .

Prada, Camilo Mejia↗
NASA NTRS2000

Advanced Atmospheric Water Vapor DIAL Detection System

Measurement of atmospheric water vapor is very important for understanding the Earth's climate and water cycle. The remote sensing Differential Absorption Lidar (DIAL) technique is a powerful method to perform such measurement from aircraft and space. This thesis describes a new advanced detection system, which incorporates major improvements regarding sensitivity and size. These improvements include a low noise advanced avalanche photodiode detector, a custom analog circuit, a 14-bit digitizer, a microcontroller for on board averaging and finally a fast computer interface. This thesis describes the design and validation of this new water vapor DIAL detection system which was integrated onto a small Printed Circuit Board (PCB) with minimal weight and power consumption. Comparing its measurements to an existing DIAL system for aerosol and water vapor profiling validated the detection system.

Refaat, Tamer F.↗
NASA NTRS2010

Configurable Multi-Purpose Processor

Advancements in technology have allowed the miniaturization of systems used in aerospace vehicles. This technology is driven by the need for next-generation systems that provide reliable, responsive, and cost-effective range operations while providing increased capabilities such as simultaneous mission support, increased launch trajectories, improved launch, and landing opportunities, etc. Leveraging the newest technologies, the command and telemetry processor (CTP) concept provides for a compact, flexible, and integrated solution for flight command and telemetry systems and range systems. The CTP is a relatively small circuit board that serves as a processing platform for high dynamic, high vibration environments. The CTP can be reconfigured and reprogrammed, allowing it to be adapted for many different applications. The design is centered around a configurable field-programmable gate array (FPGA) device that contains numerous logic cells that can be used to implement traditional integrated circuits. The FPGA contains two PowerPC processors running the Vx-Works real-time operating system and are used to execute software programs specific to each application. The CTP was designed and developed specifically to provide telemetry functions; namely, the command processing, telemetry processing, and GPS metric tracking of a flight vehicle. However, it can be used as a general-purpose processor board to perform numerous functions implemented in either hardware or software using the FPGA s processors and/or logic cells. Functionally, the CTP was designed for range safety applications where it would ultimately become part of a vehicle s flight termination system. Consequently, the major functions of the CTP are to perform the forward link command processing, GPS metric tracking, return link telemetry data processing, error detection and correction, data encryption/ decryption, and initiate flight termination action commands. Also, the CTP had to be designed to survive and operate in a launch environment. Additionally, the CTP was designed to interface with the WFF (Wallops Flight Facility) custom-designed transceiver board which is used in the Low Cost TDRSS Transceiver (LCT2) also developed by WFF. The LCT2 s transceiver board demodulates commands received from the ground via the forward link and sends them to the CTP, where they are processed. The CTP inputs and processes data from the inertial measurement unit (IMU) and the GPS receiver board, generates status data, and then sends the data to the transceiver board where it is modulated and sent to the ground via the return link. Overall, the CTP has combined processing with the ability to interface to a GPS receiver, an IMU, and a pulse code modulation (PCM) communication link, while providing the capability to support common interfaces including Ethernet and serial interfaces boarding a relatively small-sized, lightweight package.

Valencia, J. Emilio↗
NASA NTRS1999

Design of the Wind Tunnel Model Communication Controller Board

The NASA Langley Research Center's Wind Tunnel Reinvestment project plans to shrink the existing data acquisition electronics to fit inside a wind tunnel model. Space limitations within a model necessitate a distributed system of Application Specific Integrated Circuits (ASICs) rather than a centralized system based on PC boards. This thesis will focus on the design of the prototype of the communication Controller board. A portion of the communication Controller board is to be used as the basis of an ASIC design. The communication Controller board will communicate between the internal model modules and the external data acquisition computer. This board is based around an Field Programmable Gate Array (FPGA), to allow for reconfigurability. In addition to the FPGA, this board contains buffer Random Access Memory (RAM), configuration memory (EEPROM), drivers for the communications ports, and passive components.

Wilson, William C.↗
NASA NTRS2003

Capturing a failure of an ASIC in-situ, using infrared radiometry and image processing software

Failures in electronic devices can sometimes be tricky to locate-especially if they are buried inside radiation-shielded containers designed to work in outer space. Such was the case with a malfunctioning ASIC (Application Specific Integrated Circuit) that was drawing excessive power at a specific temperature during temperature cycle testing. To analyze the failure, infrared radiometry (thermography) was used in combination with image processing software to locate precisely where the power was being dissipated at the moment the failure took place. The IR imaging software was used to make the image of the target and background, appear as unity. As testing proceeded and the failure mode was reached, temperature changes revealed the precise location of the fault. The results gave the design engineers the information they needed to fix the problem. This paper describes the techniques and equipment used to accomplish this failure analysis.

infrared↗
NASA NTRS2007

Power-Amplifier Module for 145 to 165 GHz

A power-amplifier module that operates in the frequency range of 145 to 165 GHz has been designed and constructed as a combination of (1) a previously developed monolithic microwave integrated circuit (MMIC) power amplifier and (2) a waveguide module. The amplifier chip was needed for driving a high-electron-mobility-transistor (HEMT) frequency doubler. While it was feasible to connect the amplifier and frequency-doubler chips by use of wire bonds, it was found to be much more convenient to test the amplifier and doubler chips separately. To facilitate separate testing, it was decided to package the amplifier and doubler chips in separate waveguide modules. Figure 1 shows the resulting amplifier module. The amplifier chip was described in "MMIC HEMT Power Amplifier for 140 to 170 GHz" (NPO-30127), NASA Tech Briefs, Vol. 27, No. 11, (November 2003), page 49. To recapitulate: This is a three-stage MMIC power amplifier that utilizes HEMTs as gain elements. The amplifier was originally designed to operate in the frequency range of 140 to 170 GHz. The waveguide module is based on a previously developed lower frequency module, redesigned to support operation in the frequency range of 140 to 220 GHz. Figure 2 presents results of one of several tests of the amplifier module - measurements of output power and gain as functions of input power at an output frequency of 150 GHz. Such an amplifier module has many applications to test equipment for power sources above 100 GHz.

Samoska, Lorene↗