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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 37 records · Page 2
All sourcesNASA NTRSDOE OSTI
NASA NTRS2011

Fast Imaging Detector Readout Circuits with In-Pixel ADCs for Fourier Transform Imaging Spectrometers

Focal plane arrays (FPAs) with high frame rates and many pixels benefit several upcoming Earth science missions including GEO-CAPE, GACM, and ACE by enabling broader spatial coverage and higher spectral resolution. FPAs for the PanFTS, a high spatial resolution Fourier transform spectrometer and a candidate instrument for the GEO-CAPE mission are the focus of the developments reported here, but this FPA technology has the potential to enable a variety of future measurements and instruments. The ESTO ACT Program funded the developed of a fast readout integrated circuit (ROIC) based on an innovative in-pixel analog-to-digital converter (ADC). The 128 X 128 pixel ROIC features 60 ?m pixels, a 14-bit ADC in each pixel and operates at a continuous frame rate of 14 kHz consuming only 1.1 W of power. The ROIC outputs digitized data completely eliminating the bulky, power consuming signal chains needed by conventional FPAs. The 128 X 128 pixel ROIC has been fabricated in CMOS and tested at the Jet Propulsion Laboratory. The current version is designed to be hybridized with PIN photodiode arrays via indium bump bonding for light detection in the visible and ultraviolet spectral regions. However, the ROIC design incorporates a small photodiode in each cell to permit detailed characterization of the ROICperformance without the need for hybridization. We will describe the essential features of the ROIC design and present results of ROIC performance measurements.

focal plane arrays (FPAs)↗
NASA NTRS2013

Mixed Linear/Square-Root Encoded Single-Slope Ramp Provides Low-Noise ADC with High Linearity for Focal Plane Arrays

Single-slope analog-to-digital converters (ADCs) are particularly useful for onchip digitization in focal plane arrays (FPAs) because of their inherent monotonicity, relative simplicity, and efficiency for column-parallel applications, but they are comparatively slow. Squareroot encoding can allow the number of code values to be reduced without loss of signal-to-noise ratio (SNR) by keeping the quantization noise just below the signal shot noise. This encoding can be implemented directly by using a quadratic ramp. The reduction in the number of code values can substantially increase the quantization speed. However, in an FPA, the fixed pattern noise (FPN) limits the use of small quantization steps at low signal levels. If the zero-point is adjusted so that the lowest column is onscale, the other columns, including those at the center of the distribution, will be pushed up the ramp where the quantization noise is higher. Additionally, the finite frequency response of the ramp buffer amplifier and the comparator distort the shape of the ramp, so that the effective ramp value at the time the comparator trips differs from the intended value, resulting in errors. Allowing increased settling time decreases the quantization speed, while increasing the bandwidth increases the noise. The FPN problem is solved by breaking the ramp into two portions, with some fraction of the available code values allocated to a linear ramp and the remainder to a quadratic ramp. To avoid large transients, both the value and the slope of the linear and quadratic portions should be equal where they join. The span of the linear portion must cover the minimum offset, but not necessarily the maximum, since the fraction of the pixels above the upper limit will still be correctly quantized, albeit with increased quantization noise. The required linear span, maximum signal and ratio of quantization noise to shot noise at high signal, along with the continuity requirement, determines the number of code values that must be allocated to each portion. The distortion problem is solved by using a lookup table to convert captured code values back to signal levels. The values in this table will be similar to the intended ramp value, but with a correction for the finite bandwidth effects. Continuous-time comparators are used, and their bandwidth is set below the step rate, which smoothes the ramp and reduces the noise. No settling time is needed, as would be the case for clocked comparators, but the low bandwidth enhances the distortion of the non-linear portion. This is corrected by use of a return lookup table, which differs from the one used to generate the ramp. The return lookup table is obtained by calibrating against a stepped precision DC reference. This results in a residual non-linearity well below the quantization noise. This method can also compensate for differential non-linearity (DNL) in the DAC used to generate the ramp. The use of a ramp with a combination of linear and quadratic portions for a single-slope ADC is novel. The number of steps is minimized by keeping the step size just below the photon shot noise. This in turn maximizes the speed of the conversion. High resolution is maintained by keeping small quantization steps at low signals, and noise is minimized by allowing the lowest analog bandwidth, all without increasing the quantization noise. A calibrated return lookup table allows the system to maintain excellent linearity.

Wrigley, Chris J.↗
NASA NTRSDate not supplied

Alternating Direct Current (ADC) - A New Form of Efficient Energy Transmission for Renewable Sources

The prevailing means of electricity transmission through Direct Current (DC) and Alternating Current (AC) have limitations with the ongoing transition to renewable energy sources. In this paper, we discuss a new form of energy transmission, known as alternating direct current (ADC) that would provide significant savings in energy consumption and simultaneously allow efficient utilization of generated energy from renewable sources. This has become possible due to substantial advances in electronics and optoelectronics technologies since the days of Nicholas Tesla and Thomas Edison. Recent efforts of implementing the proposed ADC technology in relevant environments have demonstrated significant energy savings and opened a new paradigm that has the potential to provide an efficient and cost-effective pathway for transition to renewable energy sources even with the existing grid infrastructure. The DC power utilization initiated by Thomas Edison can be stored in battery arrangement but suffers from line loss and hence is not efficient for long-distance transmission. However, AC power developed by Nicholas Tesla cannot be stored efficiently but can be transmitted over long distances due to significantly lower line losses. Currently, AC power is the global foundational energy transmission methodology used because of events that took place over 135 years ago involving Edison, Tesla, and Westinghouse, and since AC power can transmit long distances from power plants to end users efficiently and economically. Approximately 50 years ago, the introduction of semiconductors in commercialized electronic devices and products changed the way people consume electricity. Also, over the years, the expanding adaptation of nonlinear loads has adversely affected the grid stability and hence the utility infrastructures worldwide.

AC↗
DOE OSTI2020

A pixel detector ROIC with a 3-bit, 40 Msps synchronous ADC per pixel for HL LHC

The prototype Fermi Compact Muon Solenoid (CMS) Pixel (FCP130), manufactured in a 130 nm process, is a readout integrated circuit (ROIC) designed for the High Luminosity upgrade of the Large Hadron Collider. It employs a synchronous analog to digital converter (ADC) for the front-end design, with signal processing and data conversion within a single bunch crossing of 25 ns. It is therefore capable of accurately detecting hits occurring in consecutive bunch crossings, without off-time registration of events, making it particularly suitable for the inner most layers of the vertex detector. The ROIC consists of a matrix of 48 × 160 pixels, each 100 × 30 μm2 in size. Each pixel contains a charge sensitive preamplifier with self-biasing leakage current compensation, eight auto-zero comparators and a Gray code encoder for a 3-bit flash-type ADC. The total power consumption is approximately 24 μW per pixel. The measured noise at the output of all the hit comparators across the ROIC is < 80 e- with threshold dispersion < 110 e-RMS, which allows an in-time threshold setting of ~ 1000 e-.

43 PARTICLE ACCELERATORS↗
DOE OSTI2023

In-Pixel Readout IC with compact in-pixel ADC for Pixel detectors at HL LHC

The prototype Smart Pixel concept test chip (SP28), designed in a CMOS 28 nm bulk process, is a proof of concept readout integrated circuit (ROIC) designed for a future Phase III High Luminosity upgrade of the Large Hadron Collider. It employs a synchronous analog to digital converter (ADC) for the front-end design, with signal processing and data conversion within a single bunch crossing of 25 ns. It is therefore capable of accurately detecting hits occurring in consecutive bunch crossings, without off-time registration of events and pileup insensitivity, making it particularly suitable for the inner most layers of the vertex detector. The ROIC consists of a matrix of 32 × 16 pixels, each 25 × 25 µm 2 in size. Each pixel contains a charge sensitive preamplifer with leakage current compensation, three auto-zero comparators for a 2-bit fash-type ADC. The total power consumption is approximately 5 µW per pixel. The measured noise at the output of all the hit comparators across the ROIC is < 90 e- with threshold dispersion < 45 e-RMS, which allows an in-time threshold setting of ≈ 475 e-.

Parpillon, Benjamin↗
DOE OSTI2023

A Cryogenic Readout IC with 100 KSPS in-Pixel ADC for Skipper CCD-in-CMOS Sensors

The Skipper CCD-in-CMOS Parallel Read-Out Circuit (SPROCKET) is a mixed-signal front-end design for the readout of Skipper CCD-in-CMOS image sensors. SPROCKET is fabricated in a 65 nm CMOS process and each pixel occupies a 50$\mu$m $\times$ 50$\mu$m footprint. SPROCKET is intended to be heterogeneously integrated with a Skipper-in-CMOS sensor array, such that one readout pixel is connected to a multiplexed array of nine Skipper-in-CMOS pixels to enable massively parallel readout. The front-end includes a variable gain preamplifier, a correlated double sampling circuit, and a 10-bit serial successive approximation register (SAR) ADC. The circuit achieves a sample rate of 100 ksps with 0.48 $\mathrm{e^-_{rms}}$ equivalent noise at the input to the ADC. SPROCKET achieves a maximum dynamic range of 9,000 $e^-$ at the lowest gain setting (or 900 $e^-$ at the lowest noise setting). The circuit operates at 100 Kelvin with a power consumption of 40 $\mu W$ per pixel. A SPROCKET test chip was submitted in September 2022, and test results will be presented at the conference.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗
NASA NTRS2005

Precision ADCS of a spinning spacecraft for the Mars Aeronomy Explorer Mission

This paper discusses a precision attitude and control technique for meeting these requirements utilizing a similar architecture that was adopted for the Laboratory of Atmospheric and Space Physics (LASP) SNOE (Student Nitrous Oxide Explorer) spinning spacecraft; SNOE has been operating with its ADCS architecture in low earth orbit (LEO) for over two years.

Mars Aeronomy Explorer (MAX)↗
NASA NTRS2011

Extension of the ADC Charge-Collection Model to Include Multiple Junctions

The ADC model is a charge-collection model derived for simple p-n junction silicon diodes having a single reverse-biased p-n junction at one end and an ideal substrate contact at the other end. The present paper extends the model to include multiple junctions, and the goal is to estimate how collected charge is shared by the different junctions.

drift-diffusion↗
NASA NTRS2021

Single-Event Effect Test Report Analog Devices LTC1604AIG#90117 ADC

This study is to characterize the destructive single-event latchup (SEL) susceptibility of the LTC1604AIG#90117 (LTC1604) analog/digital converter (ADC). The device was monitored for SEL current events on the power supplies during exposure to a heavy ion beam at Lawrence Berkeley National Laboratory (LBNL) 88-inch Cyclotron. Testing was performed on September 11, 2021.

single-event latchup (SEL)↗
DOE OSTI2023

The COLUTA ADC ASIC and the ATLAS HL-LHC Liquid Argon Front-End Readout

Abstract The upgraded High-Luminosity Large Hadron Collider (HL-LHC) requires a new radiation tolerant ATLAS Liquid Argon (LAr) Calorimeter readout operating at 40 MHz with 16-bit dynamic range. The Front-End Board 2 (FEB2) will provide the front-end readout for the calorimeter, and will interface a series of custom ASICs due to radiation tolerance requirements of the HL-LHC. The COLUTA is a 65 nm CMOS custom 8-channel 15-bit 40 MSPS ADC ASIC developed for this application. This contribution will present performance results of the final prototype of the COLUTA, surpassing specifications at >11.5 ENOB for relevant frequencies, as well as non-linearity and radiation requirements. Preliminary integration results of the front-end readout components will also be described by means of the FEB2 Pre-Prototype, the “Slice Testboard”.

Instruments & Instrumentation↗
DOE OSTI2025

Muon tagging with flash ADC waveform baselines

Here, this manuscript describes an innovative method to tag muons using the baseline information of the Flash ADC (FADC) waveform of PMTs in the JSNS 2 (J-PARC Sterile Neutrino Search at J-PARC Spallation Neutron Source) experiment. The experiment is designed to search for evidence of sterile neutrinos, and a reliable method for muon tagging is an essential component for background rejection because the detector is located above ground, on the 3rd floor of the J-PARC Material and Life Science Experimental Facility (MLF). Cosmogenic muons that stop within the detector volume and produce a Michel electron are a particularly important background that must be rejected for our sterile neutrino search. Utilizing this innovative method, more than 99.8 % of Michel electrons can be rejected even without using information from the detector’s veto region PMTs. This technique can be employed by any experiments which uses a similar detector configuration.

73 NUCLEAR PHYSICS AND RADIATION PHYSICS↗
DOE OSTI2020

ADC Nonlinearity Correction for the Majorana Demonstrator

Imperfections in analog-to-digital conversion cannot be ignored when signal digitization requirements demand both wide dynamic range and high resolution, as is the case for the MAJORANA DEMONSTRATOR 76 Ge neutrinoless double beta decay search. Enabling the experiment's high-resolution spectral analysis and efficient pulse shape discrimination required careful measurement and correction of ADC nonlinearites. Here, a simple measurement protocol was developed that did not require sophisticated equipment or lengthy data taking campaigns. A slope-dependent hysteresis was observed and characterized. A correction applied to digitized waveforms prior to signal processing reduced the differential and integral nonlinearites by an order of magnitude, eliminating these as dominant contributions to the systematic energy uncertainty at the double-beta decay Q value.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗
NASA NTRS1995

Effect Of Clock Mode On Radiation Hardness Of An ADC

Report discusses techniques for testing and evaluating effects of total dosages of ionizing radiation on performances of high-resolution successive-approximation analog-to-digital converters (ADCs), without having to test each individual bit or transition. Reduces cost of testing by reducing tests to few critical parametric measurements, from which one determines approximate radiation failure levels providing good approximations of responses of converters for purpose of total-dose-radiation evaluations.

Lee, Choon I.↗
NASA NTRS2006

Broadband X-ray Spectroscopy of the ADC Source 4U 1822-37 with Suzaku

We will present the broadband spectra of the low mass x-ray binary 4U 1822-37, recently observed with Suzaku. 4U 1822-37 is the canonical accretion disk corona (ADC) source where the compact object is obscured by an extended corona that intercepts and scatters the central continuum emission, some of which is then reprocessed in the outer regions of the accretion disk. 4U 1822-37 therefore serves as an important link between x-ray binaries and AGN. The broadband x-ray spectra from the Suzaku XIS and HXD provide a unique opportunity to probe the physical conditions in the corona and the accretion disk for this important accretion geometry.

Cottam, J.↗
NASA NTRS2015

Minimal Power Latch for Single-Slope ADCs

A latch circuit that uses two interoperating latches. The latch circuit has the beneficial feature that it switches only a single time during a measurement that uses a stair step or ramp function as an input signal in an analog to digital converter. This feature minimizes the amount of power that is consumed in the latch and also minimizes the amount of high frequency noise that is generated by the latch. An application using a plurality of such latch circuits in a parallel decoding ADC for use in an image sensor is given as an example.

Hancock, Bruce R.↗
DOE OSTI2023

Chip Development Toward 12 bit 10 GSPS Cryogenic ADC for Multiplexed Quantum Readout

This presentation presents the background and plan for the development toward a 12 bit 10 GSPS cryogenic ADC for multiplexed quantum readout. It covers the first two chips that have been taped out and tested. It includes results for those chips and provides some context to plans for the upcoming chip tapeout and the final one to come later.

72 PHYSICS OF ELEMENTARY PARTICLES AND FIELDS↗
DOE OSTI2023

Physical Layer Security at a Point-to-Point MIMO System With 1-Bit DACs and ADCs

Low-resolution converters reduce the power consumption of wireless devices and help enable large energy-efficient arrays. In this letter, we evaluate the secrecy rate for the extreme case of 1-bit single-user multiple-input multiple-output systems following two signaling approaches. In the first method, the system uses discrete signaling. In the second, the system combines Gaussian signaling with artificial noise alongside power allocation. In the first case, we give a closed-form expression of the secrecy rate and propose an algorithm that provides near-optimal results for low signal-to-noise ratios (SNRs). Further, in the second scenario, depending on the channel state information, we suggest different precoding plans and derive a secrecy rate lower bound. At low SNR, power is allocated to the main signal. Only at high SNR is optimal power allocation effective. Moreover, knowing the eavesdropper channel greatly improves the system’s secrecy.

1-bit digital-to-analog (DAC) and analog-to-digita↗