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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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All sourcesNASA NTRSDOE OSTI
NASA NTRS2000

NASA Information Technology Implementation Plan

NASA's Information Technology (IT) resources and IT support continue to be a growing and integral part of all NASA missions. Furthermore, the growing IT support requirements are becoming more complex and diverse. The following are a few examples of the growing complexity and diversity of NASA's IT environment. NASA is conducting basic IT research in the Intelligent Synthesis Environment (ISE) and Intelligent Systems (IS) Initiatives. IT security, infrastructure protection, and privacy of data are requiring more and more management attention and an increasing share of the NASA IT budget. Outsourcing of IT support is becoming a key element of NASA's IT strategy as exemplified by Outsourcing Desktop Initiative for NASA (ODIN) and the outsourcing of NASA Integrated Services Network (NISN) support. Finally, technology refresh is helping to provide improved support at lower cost. Recently the NASA Automated Data Processing (ADP) Consolidation Center (NACC) upgraded its bipolar technology computer systems with Complementary Metal Oxide Semiconductor (CMOS) technology systems. This NACC upgrade substantially reduced the hardware maintenance and software licensing costs, significantly increased system speed and capacity, and reduced customer processing costs by 11 percent.

Source record↗
NASA NTRS1994

Ultra Low Power Imaging Systems Using CMOS Image Sensor Technology

The need for miniaturization in advanced science sensor systems has led to the development of a new image sensor technology, the active pixel image sensor (APS). The development of CMOS APS technology allows the integration of timing and control electronics, imaging detector arrays, signal chains and analog-to-digital conversion on a single integrated circuit. The impact on the imaging system is to reduce power by approximately 1000x over existing systems - from tens of watts to tens of milliwatts.

imaging↗
NASA NTRS1977

Annual Conference on Nuclear and Space Radiation Effects, 14th, College of William and Mary, Williamsburg, Va., July 12-15, 1977, Proceedings

Topics related to processing and hardness assurance are considered, taking into account the radiation hardening of CMOS technologies, technological advances in the manufacture of radiation-hardened CMOS integrated circuits, CMOS hardness assurance through process controls and optimized design procedures, the application of operational amplifiers to hardened systems, a hard off-the-shelf SG1524 pulse width modulator, and the gamma-induced voltage breakdown anomaly in a Schottky diode. Basic mechanisms are examined, giving attention to chemical and structural aspects of the irradiation behavior of SiO2 films on silicon, experimental observations of the chemistry of the SiO2/Si interface, leakage current phenomena in irradiated SOS devices, the avalanche injection of holes into SiO2, the low-temperature radiation response of Al2O3 gate insulators, and neutron damage mechanisms in silicon at 10 K. Other subjects discussed are related to radiation effects in devices and circuits, space radiation effects, and aspects of simulation, energy deposition, and dosimetry.

Stahl, R. H.↗
NASA NTRS2006

Product Reliability Trends, Derating Considerations and Failure Mechanisms with Scaled CMOS

As microelectronics is scaled into the deep sub-micron regime, space and aerospace users of advanced technology CMOS are reassessing how scaling effects impact long-term product reliability. The effects of electromigration (EM), time-dependent-dielectric-breakdown (TDDB) and hot carrier degradation (HCI and NBTI) wearout mechanisms on scaled technologies and product reliability are investigated, accelerated stress testing across several technology nodes is performed, and FA is conducted to confirm the failure mechanism(s).

CMOS integrated circuits↗
NASA NTRS1995

Active-Pixel Image Sensor With Analog-To-Digital Converters

Proposed single-chip integrated-circuit image sensor contains 128 x 128 array of active pixel sensors at 50-micrometer pitch. Output terminals of all pixels in each given column connected to analog-to-digital (A/D) converter located at bottom of column. Pixels scanned in semiparallel fashion, one row at time; during time allocated to scanning row, outputs of all active pixel sensors in row fed to respective A/D converters. Design of chip based on complementary metal oxide semiconductor (CMOS) technology, and individual circuit elements fabricated according to 2-micrometer CMOS design rules. Active pixel sensors designed to operate at video rate of 30 frames/second, even at low light levels. A/D scheme based on first-order Sigma-Delta modulation.

Fossum, Eric R.↗
NASA NTRS1982

On testing stuck-open faults in CMOS combinational circuits

Recently it has been found that a class of failure related to a particular technology (CMOS) cannot be modelled as the conventional stuck-at fault model. These failures change the combinational behavior of CMOS logic gates into a sequential one. Such a failure is modelled as a fault, called the Stuck-Open fault (SOP). The object of this paper is to develop a procedure to detect single SOPs in combinational circuits. It is shown, that in general, tests generated for stuck-at faults when applied in a particular sequence will detect all single SOP faults. In case of single redundancy in the network, the SOP fault on the redundant line cannot be detected. When there is reconvergent fan-out in the network, there is a one-one correspondence between the conditions for stuck-at fault and stuck-open fault detectability.

Chandramouli, R.↗
NASA NTRS2008

Radiation Testing, Characterization and Qualification Challenges for Modern Microelectronics and Photonics Devices and Technologies

At an earlier conference we discussed a selection of the challenges for radiation testing of modern semiconductor devices focusing on state-of-the-art CMOS technologies. In this presentation, we extend this discussion focusing on the following areas: (1) Device packaging, (2) Evolving physical single even upset mechanisms, (3) Device complexity, and (4) the goal of understanding the limitations and interpretation of radiation testing results.

LaBel, Kenneth A.↗
NASA NTRS2005

Impact of Device Scaling on Deep Sub-micron Transistor Reliability: A Study of Reliability Trends using SRAM

As microelectronics are scaled in to the deep sub-micron regime, users of advanced technology CMOS, particularly in high-reliability applications, should reassess how scaling effects impact long-term reliability. An experimental based reliability study of industrial grade SRAMs, consisting of three different technology nodes, is proposed to substantiate current acceleration models for temperature and voltage life-stress relationships. This reliability study utilizes step-stress techniques to evaluate memory technologies (0.25mum, 0.15mum, and 0.13mum) embedded in many of today's high-reliability space/aerospace applications. Two acceleration modeling approaches are presented to relate experimental FIT calculations to Mfr's qualification data.

CMOS integrated circuits↗
NASA NTRS2011

Users Guide on Scaled CMOS Reliability: NASA Electronic Parts and Packaging (NEPP) Program Office of Safety and Mission Assurance

Reliability of advanced CMOS technology is a complex problem that is usually addressed from the standpoint of specific failure mechanisms rather than overall reliability of a finished microcircuit. A detailed treatment of CMOS reliability in scaled devices can be found in Ref. 1; it should be consulted for a more thorough discussion. The present document provides a more concise treatment of the scaled CMOS reliability problem, emphasizing differences in the recommended approach for these advanced devices compared to that of less aggressively scaled devices. It includes specific recommendations that can be used by flight projects that use advanced CMOS. The primary emphasis is on conventional memories, microprocessors, and related devices.

Scaled CMOS↗
NASA NTRS2001

Radiation Response of Emerging FeRAM Technology

The test results of measurements performed on two different sizes of ferroelectric random access memory (FeRAM) suggest the degradation is due to the low radiation tolerance of sense amplifiers and reference voltage generators which are based on commercial complementary metal oxide semiconductor (CMOS) technology. This paper presents total ionizing dose (TID) testing of 64Kb Ramtron FM1608 and 256Kb Ramtron FM1808.

Nguyen, D. N.↗
NASA NTRS2000

A Single-Chip Programmable Digital CMOS Imager with Enhanced Low Light Detection Capability

Low-power, low-cost, miniature and integrated digital imaging systems are expected to be widely used in consumer electronics in the near future. While CMOS technology has been responsible for the phenomenal growth in consumer electronics, micro-porcessors, memory, audio systems, and radio-frequency circuits (e.g. cellular phones), till recently, the video technology remained outside this mainstream.

digital↗
NASA NTRS2000

Development of Individually Addressable Micro-Mirror-Arrays for Space Applications

We have been developing a 32 x 32 prototype array of individually addressable Micro-Mirrors capable of operating at cryogenic temperature for Earth and Space Science applications. Micro-Mirror-Array technology has the potential to revolutionize imaging and spectroscopy systems for NASA's missions of the 21st century. They can be used as programmable slits for the Next Generation Space Telescope, as smart sensors for a steerable spectrometer, as neutral density filters for bright scene attenuation etc. The, entire fabrication process is carried out in the Detector Development Laboratory at NASA, GSFC. The fabrication process is low temperature compatible and involves integration of conventional CMOS technology and surface micro-machining used in MEMS. Aluminum is used as the mirror material and is built on a silicon substrate containing the CMOS address circuit. The mirrors are 100 microns x l00 microns in area and deflect by +/- 10 deg induced by electrostatic actuation between two parallel plate capacitors. A pair of thin aluminum torsion straps allow the mirrors to tilt. Finite-element-analysis and closed form solutions using electrostatic and mechanical torque for mirror operation were developed and the results were compared with laboratory performance. The results agree well both at room temperature and at cryogenic temperature. The development demonstrates the first cryogenic operation of two-dimensional Micro-Mirrors with bi-state operation. Larger arrays will be developed meeting requirements for different science applications. Theoretical analysis, fabrication process, laboratory test results and different science applications will be described in detail.

Dutta, Sanghamitra B.↗
NASA NTRS1987

High data rate Reed-Solomon encoding and decoding using VLSI technology

Presented as an implementation of a Reed-Solomon encode and decoder, which is 16-symbol error correcting, each symbol is 8 bits. This Reed-Solomon (RS) code is an efficient error correcting code that the National Aeronautics and Space Administration (NASA) will use in future space communications missions. A Very Large Scale Integration (VLSI) implementation of the encoder and decoder accepts data rates up 80 Mbps. A total of seven chips are needed for the decoder (four of the seven decoding chips are customized using 3-micron Complementary Metal Oxide Semiconduction (CMOS) technology) and one chip is required for the encoder. The decoder operates with the symbol clock being the system clock for the chip set. Approximately 1.65 billion Galois Field (GF) operations per second are achieved with the decoder chip set and 640 MOPS are achieved with the encoder chip.

Miller, Warner↗
NASA NTRS1986

Electronic timer for sounding rocket payload use

An electronic timer has been developed for sounding rocket use. The timer uses CMOS technology for low power consumption and has a battery back-up to keep the timing circuit active in case of a dropout on the payload power bus. Time-event decoding is done by programming EPROM's which enable a +28 volt dc sourcing output. There are 32 discrete outputs which can provide +28 volt dc into a minimum load impedance of 150 ohms. Inputs are designed to operate on standard CMOS voltage levels, but they can withstand +28 volts dc without damage. The timer can be started by either 'G' or lift-off switch closure or umbilical release at lift-off.

Williams, C. P.↗