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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 37 records · Page 2
All sourcesNASA NTRSDOE OSTI
DOE OSTI2020

High broadband photoconductivity of few-layered MoS 2 field-effect transistors measured using multi-terminal methods: effects of contact resistance

Among the layered two dimensional semiconductors, molybdenum disulfide (MoS 2 ) is considered to be an excellent candidate for applications in optoelectronics and integrated circuits due to its layer-dependent tunable bandgap in the visible region, high ON/OFF current ratio in field-effect transistors (FET) and strong light–matter interaction properties. In this study, using multi-terminal measurements, we report high broadband photocurrent response ( R ) and external quantum efficiency (EQE) of few-atomic layered MoS 2 phototransistors fabricated on a SiO 2 dielectric substrate and encapsulated with a thin transparent polymer film of Cytop. The photocurrent response was measured using a white light source as well as a monochromatic light of wavelength λ = 400 nm–900 nm. We measured responsivity using a 2-terminal configuration as high as R = 1 × 10 3 A W -1 under white light illumination with an optical power P opt = 0.02 nW. The R value increased to 3.5 × 10 3 A W -1 when measured using a 4-terminal configuration. Using monochromatic light on the same device, the measured values of R were 10 3 and 6 × 10 3 A W -1 under illumination of λ = 400 nm when measured using 2- and 4-terminal methods, respectively. The highest EQE values obtained using λ = 400 nm were 10 5 % and 10 6 % measured using 2- and 4-terminal configurations, respectively. The wavelength dependent responsivity decreased from 400 nm to the near-IR region at 900 nm. The observed photoresponse, photocurrent–dark current ratio (PDCR), detectivity as a function of applied gate voltage, optical power, contact resistances and wavelength were measured and are discussed in detail. The observed responsivity is also thoroughly studied as a function of contact resistance of the device.

36 MATERIALS SCIENCE↗
DOE OSTI2022

Review of Thermal Contact Resistance of Flexible Graphite Materials for Thermal Interfaces in High Heat Flux Applications

In this report the data is reviewed on thermal contact conductance (TCC) and/or thermal contact resistance (TCR) at material interfaces which employs flexible graphite (FG) materials as thermal interface materials (TIM). FG materials are often used as TIM due to their conforming nature. While the overall TCR can be estimated straightforward from measured data, the interface TCR is much more difficult to obtain. The report also discusses the interfacial thermal contact conductance between FG-tungsten and FG-Glidcop-Al15, which are envisioned for high-heat flux applications.

36 MATERIALS SCIENCE↗
DOE OSTI2023

Temperature-Dependent Sheet and Contact Resistivity Measurements on Ag and Ag-Ni Circuit Pastes

The metal circuits and brazes used in electronic, energy conversion, and/or energy storage devices often have difficulty wetting and adhering to ceramic and/or ceramic-passivated metal substrates. Here, a novel Particle Interlayer Directed Wetting and Spreading (PIDWAS) technique is demonstrated that utilizes screen printing, the low wetting angle of silver on nickel, and the high work of adhesion between nickel and various ceramics to produce well-adhered, self-assembled silver patterns on ceramic and/or stainless-steel substrates not normally wet by silver. The resulting Ag-Ni circuits have higher sapphire adhesion strengths (up to 30 MPa on sapphire), higher densities (>97% on sapphire), and similar high-temperature electronic resistivities to those made using commercially-available Heraeus C8710 or DAD-87 silver circuit pastes. Similarly, Ag-Ni brazes between a variety of ceramic and/or stainless-steel substrates have better microstructural stability with rapid thermal cycling, reduction-oxidation cycling, and dual atmosphere isothermal aging than conventional Ag-CuO brazes. In addition, the residual Ni in these Ag-Ni circuits and brazes can be used to chemically getter surface segregated Al, ensuring low contact resistances on a variety of chromia- and/or alumina-passivated stainless steels. Reference: [1] Hu G, Zhou Q, Bhatlawande A, Park J, Termuhlen R, Ma Y, Bieler TR, Yu HC, Qi Y, Hogan T & Nicholas JD. Patterned Nickel Interlayers for Enhanced Silver Wetting, Spreading and Adhesion on Ceramic Substrates. Scripta Materialia, 2021; 196, 113767. 10.1016/j.scriptamat.2021.113767 [2] Park J, Phongpreecha T, Nicholas JD & Qi Y. Enhanced Liquid Metal Wetting on Oxide Surfaces via Patterned Particles. Acta Materialia, 2020; 199, 551-560. 10.1016/j.actamat.2020.08.037

Bhatlawande, Aishwarya↗
DOE OSTI2026

Patterned, Low-Temperature Growth of Transition Metal Dichalcogenides for Low Resistance Raised Contacts

Transition metal dichalcogenide (TMD) monolayers are promising channel materials for next-generation electronic devices. A challenge is the high contact resistance between monolayer TMDs and metal contacts, especially for holes. Here, in this regard, raised source/drain contacts are promising. However, the direct, patterned growth of raised contacts at CMOS-compatible temperatures remains largely unresolved. We present plasma-free selenization and sulfurization of metal oxides at substrate temperatures down to 400 °C, compatible with back-end-of-line thermal budgets. To achieve growth at such temperatures, gas-phase chalcogen precursors are first thermally activated at 950 °C. Films grown on single-crystal monolayer TMDs exhibit high crystal quality, as confirmed by transmission electron microscopy. Raised contacts on WSe 2 monolayers fabricated using this approach yield a low hole contact resistance of 0.3 kΩ·μm after chemical doping. This process is shown to be applicable to growing various TMDs, including WS 2 , MoSe 2 , MoS 2 , PtSe 2 , and NbS 2 .

contact engineering↗
DOE OSTI2024

Silicon implantation and annealing in β -Ga 2 O 3 : Role of ambient, temperature, and time

Optimizing thermal anneals of Si-implanted β-Ga 2 O 3 is critical for low resistance contacts and selective area doping. Here we report the impact of annealing ambient, temperature, and time on the activation of room temperature ion-implanted Si in β-Ga 2 O 3 at concentrations from 5 × 10 18 to 1 × 10 20 cm −3 , demonstrating full activation (>80% activation, mobilities >70 cm 2 /V s) with contact resistances below 0.29 Ω mm. Homoepitaxial β-Ga 2 O 3 films, grown by plasma-assisted molecular beam epitaxy on Fe-doped (010) substrates, were implanted at multiple energies to yield 100 nm box profiles of 5 × 10 18 , 5 × 10 19, and 1 × 10 20 cm −3 . Anneals were performed in an ultra-high vacuum-compatible quartz furnace at 1 bar with well-controlled gas compositions. To maintain β-Ga 2 O 3 stability, p O2 must be greater than 10 −9 bar. Anneals up to p O2 = 1 bar achieve full activation at 5 × 10 18 cm −3, while 5 × 10 19 cm −3 must be annealed with p O2 ≤ 10 −4 bar, and 1 × 10 20 cm −3 requires p O2 < 10 −6 bar. Water vapor prevents activation and must be maintained below 10 −8 bar. Activation is achieved for anneal temperatures as low as 850 °C with mobility increasing with anneal temperatures up to 1050 °C, though Si diffusion has been reported above 950 °C. At 950 °C, activation is maximized between 5 and 20 min with longer times resulting in decreased carrier activation (over-annealing). This over-annealing is significant for concentrations above 5 × 10 19 cm −3 and occurs rapidly at 1 × 10 20 cm −3 . Rutherford backscattering spectrometry (channeling) suggests that damage recovery is seeded from remnant aligned β-Ga 2 O 3 that remains after implantation; this conclusion is also supported by scanning transmission electron microscopy showing retention of the β-phase with inclusions that resemble the γ-phase.

71 CLASSICAL AND QUANTUM MECHANICS, GENERAL PHYSIC↗
DOE OSTI2022

Characterization of Engineered Pinholes in Dielectric Stacks of High-Performance Poly-Silicon Passivating Contacts

Passivating contact structures are expected to be implemented in > 50 % of industrially manufactured silicon photovoltaics produced over the next decade. One type of passivating contact utilizes a c-Si/dielectric/doped poly-Si layer stack. In cases where the dielectric layer/s are thick enough to impede tunneling of charge carriers, it was shown that disruptions (pinholes) in the dielectric are required to facilitate transport.[1] Pinholes in SiOx layers have typically been formed via high temperature annealing that allows localized breakup of this layer. This approach has drawbacks; 1) high temperature annealing increases cost and 2) pinhole formation is sensitive to both the SiOx thickness and wafer surface morphology making control of density and dimensions difficult. Recently, an alternative method of pinhole formation relying on metal assisted chemical etching (MACE) was shown to allow control over pinhole areal densities.[2] Such control is critical as both the density and dimensions of the pinholes determine saturation current density and contact resistivity. The contacts formed with the MACE process are known as polysilicon on locally etched oxide or PLEO and also result in low saturation current densities and low contact resistivity due to SiOx passivation and engineered pinhole enabled charge carrier transport, respectively. Photovoltaic devices with efficiencies greater than 20 % have recently been produced with these contacts, demonstrating the viability of contacts with engineered pinholes. Experimentally, preferential local collection of excess charge carriers has been observed and definitively connected to thermally induced pinholes in thick SiOx layers within c-Si/SiOx/poly-Si contact structures.[3] Recent work has shown that enhanced local collection of excess carriers can result from enhanced diffusion of dopants through pinholes in SiOx layers.[4] This study was restricted to simulation and characterization of poly-Si with the same dopant type as the c-Si substrates. In this work we focus our analysis on boron doped poly-Si with different stacks of dielectric layers (PLEO and PLENO where the N refers to a SiNy layer on top of the SiOx) on n-type crystalline silicon. This provides insight into how engineered pinholes affect charge collection across the p-n junction. Like previous observations of locally enhanced carrier transport through thermally induced pinholes, the EBIC images in Figure 1 shows that engineered pinholes in PLENO (1a) and PLEO (1b) also exhibit locally enhanced carrier transport at pinhole locations (bright spots in the images). We will also present detailed correlative nanoscale structural and chemical analysis using TEM imaging and EELS analysis with sample preparation guided by EBIC imaging. This allows us to connect the density and dimensions of engineered pinholes with charge carrier transport and measured photovoltaic device parameters. Our findings will accelerate the adoption of PLEO and PLENO contacts in industrially manufactured photovoltaic devices.

EBIC↗
DOE OSTI2026

Low resistance p-type contacts to monolayer WSe2 through chlorinated solvent doping

Tungsten diselenide (WSe 2 ) is a promising p-type semiconductor limited by high contact resistance (R C ) and the lack of a reliable doping strategy. Here, we demonstrate that exposing WSe 2 to chloroform provides simple and stable p-type doping. In monolayer WSe 2 transistors with Pd contacts, chloroform increases the maximum hole current by over 100× (>200 µA/µm), reduces R C to ~ 2.5 kΩ·μm, and retains an on/off ratio of 10 10 at room temperature. These improvements persist for over 8 months, survive a 150 °C thermal anneal, and remain effective down to 10 K, enabling a cryogenic R C of ~ 1 kΩ·μm. Density functional theory indicates that chloroform strongly physisorbs to WSe 2 , inducing hole doping with minimal impact on the electronic states between the valence band and conduction band edges. Auger electron spectroscopy and atomic force microscopy suggest that chloroform intercalates at the WSe 2 interface with the gate oxide, contributing to doping stability and mitigating interfacial dielectric disorder, though further studies are needed to conclusively confirm this mechanism. This robust, scalable approach enables high-yield WSe 2 transistors with good p-type performance.

42 ENGINEERING↗
DOE OSTI2026

Optimizing Porous Transport Layer Porosity for Proton Exchange Membrane Water Electrolysis

An empirical model is presented that describes anode-side losses related to porous transport layer (PTL) morphology in proton exchange membrane water electrolysis (PEMWE). The model is based on an advanced voltage breakdown analysis that links various overpotentials to PTL morphology. Custom Ti PTLs, spanning uncommonly low porosities (22 - 31%), were fabricated and analyzed with X-ray CT to obtain pore and particle size distributions. Particle size distributions were consistent across samples with an average particle diameter of 12.0?..mu..m, whereas average pore diameters ranged from 6.0 to 7.0?..mu..m. The PTLs were tested in standard PEMWE cell assemblies with anode catalyst loadings of 0.1 mgIr cm-2 to obtain polarization curves, electrochemical impedance spectra, and augmented Tafel analysis. The PTL-dependent anode side losses were deconvoluted and assigned to excess utilization, concentration, ion transport resistance, and electrical contact resistance overpotentials. The data and model reveal an optimal 20 - 28% PTL porosity region where utilization and contact resistance overpotentials are minimized without triggering concentration and ion transport losses related to water deprivation. The optimal PTL porosity depends on the operating current density and is demonstrated at realistic PEMWE water flow rates to establish PTL design guidance for operation at scale.

08 HYDROGEN↗