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Digital subsystem design and development employing n-channel and p-channel in MOS FET units in complimentary circuits in integrated circuit array
Application of NASAP to design of circuits and extension of NASAP routines to large scale circuits
A nonlinear circuit model for avalanche diodes is proposed. The model was derived by assuming that the bias dependence of the elements in a known small-signal equivalent-circuit model for existing diodes arises in a manner consistent with the theory of an idealized Read-type device. The model contains a nonlinear R-L branch, a controlled source, and a linear depletion capacitance. The model is used in the nearly linear sense to predict intermodulation distortion and gain compression in avalanche diode amplifiers. Computed results for amplifiers with existing diodes are shown to be in good agreement with experiment.
Excellent radiation resistance of indium phosphide solar cells makes them a promising candidate for space power applications, but the present high cost of starting substrates may inhibit their large scale use. Thin film indium phosphide cells grown on Si or GaAs substrates have exhibited low efficiencies, because of the generation and propagation of large number of dislocations. Dislocation densities were calculated and its influence on the open circuit voltage, short circuit current, and efficiency of heteroepitaxial indium phosphide cells was studied using the PC-1D. Dislocations act as predominant recombination centers and are required to be controlled by proper transition layers and improved growth techniques. It is shown that heteroepitaxial grown cells could achieve efficiencies in excess of 18 percent AMO by controlling the number of dislocations. The effect of emitter thickness and surface recombination velocity on the cell performance parameters vs. dislocation density is also studied.
Electrical designers of Orbiter payloads face the challenge of determining proper circuit protection/wire size parameters to satisfy Orbiter engineering and safety requirements. This document is the result of a program undertaken to review test data from all available aerospace sources and perform additional testing to eliminate extrapolation errors. The resulting compilation of data was used to develop guidelines for the selection of wire sizes and circuit protection ratings. The purpose is to provide guidance to the engineering to ensure a design which meets Orbiter standards and which should be applicable to any aerospace design.
A flexible, fabric-based circuit comprises a non-conductive flexible layer of fabric and a conductive flexible layer of fabric adjacent thereto. A non-conductive thread, an adhesive, and/or other means may be used for attaching the conductive layer to the non-conductive layer. In some embodiments, the layers are attached by a computer-driven embroidery machine at pre-determined portions or locations in accordance with a pre-determined attachment layout before automated cutting. In some other embodiments, an automated milling machine or a computer-driven laser using a pre-designed circuit trace as a template cuts the conductive layer so as to separate an undesired portion of the conductive layer from a desired portion of the conductive layer. Additional layers of conductive fabric may be attached in some embodiments to form a multi-layer construct.
We implemented the ADAPT-VQE algorithm into our recent classical sparse wavefunction circuit simulator to demonstrate that classical resources can (1) efficiently find a physically motivated compact wavefunction ansatz for further refinement on near-term quantum hardware and (2) benchmark expected results of VQE-based algorithms once the quantum hardware is available to study large-scale applications. In particular, we study the role of the ADAPT-VQE operator pool, molecular basis set selection, and variations such as TETRIS-ADAPT-VQE on the performance of our classical circuit simulator. This work demonstrates the promise of using classical resources to generate highly accurate wavefunctions that can be prepared on quantum hardware to initiate other quantum algorithms such as phase estimation. Our approach harnesses the power of high-performance computing resources with the more limited available quantum computers to map a path toward quantum advantage for electronic structure calculations in chemistry and materials science.
Controllable threshold circuit using interconnection simple toroids for all-magnetic logic to select signal paths
The open circuit voltage (V OC) is a critical and common indicator of solar cell performance as well as degradation, for panel down to lab-scale photovoltaics. Detecting V OC at the nanoscale is much more challenging, however, due to experimental limitations on spatial resolution, voltage resolution, and/or measurement times. Accordingly, in this work an approach based on Conductive Atomic Force Microscopy is implemented to directly detect the local V OC , notably for monocrystalline Passivated Emitter Rear Contact (PERC) cells which are the most common industrial-scale solar panel technology in production worldwide. This is demonstrated with cross-sectioned monocrystalline PERC cells around the entire circumference of a poly-Aluminum-Silicide via through the rear emitter. The V OC maps reveal a local Back Surface Field extending ~2 μm into the underlying p-type Si absorber due to Al in-diffusion as designed. Such high spatial resolution methods for photovoltaic performance mapping are especially promising for directly visualizing the effects of processing parameters, as well as identifying signatures of degradation for silicon and other solar cell technologies.
We dope CdTe solar cells with Bi after the device structure is completed using a solution process.
Small magnetic sweep deflection circuits operate a hand-held lunar television camera. They convert timing signals from the synchronizer into waveforms that provide a raster on the vidicon target. Raster size remains constant and linear during wide voltage and temperature fluctuations.
Analysis and synthesis of distributed transmission line networks with open or short circuited shunts or series stubs, describing composite transfer matrices
Electro-mechanical circuit for converting floating intelligence signal to common electrically grounded intelligence recorder
Circuit limits lamp current, replacing the series current-limiting resistor.
Solder coating process for printed copper circuit protection
The purpose of the short-circuit voltage transducer is to provide engineering data to aid the evaluation of array performance during flight. The design, fabrication, calibration, and in-flight performance of the transducers onboard the Mariner 6, 7 and 9 spacecrafts are described. No significant differences were observed in the in-flight electrical performance of the three transducers. The transducers did experience significant losses due to coverslides or adhesive darkening, increased surface reflection, or spectral shifts within coverslide assembly. Mariner 6, 7 and 9 transducers showed non-cell current degradations of 3-1/2%, 3%, and 4%, respectively at Mars encounter and 6%, 3%, and 4-12%, respectively at end of mission. Mariner 9 solar Array Test 2 showed 3-12% current degradation while the transducer showed 4-12% degradation.
Here, the 7400 line of transistor to transistor logic (TTL) devices is emphasized almost exclusively where hardware is concerned. However, it should be noted that the logic theory contained herein applies to all hardware. Discussed here are synchronous binary UP counters, synchronous DOWN and UP/DOWN counters, integrated circuit counters, shift registers, sequential techniques, and designing sequential counting machines.
A printed circuit board (PCB) structure and mounting assembly for joining two PCBs. A first PCB has a top and bottom surface faces and a peripheral end face separating the top and bottom surface. The first PCB has one or more conductive wire ends exposed at a surface of the peripheral end face; the exposed conductive wire ends forming multiple separate electrical contacts across the thickness and length of the PEF surface. A second PCB has a top surface face and one or more conductive pads exposed at the top surface at locations corresponding to locations of the multiple electrical contacts. A surface mount solder material is disposed on one or more exposed conductive pads for electrically connecting with corresponding the multiple electrical contacts. The disposed solder material stably joins the PEF surface of the first PCB to the top surface of the second PCB in a relative perpendicular orientation.