A Cold ASIC for Streaming Readout of Segmented Detectors
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Zhankevich, Aliaksandr↗
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Strip-based Scintillation Detector for Dual-readout High-granularity Calorimetry
New calorimeter technology is being developed for future collider experiments. We are developing a calorimeter that integrates two technologies, a high-granularity calorimeter and a dual-readout calorimeter, and has high time resolution at a picosecond level. The proposed calorimeter is a sampling calorimeter based on scintillation and Cherenkov detectors with high-granularity readout. The Cherenkov detector has a picosecond level time resolution. For the high-granularity scintillation detector, scintillator strips of 300mm × 30mm ×3mm-thick are aligned horizontally and vertically to realize an effective 30mm-square-cell segmentation. Prototype strips with different designs and scintillator materials were tested to compare the performance.
46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗
GRAPH — an readout ASIC for large MCP based detectors
We present a programmable 16 channel, mixed signal, low power readout ASIC, having the project historically named Gigasample Recorder of Analog waveforms from a PHotodetector (GRAPH). It is designed to read large aperture single photon imaging detectors using micro channel plates for charge multiplication, and measuring the detector's response on crossed strips anodes to extrapolate the incoming photon position. Each channel consists of a fast, low power and low noise charge sensitive amplifier, which provides a myriad of coarse and fine programmable options for gain and shaping settings. Further, the amplified signal is recorded using, to our knowledge novel, the Hybrid Universal sampLing Architecture (HULA) ADC. A kind of mixed signal double buffer memory, that enables concurrent waveform recording, and selected event digitized data extraction. The sampling frequency is freely adjustable between few kHz up to 125 MHz, while the chip's internal digital memory holds a history 2048 samples for each channel, with a digital headroom of 12 bits. An optimized region of interest sample-read algorithm allows to extract the information just around the event pulse peak, while selecting the next event, thus substantially reducing the operational dead time. The chip is designed in 130 nm TSMC CMOS technology, and its power consumption is around 47 mW per channel.
47 OTHER INSTRUMENTATION↗
Anode sensitivity calibration of photomultiplier tubes used as a readout of the ELOSS detector
We present and discuss the methodology and results for an anode sensitivity calibration of Photomultiplier Tubes (PMTs) that serve as the optical readout of the Energy Loss Optical Scintillation System (ELOSS). The ELOSS detector, under development at the Facility for Rare Isotope Beams (FRIB), is a gaseous Xe scintillation-based detector designed to identify the atomic number (Z) of nuclear reaction fragments by energy-loss measurement. Variation in the anode sensitivity from tube to tube of commercially available PMTs limits ELOSS from reaching its ultimate Z resolution. A methodical approach to calibrating PMT anode sensitivities to a single target value by systematic PMT gain corrections is presented. Although the calibration process is discussed in terms of its impact on ELOSS performance, the presented method is applicable to any optical detector system composed of a large number of PMTs needing anode sensitivity calibration.
Instrumentation for heavy-ion accelerators↗
Commissioning of an MPGD-based Drift Chamber for Heavy-ion Tracking in FRIB's Sweeper magnet system
A newly developed drift chamber equipped with an innovative hybrid Micro-Pattern Gaseous Detector based readout was commissioned at FRIB. The detector consists of a Multi-layer Thick Gas Electron Multiplier (M-THGEM) mounted over a high-granularity, position-sensitive readout board. Denoted as the Micro-Pattern Drift Chamber (MPDC), the new device is used to provide tracking capability as part of the detectors of the Sweeper magnet system for neutron-invariant-mass spectrometry at the Facility for Rare Isotope Beams (FRIB). The localization of impinging ions in a 30 × 30 cm 2 drift area is derived by processing the charge-avalanche distribution induced on the segmented readout board. The signals induced on the readout pads are processed by a compact, multi-channel Data Acquisition System (DAQ) based on the Scalable Readout System (SRS). To facilitate synchronization with other detector systems of the Sweeper magnet system, the SRS has been configured to accept an external trigger.
Gaseous detectors↗
Performance of an X-γ ray detection system based on a thick silicon LGAD
We present the performance of a X-γ ray detection systems based on a 300 µm thick silicon low-gain avalanche diode (LGAD) and of an equivalent Diode structure without the gain layer, read-out by a custom-made low-noise charge amplifier. For the LGAD structure, the multiplication gains M s from 10.2 to 19.3 are measured, and the Equivalent Noise Charge (ENC) components have been studied in detail. As expected, a significant reduction of the white and 1/f voltage series and dielectric ENC components is observed with increasing gain, shortening the optimum peaking time to τ = 0.4÷8 μs depending on the gain value, with respect to the standard diode, while the parallel ENC component increases proportionally to the gain up to M s = 15. Setting the gain M s = 12.7, a minimum ENC = 34.5 electrons r.m.s. (298 eV FWHM) at τ = 1 μs is found. However, the electronic noise, evaluated on the pulser FWHM, is found to only marginally contribute to the width of the spectral lines of a radioactive source, which are dominated instead by the statistical noise of the charge multiplication within the LGAD structure. The spectral lines' excess width is found to be proportional to the signal multiplication gain M s and increases with the energy of the photons. A minimum line width of 850 eV FWHM at 13.9 keV is measured at room temperature, τ = 2 μs and a gain M s = 10.2.
47 OTHER INSTRUMENTATION↗
Low-Jitter Clock Receivers for Fast Timing Applications
Precision timing is a key requirement for emerging 4D particle tracking, Positron Emission Tomography (PET), beam and fusion plasma diagnostics, and other systems. Time-to-Digital Converters (TDCs) are commonly used to provide digital estimates of the relative timing between events, but the jitter performance of a TDC can be no better than the performance of the circuits that acquire the pulses and deliver them to the TDC. Several clock receiver and distribution circuits were evaluated, and a differential amplifier with resistive loads driving a pseudo-differential clock distribution network, developed using design guidelines for radiation tolerance and cryogenic compatibility, was fabricated as part of three prototypes: an analog front-end testbed chip for high-precision timing pixel readout, a dedicated TDC evaluation chip, and a Low-Gain Avalanche Detector (LGAD) readout circuit. Based on TDC measurements of the prototypes, we infer that the jitter added by the clock receiver and distribution circuits is less than 2.25 ps-rms. This performance meets the requirements of many future precision timing systems. The clock receiver and on-chip pseudo-differential driver were fabricated in commercial 28-nm CMOS technology and occupy 2288 µm 2 .
47 OTHER INSTRUMENTATION↗
Evolution of DUNE’s Production System
The DUNE experiment will start running in 2029 and record 30 PB/year of raw waveforms from Liquid Argon TPCs and photon detectors. The size of individual readouts can range from 100 MB to a typical 8 GB full readout of the detector, and even 100 TB for extended readouts from supernova candidates. These data then need to be cataloged, stored and distributed for processing worldwide. This massive amount of data and a heterogeneous computing environment necessitates a powerful and robust distributed computing infrastructure. In the process of building up that infrastructure, DUNE’s production system has recently undergone an overhaul, in which it has integrated 1) a new workflow management system (justIN) 2) a new data catalog (MetaCat) and 3) a state-of-the-art data management system (Rucio). Simulations of DUNE’s Far Detector and its prototypes ProtoDUNE Horizontal Drift (ProtoDUNE-HD) and ProtoDUNE Vertical Drift (ProtoDUNE-VD), as well as data from ProtoDUNE-HD serve as the first tests of this infrastructure.
73 NUCLEAR PHYSICS AND RADIATION PHYSICS↗
Thermal neutron imaging detector with wavelength shifting fiber and digital readout
Here, we developed a large area, digital thermal neutron imaging detector. The detector uses a 6 LiF/ZnS(Ag) neutron-sensitive scintillator combined with wavelength shifting fiber technology. The signals from fiber channels are amplified, integrated, and digitized using individual analog-to-digital converters for each channel. The neutron position is determined from the digitized signal using a least-squares gaussian-fitting algorithm. The detector size was 77 × 38 cm 2 (2926 cm 2 ), it provided 1.3 mm resolution, and its resolution can further be improved. The detector was designed for a powder diffraction neutron scattering beamline and provided substantial improvement of d-space resolution compared with existing detectors. This detector may have broader applications due to its large area and high spatial resolution extended over its large area.
6LiF/ZnS(Ag) scintillator↗
Rad-hard readout system for Timepix3 Hybrid Pixel Detectors
The Beam Gas Ionisation (BGI) profile monitor, located in the Proton Synchrotron (PS) and Super Proton Synchrotron (SPS) at CERN, requires a radiation-tolerant readout system to transfer data from the challenging accelerator surroundings to the back-end for processing. The system needs to control and acquire data from four Timepix3 Hybrid Pixel Detectors (HPDs) located directly inside the beam pipe, a highly radioactive environment. It must ensure reliability given limited hardware access and preserve signal integrity for the high-speed data (32 channels at 320 MHz). However, due to the unavailability of a suitable rad-hard Timepix3 readout, the Beam Instrumentation PiXeL (BIPXL) readout system was designed to meet these requirements. This system employs radiation-hardened components such as the GBTx and the FEASTMP, both developed at CERN. It will be compatible with forthcoming hybrid pixel detector initiatives in similarly harsh radiation conditions.
47 OTHER INSTRUMENTATION↗
Charge readout electronics for the DUNE horizontal drift far detector: design and performance in ProtoDUNE-HD
DUNE (Deep Underground Neutrino Experiment) is a long-baseline neutrino oscillation experiment currently under construction, whose far detectors will be the largest liquid argon time projection chambers ever built. This detector design calls for custom-built cryogenic front-end electronics to meet its performance requirements. This paper describes the charge readout electronics that will be used in the DUNE horizontal drift (HD) far detector and presents performance results using data from the ProtoDUNE-HD detector, a 770 ton liquid argon time projection chamber operated at the CERN Neutrino Platform in 2024 that served as the final prototype of the DUNE HD design.
Front-end electronics for detector readout↗
ETROC1: the first full chain precision timing prototype ASIC for CMS MTD endcap timing layer upgrade
We present the design and characterization of the first fullchain precision timing prototype ASIC, named ETL Readout Chipversion 1 (ETROC1) for the CMS MTD endcap timing layer (ETL)upgrade. The ETL utilizes Low Gain Avalanche Diode (LGAD) sensors todetect charged particles, with the goal to achieve a time resolutionof 40–50 ps per hit, and 30–40 ps per track with hits from twodetector layers. The ETROC1 is composed of a 5 × 5 pixelarray and peripheral circuits. The pixel array includes a4 × 4 active pixel array with an H-tree shaped networkdelivering clock and charge injection signals. Each active pixel iscomposed of various components, including a bump pad, a chargeinjection circuit, a pre-amplifier, a discriminator, adigital-to-analog converter, and a time-to-digital converter. Thesecomponents play essential roles as the front-end link in processingLGAD signals and measuring timing-related information. Theperipheral circuits provide clock signals and readoutfunctionalities. The size of the ETROC1 chip is7 mm× 9 mm. ETROC1 has been fabricated in a 65 nmCMOS process, and extensively tested under stimuli of chargeinjection, infrared laser, and proton beam. The time resolution ofbump-bonded ETROC1 + LGAD chipsets reaches 42–46 ps per hit in thebeam test.
46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗
Versatile High-Gain Low-Noise Readout ASIC for Silicon Microstrip Tracking Detectors
This work presents Turpial, a custom-designed low- power front-end readout ASIC for microstrip silicon sensors. Implemented in 130 nm CMOS technology, the chip integrates 64 identical readout channels, each including a configurable charge-sensitive amplifier, a bipolar pulse shaper, a 32-sample 50 Msps analog memory, and a 12-bit RC-hybrid SAR ADC operating at 1 Msps. To satisfy the target power budget of 5 mW per channel, the architecture employs a time-decoupled readout scheme in which fast transient signals are first captured in the analog memory and subsequently digitized at a lower rate. Turpial supports a wide dynamic range from 1 kℎ+ to 1 Mℎ+ while maintaining low noise performance, targeting an equivalent noise charge (ENC) below 200 𝑒−including the sensor, and providing a maximum gain of 1500 mV/fC. A digital block manages slow control, data acquisition, and data serialization through dual CML 300 Mb/s serializers. In addition, an on-chip reference circuit, based on a sub-1 V bandgap reference and an integrated LDO regulator, eliminates the need for external reference circuitry. Experimental results demonstrate that both the individual building blocks and the fully integrated ASIC meet the design specifications.
Hernandez, Hugo [Stanford University] (ORCID:00000↗
First operation of a multi-channel Q-Pix prototype: measuring transverse electron diffusion in a gas time projection chamber
We report measurements of the transverse diffusion of electrons in P-10 gas (90% Ar, 10% CH 4 ) in a laboratory-scale time projection chamber (TPC) utilizing a novel pixelated signal capture and digitization technique known as Q-Pix. The Q-Pix method incorporates a precision switched integrating transimpedance amplifier whose output is compared to a threshold voltage. Upon reaching the threshold, a comparator sends a 'reset' signal, initiating a discharge of the integrating capacitor. The time difference between successive resets is inversely proportional to the average current at the pixel in that time interval, and the number of resets is directly proportional to the total collected charge. We developed a 16-channel Q-Pix prototype fabricated from commercial off-the-shelf components and coupled them to 16 concentric annular anode electrodes to measure the spatial extent of the electron swarm that reaches the anode after drifting through the uniform field of the TPC. The swarm is produced at a gold photocathode using pulsed UV light. The measured transverse diffusion agrees with simulations in PyBoltz across a range of operating pressures (200–1500 Torr). These results demonstrate that a Q-Pix readout can successfully reconstruct the ionization topology in a TPC.
47 OTHER INSTRUMENTATION↗
Event-driven readout development: testing of the EDWARD65P1 chip with integrated event generators
Building on a prototype readout integrated circuit for segmented silicon sensors with the EDWARD event-driven readout architecture, the front-end in each pixel was replaced by a hardware generator to verify readout performance, ensuring no data loss, consistent priority handling, and speed verification. Here, this generator produces Poisson-distributed readout requests with individually tunable rates per pixel via a digitally controlled oscillator. The resulting EDWARD65P1 test ASIC is a 32×32 pixel matrix with a 100 μm pitch, equipped with digital event generators simulating radiation hits at user-defined rates. Test results for this new design are presented.
47 OTHER INSTRUMENTATION↗
Graphical User Interface for a Biasing Board for the PSEC6
The PSEC6 is an application-specific integrated circuit (ASIC) designed for a readout system for a large area picosecond photodetector (LAPPD). The PSEC6 is currently in fabrication and pending testing. The testing system for the PSEC5, the previous iteration of the ASIC, required expensive and non-portable equipment, because the ASIC needs twelve adjustable reference voltages. The new testing system consists of an low-cost, open-source, cross-platform graphical user interface (GUI), a digital system, and a biasing board. The digital system is the interface between the GUI and biasing board, and can be implemented on a microcontroller or field-programmable gate array (FPGA). The biasing board contains twelve digital-to-analog converters (DACs) that are configurable via the GUI, which gives users the ability to write voltage values to all or specific DACs. The GUI was developed in C on Linux using the widget library GTK4 and cross-compiled for Windows compatibility. I2C and SPI protocols were implemented on an Adafruit Feather ESP32-S3 microcontroller to write commands to the DACs and PSEC6. A hardware implementation of the I2C protocol is in development on an FPGA. Since LAPPDs will be used by the Accelerator Neutrino Neutron Interaction Experiment (ANNIE) at Fermilab, the PSEC6 testing system in this internship project can potentially benefit future neutrino research. The project is relevant to the Department of Energy’s microelectronics mission, because the PSEC6 is an ASIC that will handle fast time signals arriving from the detector for readout. It also provided experience with building a cross-platform user interface, practicing digital design and implementation in hardware description language (HDL), and using simulations to inform new design iterations.
Guerrero, Sasha Camila [North Central Coll.]↗
Graphical User Interface for a Biasing Board for the PSEC6
The PSEC6 is an application-specific integrated circuit (ASIC) designed for a readout system for a large area picosecond photodetector (LAPPD). The PSEC6 is currently in fabrication and pending testing. The testing system for the PSEC5, the previous iteration of the ASIC, required expensive and non-portable equipment, because the ASIC needs twelve adjustable reference voltages. The new testing system consists of an low-cost, open-source, cross-platform graphical user interface (GUI), a digital system, and a biasing board. The digital system is the interface between the GUI and biasing board, and can be implemented on a microcontroller or field-programmable gate array (FPGA). The biasing board contains twelve digital-to-analog converters (DACs) that are configurable via the GUI, which gives users the ability to write voltage values to all or specific DACs. The GUI was developed in C on Linux using the widget library GTK4 and cross-compiled for Windows compatibility. I2C and SPI protocols were implemented on an Adafruit Feather ESP32-S3 microcontroller to write commands to the DACs and PSEC6. A hardware implementation of the I2C protocol is in development on an FPGA. Since LAPPDs will be used by the Accelerator Neutrino Neutron Interaction Experiment (ANNIE) at Fermilab, the PSEC6 testing system in this internship project can potentially benefit future neutrino research. The project is relevant to the Department of Energy’s microelectronics mission, because the PSEC6 is an ASIC that will handle fast time signals arriving from the detector for readout. It also provided experience with building a cross-platform user interface, practicing digital design and implementation in hardware description language (HDL), and using simulations to inform new design iterations.
Guerrero, Sasha Camila [North Central Coll.]↗
Single channel PICOSEC Micromegas detector with improved time resolution
This paper presents design guidelines and the experimental verification of a single-channel PICOSEC Micromegas (MM) detector with an improved time resolution. The design encompasses the detector board, vessel, auxiliary mechanical parts, and electrical connectivity for high voltage (HV) and signals, focusing on improving the stability, reducing noise, and ensuring signal integrity to optimize timing performance. A notable feature is the simple and fast reassembly procedure, facilitating quick replacement of the detector internal components that allows for an efficient measurement strategy involving different detector components. The paper also examines the influence of parasitic capacitance and inductance on the output signal integrity. To validate the design, a prototype assembly and three interchangeable detector boards with varying readout pad diameters were manufactured. Detectors were initially tested in the laboratory. Finally, the timing performance of the detectors with different pad sizes was verified using 150 GeV muons. Notably, a record time resolution for a PICOSEC Micromegas detector technology with a CsI photocathode of 12.5 ± 0.8 ps was achieved for a detector with 10 mm diameter readout pad size.
46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗