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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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All sourcesNASA NTRSDOE OSTI
DOE OSTI2026

Shaping the FutureWorkforce: Challenges and Lessons Learned in HPC Education from National Labs and Computing Centers

Workforce training at national laboratories and computing centers is essential and typically falls into two categories: foundational training for newcomers and advanced training for experienced users. Foundational topics—such as version control, build systems, and basic HPC usage—are largely transferable across institutions, while cluster-specific training varies due to differences in hardware, job schedulers, and local workflows. Training on emerging technologies is split between hardware-specific content and broadly applicable programming paradigms. Here, to reduce redundancy and increase impact, national labs, computing centers, and vendors are collaborating through initiatives like the HPC Training Working Group to share best practices, co-develop materials, and broaden outreach. These coordinated efforts aim to make HPC training more accessible, scalable, and consistent across the community.

HPC↗
DOE OSTI2020

Dyno-in-the-Loop: An Innovative Hardware-in-the-Loop Development and Testing Platform for Emerging Mobility Technologies

Today’s transportation is quickly transforming with the nascent advent of connectivity, automation, shared-mobility, and electrification. These technologies will not only affect our safety and mobility, but also our energy consumption, and environment. As a result, it is of unprecedented importance to understand the overall system impacts due to the introduction of these emerging technologies and concepts. Existing modeling tools are not able to effectively capture the implications of these technologies, not to mention accurately and reliably evaluating their effectiveness with a reasonable scope. To address these gaps, a dynamometer-in-the-loop (DiL) development and testing approach is proposed which integrates test vehicle(s), chassis dynamometer, and high fidelity traffic simulation tools, in order to achieve a balance between the model accuracy and scalability of environmental analysis for the next generation of transportation systems. With this DiL platform, a connected eco-operation system for the plug-in hybrid electric bus (PHEB) has been developed and tested, which can optimize the vehicle dynamics (and potentially powertrain control via smart energy management) to reduce the operational energy consumption as well as tailpipe emissions of the target PHEB. The system performance has been evaluated on the DiL platform with respect to a variety of traffic congestion levels. The results have shown that the developed system can save fuel by more than 13% while reducing the electricity consumption by 2% in the test scenarios.

Wu, Guoyuan↗
DOE OSTI2025

Leveraging dendritic complexity for neuromorphic computing

Abstract Beyond-von Neumann computing approaches are necessary to sustain the growth of microelectronics and the increasing appetite for artificial intelligence/machine learning algorithms. Neuromorphic computing is an emerging paradigm that takes inspiration from the brain to provide a path forward to improve the computational efficiency and computational density of next-generation computing architectures. In nature, we observe brains performing complex computations with a much smaller energy footprint than conventional computing approaches. Current neuromorphic systems are focused primarily on scalability, namely, increasing the number of computational units (neurons) and connections between units (synapses). However, for brain-like cognition and efficiency in next-generation computing hardware, we need increased complexity in function, as well as improved connection density for scalability. Here, we present our work that aims to incorporate dendrites for ‘compute-on-wire’ in neuromorphic architectures to increase the computational complexity (e.g. number of programmable parameters, nonlinear dynamics) as well as computational efficiency (energy/compute) of artificial neural networks (ANNs). We do this by showcasing neuromorphic dendrite elements that can be leveraged for various applications. We will present examples of neuroscience-inspired direction-selective circuits and an ANN with active dendrites leveraging shunting inhibition. We also demonstrate the benefits of using dendrites in deep neural networks. To conclude, we discuss how we can utilize emerging hardware devices in these systems and design next-generation neuromorphic architectures with dendrites.

Cardwell, Suma G. (ORCID:0000000226575545)↗
DOE OSTI2020

Analysis of Threading Libraries for High Performance Computing

With the appearance of multi-/many core machines, applications and runtime systems have evolved in order to exploit the new on-node concurrency brought by new software paradigms. POSIX threads (Pthreads) was widely-adopted for that purpose and it remains as the most used threading solution in current hardware. Lightweight thread (LWT) libraries emerged as an alternative offering lighter mechanisms to tackle the massive concurrency of current hardware. In this article, we analyze in detail the most representative threading libraries including Pthread- and LWT-based solutions. In addition, to examine the suitability of LWTs for different use cases, we develop a set of microbenchmarks consisting of OpenMP patterns commonly found in current parallel codes, and we compare the results using threading libraries and OpenMP implementations. Moreover, we study the semantics offered by threading libraries in order to expose the similarities among different LWT application programming interfaces and their advantages over Pthreads. This article exposes that LWT libraries outperform solutions based on operating system threads when tasks and nested parallelism are required.

GLT↗
DOE OSTI2022

Computer Science Research Needs for Parallel Discrete Event Simulation (PDES)

Historically, scientific computing efforts have demonstrated the clear need for, and effective use of, supercomputing with traditional time-stepped simulations. Nevertheless, there are several areas in the mission spaces of the U.S. Department of Energy and other agencies waiting to tap advanced computing research using a different, discrete event style of modeling, simulation, and analysis. These span a wide spectrum of applications including energy grid resilience, urban planning and policy, transportation science, building technologies, emergency response and planning, environmental impact analysis, computational epidemiology, Internet communications, cyber security, and cyber-physical systems, to name only a few. Even within traditional scientific applications, the role of discrete event modes of execution is increasing in the form of new event-based mathematical solvers such as quantized state integration methods and discrete-continuous hybrid system solvers. Co-design of advanced supercomputing hardware systems is another area that exploits discrete event simulation at its core for effective analyses. Complex systems, entity behaviors and interconnections play a significant role in all these applications, which are mapped to large-scale models with discrete event formulations. To make advancements in all the aforementioned scientific areas, many technical aspects need to be more thoroughly studied and deeply understood in parallel discrete event simulation (PDES). The unique dynamics inherent in a discrete event modeling approach, by their very nature, intersect and influence the entire stack of the computing system, including (a) the unique nature of the instruction sets exercised in PDES workloads without a predominance of high-precision floating point operations, (b) virtual time-constrained multi-threaded execution of many logical processes per processor, (c) extremely variable and difficult to predict network traffic characteristics, (d) interfaces and inter-dependencies with machine learning and artificial intelligence codes at higher software layers, and (e) highly challenging load balancing needs, especially in effectively accounting for accelerated/extremely heterogeneous computing in current and future high-performance computing systems. Efficient and accurate parallel execution of PDES workloads is also dominated by challenges in dealing with their asynchronous concurrency fundamentally present at the model level. Conservative synchronization, optimistic/speculative synchronization, and their hybrid schemes open new questions in fundamental computer science with respect to reversibility of computation and prediction (lookahead) of behaviors inherent within model codes. On the implementation front, there are relatively few scalable, general-purpose parallel discrete event simulators in the world, and even fewer have been studied on emerging hardware platforms. To enable scientific advances using PDES, the research needs in computer science must also be pursued and met in the intersection of the algorithmic and hardware-aware aspects of scalable PDES engines. This report is aimed at capturing a computer science-oriented view of this important area of research in PDES, presenting a sample of important applications with their inherent discrete event technology elements. Needs are outlined in core areas of parallel discrete event research as well as cross-cutting directions in computer science research that positively impact scientific advancements across several important application areas. A selection of priority research opportunities in advanced computing for PDES is identified to serve as reference for key research topics and their order of importance for scientific advancements.

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2020

Electronic structure with direct diagonalization on a D-wave quantum annealer

Quantum chemistry is regarded to be one of the first disciplines that will be revolutionized by quantum computing. Although universal quantum computers of practical scale may be years away, various approaches are currently being pursued to solve quantum chemistry problems on near-term gate-based quantum computers and quantum annealers by developing the appropriate algorithm and software base. This work implements the general Quantum Annealer Eigensolver (QAE) algorithm to solve the molecular electronic Hamiltonian eigenvalue-eigenvector problem on a D-Wave 2000Q quantum annealer. The approach is based on the matrix formulation, efficiently uses qubit resources based on a power-of-two encoding scheme and is hardware-dominant relying on only one classically optimized parameter. We demonstrate the use of D-Wave hardware for obtaining ground and excited electronic states across a variety of small molecular systems. The approach can be adapted for use by a vast majority of electronic structure methods currently implemented in conventional quantum-chemical packages. The results of this work will encourage further development of software such as qbsolv which has promising applications in emerging quantum information processing hardware and has expectation to address large and complex optimization problems intractable for classical computers.

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2021

ARENA: Asynchronous Reconfigurable Accelerator Ring to Enable Data-Centric Parallel Computing

The next generation HPC and data centers are likely to be reconfigurable and data-centric due to the trend of hardware specialization and the emergence of data-driven applications. In this work, we propose ARENA – an asynchronous reconfigurable accelerator ring architecture as a potential scenario on how the future HPC and data centers will be like. Despite using the coarse-grained reconfigurable arrays (CGRAs) as the substrate platform, our key contribution is not only the CGRA-cluster design itself, but also the ensemble of a new architecture and programming model that enables asynchronous tasking across a cluster of reconfigurable nodes, so as to bring specialized computation to the data rather than the reverse. We presume distributed data storage without asserting any prior knowledge on the data distribution. Hardware specialization occurs at runtime when a task finds the majority of data it requires are available at the present node. In other words, we dynamically generate specialized CGRA accelerators where the data reside. The asynchronous tasking for bringing computation to data is achieved by circulating the task token, which describes the dataflow graphs to be executed for a task, among the CGRA cluster connected by a fast ring network. Evaluations on a set of HPC and data-driven applications across different domains show that ARENA can provide better parallel scalability with reduced data movement (53.9 percent). Compared with contemporary compute-centric parallel models, ARENA can bring on average 4.37× speedup. The synthesized CGRAs and their task-dispatchers only occupy 2.93mm 2 chip area under 45nm process technology and can run at 800MHz with on average 759.8mW power consumption. ARENA also supports the concurrent execution of multi-applications, offering ideal architectural support for future high-performance parallel computing and data analytics systems.

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2023

Integration of Ag-CBRAM crossbars and Mott ReLU neurons for efficient implementation of deep neural networks in hardware

In-memory computing with emerging non-volatile memory devices (eNVMs) has shown promising results in accelerating matrix-vector multiplications. However, activation function calculations are still being implemented with general processors or large and complex neuron peripheral circuits. Here, we present the integration of Ag-based conductive bridge random access memory (Ag-CBRAM) crossbar arrays with Mott rectified linear unit (ReLU) activation neurons for scalable, energy and area-efficient hardware (HW) implementation of deep neural networks. We develop Ag-CBRAM devices that can achieve a high ON/OFF ratio and multi-level programmability. Compact and energy-efficient Mott ReLU neuron devices implementing ReLU activation function are directly connected to the columns of Ag-CBRAM crossbars to compute the output from the weighted sum current. We implement convolution filters and activations for VGG-16 using our integrated HW and demonstrate the successful generation of feature maps for CIFAR-10 images in HW. Our approach paves a new way toward building a highly compact and energy-efficient eNVMs-based in-memory computing system.

Mott insulators↗
DOE OSTI2021

Low-temperature emergent neuromorphic networks with correlated oxide devices

Significance Designing neuromorphic hardware for cryoelectronics is an important area of research as the field of computing paradigms beyond complementary metal-oxide-semiconductor (CMOS) progresses. Superconductivity and metal−insulator transitions are two of the most celebrated emergent, collective properties found in quantum materials such as strongly correlated oxides. Here, we present simulations of artificial neural networks that can be designed by combining superconducting devices (e.g. Josephson junctions) with Mott metal−insulator transition−based tunable resistor devices. Our simulations show that 1) neurons and synapses can be seamlessly created, 2) their functions can be tuned via learning, and 3) controlling disorder by incorporating light ions enables exponential multiplicity of states. The results open up directions for incorporating emergent behavior seen in condensed matter into hardware design for artificial intelligence.

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2022

DFSynthesizer: Dataflow-based Synthesis of Spiking Neural Networks to Neuromorphic Hardware

Spiking Neural Networks (SNNs) are an emerging computation model that uses event-driven activation and bio-inspired learning algorithms. SNN-based machine learning programs are typically executed on tile-based neuromorphic hardware platforms, where each tile consists of a computation unit called a crossbar, which maps neurons and synapses of the program. However, synthesizing such programs on an off-the-shelf neuromorphic hardware is challenging. This is because of the inherent resource and latency limitations of the hardware, which impact both model performance, e.g., accuracy, and hardware performance, e.g., throughput. We propose DFSynthesizer, an end-to-end framework for synthesizing SNN-based machine learning programs to neuromorphic hardware. The proposed framework works in four steps. First, it analyzes a machine learning program and generates SNN workload using representative data. Second, it partitions the SNN workload and generates clusters that fit on crossbars of the target neuromorphic hardware. Third, it exploits the rich semantics of the Synchronous Dataflow Graph (SDFG) to represent a clustered SNN program, allowing for performance analysis in terms of key hardware constraints such as number of crossbars, dimension of each crossbar, buffer space on tiles, and tile communication bandwidth. Finally, it uses a novel scheduling algorithm to execute clusters on crossbars of the hardware, guaranteeing hardware performance. We evaluate DFSynthesizer with 10 commonly used machine learning programs. Our results demonstrate that DFSynthesizer provides a much tighter performance guarantee compared to current mapping approaches.

Computer Science↗
DOE OSTI2024

PHIL Interface Design for Use With a Voltage-Regulated Amplifier

Power hardware-in-the-loop (PHIL) has emerged as a leading strategy to thoroughly assess the impact of proprietary inverter controls on a specific power system. The development of a PHIL test bed typically involves an inverter under test, a power amplifier, controllable DC supply, and a digital real-time simulator (DRTS) to simulate the power system under study. As a result of PHIL nonidealities, a form of digital compensation within the DRTS is used, which is commonly referred to as a PHIL interface. Many existing methods use legacy power amplifiers that do not contain internal voltage regulation. These existing interface methods are based around a voltage regulator within the DRTS and do not consider the interaction with the controls in newer amplifiers. In this study, a three-step approach of PHIL interface development for modern power amplifiers with built-in voltage regulation is introduced and is validated in hardware with a 30-kW grid-following inverter.

DRTS↗
DOE OSTI2022

Open-source FPGA-ML codesign for the MLPerf Tiny Benchmark

We present our development experience and recent results for the MLPerf Tiny Inference Benchmark on field-programmable gate array (FPGA) platforms. We use the open-source hls4ml and FINN workflows, which aim to democratize AI-hardware codesign of optimized neural networks on FPGAs. We present the design and implementation process for the keyword spotting, anomaly detection, and image classification benchmark tasks. The resulting hardware implementations are quantized, configurable, spatial dataflow architectures tailored for speed and efficiency and introduce new generic optimizations and common workflows developed as a part of this work. The full workflow is presented from quantization-aware training to FPGA implementation. The solutions are deployed on system-on-chip (Pynq-Z2) and pure FPGA (Arty A7-100T) platforms. The resulting submissions achieve latencies as low as 20 $\mu$s and energy consumption as low as 30 $\mu$J per inference. We demonstrate how emerging ML benchmarks on heterogeneous hardware platforms can catalyze collaboration and the development of new techniques and more accessible tools.

Borras, Hendrik↗
DOE OSTI2025

Transmission electron microscopy with in-situ ion irradiation: Facilities and community

Whilst there is a clear scientific and technological need for the technical capabilities of transmission electron microscopes with in-situ ion irradiation, it also requires a collaborative community of international researchers to support such facilities in successfully meeting this demand. Instruments of this type serve to provide fundamental understanding of the mechanisms which drive changes in materials important to nuclear fission and fusion energy, the semiconductor industry, quantum information systems, space travel, astronomy, geology and many more applications. As these areas continue to evolve and the instrumentation possibilities expand, the capacity of in-situ ion irradiation facilities must also develop hand-in-hand with the user community to deliver an ever-greater diversity of high-fidelity extreme-environment experimentation. Future directions for the field, such as miniaturization from MEMS/microfluidic devices and advanced controls with ML-based analysis, continuously emerge to advance both the hardware and software which support the coupling of TEMs with ion beams. This review sets out to provide up-to-date insights into the community and advancement of current, and development of future, facilities which have the potential to further unlock access to the nanoscale exploration of coupled extreme environments crucial to many of the important science and engineering challenges we face today.

In-situ irradiation↗
DOE OSTI2023

PHIL Interface Design for Use With a Voltage-Regulated Amplifier: Preprint

As inverter controls have become increasingly complex, power hardware-in-the-loop (PHIL) has emerged as a leading strategy to thoroughly assess the impact of proprietary inverter controls on a specific power system. The development of a PHIL test bed typically involves the desired inverter, a power amplifier, and a digital real-time simulator (DRTS) to control the simulated power system. As a result of PHIL nonidealities, a form of digital compensation within the DRTS is used, which is commonly referred to as a PHIL interface. The interface design for PHIL test beds has been previously examined in the literature, but many existing methods use older power amplifiers that do not contain internal voltage regulation. These existing interface methods are based around a voltage regulator within the DRTS rather than one preexisting in hardware. In this study, a three-step approach of PHIL interface development for modern power amplifiers with built-in voltage regulation is introduced and validated in hardware with a single 30-kW grid-following inverter.

DRTS↗
DOE OSTI2026

Operando microscopy for neuromorphic hardware

Microscopy techniques can uncover the physical properties and dynamic behaviours of materials, driving the discovery of emergent phenomena and guiding the design of next-generation computing hardware. As artificial intelligence becomes pervasive, the demand for high-performance materials to support sustainable information technologies is growing. Here, this Review highlights state-of-the-art imaging from electron and X-ray to optical techniques to probe the dynamics of neuromorphic materials, including operando characterization of devices. We examine design principles for neuromorphic materials, along with obstacles that hinder their development. Emphasis is placed on spatially and temporally resolved approaches that capture state changes including phase transitions, ferroic switching and spin-wave propagation that emulate biological components such as neurons, synapses and their connectivity. We discuss challenges in operando characterization and the integration of artificial intelligence-driven analysis for feedback-guided material discovery. Finally, we outline opportunities for real-time imaging of neuromorphic systems, paving the way towards adaptive, brain-inspired hardware.

75 CONDENSED MATTER PHYSICS, SUPERCONDUCTIVITY AND↗
DOE OSTI2023

Chemical Profiles of the Oxides on Tantalum in State of the Art Superconducting Circuits

Abstract Over the past decades, superconducting qubits have emerged as one of the leading hardware platforms for realizing a quantum processor. Consequently, researchers have made significant effort to understand the loss channels that limit the coherence times of superconducting qubits. A major source of loss has been attributed to two level systems that are present at the material interfaces. It is recently shown that replacing the metal in the capacitor of a transmon with tantalum yields record relaxation and coherence times for superconducting qubits, motivating a detailed study of the tantalum surface. In this work, the chemical profile of the surface of tantalum films grown on c‐plane sapphire using variable energy X‐ray photoelectron spectroscopy (VEXPS) is studied. The different oxidation states of tantalum that are present in the native oxide resulting from exposure to air are identified, and their distribution through the depth of the film is measured. Furthermore, it is shown how the volume and depth distribution of these tantalum oxidation states can be altered by various chemical treatments. Correlating these measurements with detailed measurements of quantum devices may elucidate the underlying microscopic sources of loss.

36 MATERIALS SCIENCE↗
DOE OSTI2025

Dielectric-Engineered Monolayer MoS 2 Memtransistors for Brain-Inspired Computing with High Recognition Accuracy

Two-dimensional transition metal dichalcogenides (2D-TMDs)-based memtransistors have emerged as promising candidates for neuromorphic hardware due to their exceptional ability to emulate synaptic behavior. However, many existing 2D-TMDs memtransistors rely on polycrystalline channels with grain boundaries or defects introduced through postgrowth treatments, raising concerns about material integrity and the preservation of intrinsic properties. Here, in this work, we demonstrate a monocrystalline monolayer MoS 2 memtransistor fabricated on a silicon nitride (SiN X ) substrate, achieving a large resistive switching ratio of 10 4 , a dynamic range exceeding 90, along with highly linear and symmetric weight updates, minimal cycle-to-cycle variability, and low device-to-device variability. These attributes are critical for enabling high-performance neuromorphic hardware. Based on experimental data, we further show that these artificial synapses enable a recognition accuracy of more than 97% on the MNIST handwritten digits data set. Our findings present a straightforward approach to realizing 2D-TMDs memtransistors through dielectric engineering, offering a promising platform for next-generation neuromorphic computing systems.

2D TMDs↗