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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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25 records · Page 2
All sourcesNASA NTRSDOE OSTI
DOE OSTI2025

Increasing Radon Daughter Plate-out onto Superconducting Qubits

Radon daughter plate-out may pose a fundamental limitation to realizing large-scale superconducting quantum computers. Radon daughters plated-out onto a superconducting qubit chip can decay, releasing energy into the substrate, producing phonons. Phonon induced quasiparticles generate bit flip errors and reduce coherence times. We seek to increase plate-out on chips to enable future study of the impact of Radon on coherence times. In this project, we utilize COMSOL Multiphysics simulations to finalize design for a device to increase radon plate-out.

Kay, Dax [Northwestern U.]↗
DOE OSTI2024

Tailor : Altering Skip Connections for Resource-Efficient Inference

Deep neural networks use skip connections to improve training convergence. However, these skip connections are costly in hardware, requiring extra buffers and increasing on- and off-chip memory utilization and bandwidth requirements. In this article, we show that skip connections can be optimized for hardware when tackled with a hardware-software codesign approach. We argue that while a network’s skip connections are needed for the network to learn, they can later be removed or shortened to provide a more hardware-efficient implementation with minimal to no accuracy loss. We introduceTailor, a codesign tool whose hardware-aware training algorithm gradually removes or shortens a fully trained network’s skip connections to lower the hardware cost.Tailorimproves resource utilization by up to 34% for block random access memories (BRAMs), 13% for flip-flops (FFs), and 16% for look-up tables (LUTs) for on-chip, dataflow-style architectures.Tailorincreases performance by 30% and reduces memory bandwidth by 45% for a two-dimensional processing element array architecture.

Computer Science↗
DOE OSTI2024

The Single Event Error (SEE) test and analysis of the CMS Endcap Timing Layer readout chip

The ETROC2, the first full size and full functionality prototype chip for the CMS Endcap Timing Layer readout, is strategically designed to meet the SEE immunity requirements of detector operation with the low power constraint. The triplicated periphery and pixel I2C configuration registers are designed with self-correction feature. The pixel readout control is centralized in the global readout and fully triplicated. The pixel readout is not triplicated, instead protected with power-efficient one-bit correction Hamming code. The TMR protection of the on-pixel threshold calibration can be turned off allowing the detection of the beam spot during the beam test by checking the bit-flips of the internal memory cells. In the initial proton beam test in January 2024, the chip readout process did not hang throughout the tests. The Hamming code correction strategy works because the error corrected TDC data were observed in the data frames. The error-injection simulation is performed to analy ze the small number of bit-flips in the configuration registers. We also performed SEE testing with a heavy ion beam in April and the data analysis is ongoing. The detailed design on the SEE immunity and the testing as well as simulation results will be presented, including follow-up SEE testing results in May and June 2024.

Gong, Datao↗
DOE OSTI2026

Increasing Radon Daughter Plate-out onto Superconducting Qubits

Radon daughter plate-out may pose a fundamental limitation to realizing large-scale superconducting quantum computers. Radon daughters plated-out on a superconducting qubit can decay, releasing energy into the substrate, producing phonons. Phonon-induced quasiparticles then generate bit-flip errors and reduce coherence times. We seek to increase plate-out on chips to enable future study of the impact of radon on coherence times. In this project, we utilize COMSOL Multiphysics simulations to visualize electric field configuration and model ion transport to finalize design of a device to increase radon plate-out on qubit chips.

Kay, Dax [Fermilab; Northwestern U.]↗
DOE OSTI2025

Spin Decoherence Dynamics of Er 3+ in CeO 2 Films

Developing telecom-compatible spin-photon interfaces is essential towards scalable quantum networks. Erbium ions (Er 3+ ) exhibit a unique combination of a telecom (1.5 mu m) optical transition and an effective spin-1=2 ground state, but identifying a host that enables heterogeneous device integration while preserving long optical and spin coherence remains an open challenge. In this work, we explore the potential of Er 3+ :CeO 2 films on silicon and study the Er 3+ spin coherence, offering low nuclear spin density and the potential for on-chip integration. We demonstrate a 38.8 mu s spin coherence, which can be extended to 176.4 mu s with dynamical decoupling. Pairing experiments with cluster correlation expansion calculations, we identify spectral diffusion induced by bath Er 3+ spin flip-flops as the dominant decoherence mechanism and provide pathways to millisecond-scale coherence.

36 MATERIALS SCIENCE↗
DOE OSTI2024

Entropy Analysis of FPGA Interconnect and Switch Matrices for Physical Unclonable Functions

Random variations in microelectronic circuit structures represent the source of entropy for physical unclonable functions (PUFs). In this paper, we investigate delay variations that occur through the routing network and switch matrices of a field-programmable gate array (FPGA). The delay variations are isolated from other components of the programmable logic, e.g., look-up tables (LUTs), flip-flops (FFs), etc., using a feature of Xilinx FPGAs called dynamic partial reconfiguration (DPR). A set of partial designs is created to fix the placement of a time-to-digital converter (TDC) and supporting infrastructure to enable the path delays through the target interconnect and switch matrices to be extracted by subtracting out common-mode delay components. Delay variations are analyzed in the different levels of routing resources available within FPGAs, i.e., local routing and across-chip routing. Data are collected from a set of Xilinx Zynq 7010 devices, and a statistical analysis of within-die variations in delay through a set of the randomly-generated and hand-crafted interconnects is presented.

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2021

Correlated charge noise and relaxation errors in superconducting qubits

In This report, the central challenge in building a quantum computer is error correction. Unlike classical bits, which are susceptible to only one type of error, quantum bits (“qubits”) are susceptible to two types of error, corresponding to flips of the qubit state about the X- and Z-directions. While the Heisenberg Uncertainty Principle precludes simultaneous monitoring of X- and Z-flips on a single qubit, it is possible to encode quantum information in large arrays of entangled qubits that enable accurate monitoring of all errors in the system, provided the error rate is low. Another crucial requirement is that errors cannot be correlated. Here, we characterize a superconducting multiqubit circuit and find that charge fluctuations are highly correlated on a length scale over 600 µm; moreover, discrete charge jumps are accompanied by a strong transient suppression of qubit energy relaxation time across the millimeter-scale chip. The resulting correlated errors are explained in terms of the charging event and phonon-mediated quasiparticle poisoning associated with absorption of gamma rays and cosmic-ray muons in the qubit substrate. Robust quantum error correction will require the development of mitigation strategies to protect multiqubit arrays from correlated errors due to particle impacts.

70 PLASMA PHYSICS AND FUSION TECHNOLOGY↗