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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 37 records · Page 2
All sourcesNASA NTRSDOE OSTI
NASA NTRS2004

Effects of Heavy Ion Exposure on Nanocrystal Nonvolatile Memory

We have irradiated engineering samples of Freescale 4M nonvolatile memories with heavy ions. They use Silicon nanocrystals as the storage element, rather than the more common floating gate. The irradiations were performed using the Texas A&M University cyclotron Single Event Effects Test Facility. The chips were tested in the static mode, and in the dynamic read mode, dynamic write (program) mode, and dynamic erase mode. All the errors observed appeared to be due to single, isolated bits, even in the program and erase modes. These errors appeared to be related to the micro-dose mechanism. All the errors corresponded to the loss of electrons from a programmed cell. The underlying physical mechanisms will be discussed in more detail later. There were no errors, which could be attributed to malfunctions of the control circuits. At the highest LET used in the test (85 MeV/mg/sq cm), however, there appeared to be a failure due to gate rupture. Failure analysis is being conducted to confirm this conclusion. There was no unambiguous evidence of latchup under any test conditions. Generally, the results on the nanocrystal technology compare favorably with results on currently available commercial floating gate technology, indicating that the technology is promising for future space applications, both civilian and military.

Oldham, Timothy R.↗
DOE OSTI2024

Readout optimization of multi-amplifier sensing charge-coupled devices for single-quantum measurement

The non-destructive readout capability of the Skipper Charge Coupled Device (CCD) has been demonstrated to reduce the noise limitation of conventional silicon devices to levels that allow single-photon or single-electron counting. The noise reduction is achieved by taking multiple measurements of the charge in each pixel. These multiple measurements come at the cost of extra readout time, which has been a limitation for the broader adoption of this technology in particle physics, quantum imaging, and astronomy applications. This work presents recent results of a novel sensor architecture that uses multiple non-destructive floating-gate amplifiers in series to achieve sub-electron readout noise in a thick, fully-depleted silicon detector to overcome the readout time overhead of the Skipper-CCD. This sensor is called the Multiple-Amplifier Sensing Charge-Coupled Device (MAS-CCD) can perform multiple independent charge measurements with each amplifier, and the measurements from multiple amplifiers can be combined to further reduce the readout noise. We will show results obtained for sensors with 8 and 16 amplifiers per readout stage in new readout operations modes to optimize its readout speed. The noise reduction capability of the new techniques will be demonstrated in terms of its ability to reduce the noise by combining the information from the different amplifiers, and to resolve signals in the order of a single photon per pixel. The first readout operation explored here avoids the extra readout time needed in the MAS-CCD to read a line of the sensor associated with the extra extent of the serial register. The second technique explore the capability of the MAS-CCD device to perform a region of interest readout increasing the number of multiple samples per amplifier in a targeted region of the active area of the device.

72 PHYSICS OF ELEMENTARY PARTICLES AND FIELDS↗
NASA NTRS1991

Stacked-Gate FET's For Analog Memory Elements

Three-terminal, double-stacked-gate field-effect transistor (FET), developed as analog memory element. Particularly suited for use as synapse with variable connection strength in electronic neural network. Provides programmable, nonvolatile resistive connection, somewhat in manner of porous-gate FET described in "Porous-Floating-Gate Field-Effect Transistor" (NPO-17532). Resembles commercial erasable programmable read-only memory (EPROM) device, except for thickness of layers of silicon dioxide electrically isolating gates. Either p-channel or n-channel device.

Thakoor, Anilkumar P.↗
NASA NTRS2005

Active pixel sensor pixel having a photodetector whose output is coupled to an output transistor gate

An imaging device formed as a monolithic complementary metal oxide semiconductor integrated circuit in an industry standard complementary metal oxide semiconductor process, the integrated circuit including a focal plane array of pixel cells, each one of the cells including a photogate overlying the substrate for accumulating photo-generated charge in an underlying portion of the substrate and a charge coupled device section formed on the substrate adjacent the photogate having a sensing node and at least one charge coupled device stage for transferring charge from the underlying portion of the substrate to the sensing node. There is also a readout circuit, part of which can be disposed at the bottom of each column of cells and be common to all the cells in the column. A Simple Floating Gate (SFG) pixel structure could also be employed in the imager to provide a non-destructive readout and smaller pixel sizes.

Fossum, Eric R.↗
NASA NTRS2017

Environmental Effects on Data Retention in Flash Cells

Flash technology is being utilized in fuzed munition applications and, based on the development of digital logic devices in the commercial world, usage of flash technology will increase. Antifuse technology, prevalent in non-volatile field programmable gate arrays (FPGAs), will eventually be phased out as new devices have not been developed for approximately a decade. The reliance on flash technology presents a long-term reliability issue for both DoD and NASA safety- and mission-critical applications. A thorough understanding of the data retention failure modes and statistics associated with Flash data retention is of vital concern to the fuze safety community. A key retention parameter for a flash cell is the threshold voltage (VTH), which is an indirect indicator of the amount of charge stored on the cells floating gate. This paper will present the results of our on-going tests: long-term storage at 150 C for a small population of devices, neutron radiation exposure, electrostatic discharge (ESD) testing, and the trends of large populations (over 300 devices for each condition) exposed to three difference temperatures: 25 C, 125 C, and 150 C.

Flash↗
NASA NTRS1975

A 190 by 244 charge-coupled area image sensor with interline transfer organization

A 190 x 244 element charge coupled area image sensor has been designed, fabricated and tested. This sensor employs an interline transfer organization and buried n-channel technology. It features a novel on-chip charge integrator and a distributed floating gate amplifier for high and low light level applications. The X-Y element count has been chosen to establish the capability of producing an NTSC compatible video signal. The array size is also compatible with the Super 8 lens format. The first few sample devices have been successfully operated at full video bandwidth for both high and low light levels with the charge amplifier system.

Walsh, L. R.↗
NASA NTRS1992

Cryogenic measurements of aerojet GaAs n-JFETs

The spectral noise characteristics of Aerojet GaAs n-JFETs have been investigated down to liquid helium temperatures. Voltage noise characterization was performed with the FET in 1) the floating gate mode, 2) the grounded gate mode to determine the lowest noise readings possible and 3) with an extrinsic silicon photodetector at various detector bias voltages, to determine optimum operating conditions. Current noise characterization was measured at the drain in the temperature range 300 to 77 K. Device design and MBE processing are described. Static I-V characterization is done at 300, 77 and 6 K. The measurements indicate that the Aerojet GaAs n-JFET is a quiet and stable device at liquid helium temperatures. Hence, it can be considered as a readout line driver or infrared detector preamplifier as well as a host of other cryogenic applications. Its noise performance is superior to that of Si MOSFETs operating at liquid helium temperatures, and is equal to the best Si n-JFETs operating at 300 K.

Goebel, John H.↗
NASA NTRS1993

Cryogenic measurements of aerojet GaAs n-JFETs

The spectral noise characteristics of Aerojet gallium arsenide (GaAs) junction field effect transistors (JFET's) have been investigated down to liquid-helium temperatures. Noise characterization was performed with the field effect transistor (FET) in the floating-gate mode, in the grounded-gate mode to determine the lowest noise readings possible, and with an extrinsic silicon photodetector at various detector bias voltages to determine optimum operating conditions. The measurements indicate that the Aerojet GaAs JFET is a quiet and stable device at liquid helium temperatures. Hence, it can be considered a readout line driver or infrared detector preamplifier as well as a host of other cryogenic applications. Its noise performance is superior to silicon (Si) metal oxide semiconductor field effect transistor (MOSFET's) operating at liquid helium temperatures, and is equal to the best Si n channel junction field effect transistor (n-JFET's) operating at 300 K.

Goebel, John H.↗
NASA NTRS1994

Nonvolatile programmable neural network synaptic array

A floating-gate metal oxide semiconductor (MOS) transistor is implemented for use as a nonvolatile analog storage element of a synaptic cell used to implement an array of processing synaptic cells. These cells are based on a four-quadrant analog multiplier requiring both X and Y differential inputs, where one Y input is UV programmable. These nonvolatile synaptic cells are disclosed fully connected in a 32 x 32 synaptic cell array using standard very large scale integration (VLSI) complementary MOS (CMOS) technology.

Tawel, Raoul↗
NASA NTRS1998

Radiation Effects on Advanced Flash Memories

Flash memories have evolved very rapidly in recent ears. New design techniques such as multilevel storage have been proposed to increase storage density, and are now available commercially. Threshold voltage distributions for single- and three-level technologies are compared. In order to implement this technology special circuitry must be added to allow the amount of charge stored in the floating gate to be controlled within narrow limits during the writing and also to detect the different amounts of charge during reading.

Nguyen, D. N.↗
NASA NTRS2010

Modeling of Sonos Memory Cell Erase Cycle

Silicon-oxide-nitride-oxide-silicon (SONOS) nonvolatile semiconductor memories (NVSMS) have many advantages. These memories are electrically erasable programmable read-only memories (EEPROMs). They utilize low programming voltages, endure extended erase/write cycles, are inherently resistant to radiation, and are compatible with high-density scaled CMOS for low power, portable electronics. The SONOS memory cell erase cycle was investigated using a nonquasi-static (NQS) MOSFET model. The SONOS floating gate charge and voltage, tunneling current, threshold voltage, and drain current were characterized during an erase cycle. Comparisons were made between the model predictions and experimental device data.

Phillips, Thomas A.↗
NASA NTRS2010

SONOS Nonvolatile Memory Cell Programming Characteristics

Silicon-oxide-nitride-oxide-silicon (SONOS) nonvolatile memory is gaining favor over conventional EEPROM FLASH memory technology. This paper characterizes the SONOS write operation using a nonquasi-static MOSFET model. This includes floating gate charge and voltage characteristics as well as tunneling current, voltage threshold and drain current characterization. The characterization of the SONOS memory cell predicted by the model closely agrees with experimental data obtained from actual SONOS memory cells. The tunnel current, drain current, threshold voltage and read drain current all closely agreed with empirical data.

MacLeod, Todd C.↗
NASA NTRS2010

Evaluation of COTS SiGe, SOI, and Mixed Signal Electronic Parts for Extreme Temperature Use in NASA Missions

The NASA Electronic Parts and Packaging (NEPP) Program sponsors a task at the NASA Glenn Research Center titled "Reliability of SiGe, SOI, and Advanced Mixed Signal Devices for Cryogenic Space Missions." In this task COTS parts and flight-like are evaluated by determining their performance under extreme temperatures and thermal cycling. The results from the evaluations are published on the NEPP website and at professional conferences in order to disseminate information to mission planners and system designers. This presentation discusses the task and the 2010 highlights and technical results. Topics include extreme temperature operation of SiGe and SOI devices, all-silicon oscillators, a floating gate voltage reference, a MEMS oscillator, extreme temperature resistors and capacitors, and a high temperature silicon operational amplifier.

Patterson, Richard L.↗
NASA NTRS2014

Evaluation of Magnetoresistive RAM for Space Applications

Magnetoresistive random-access memory (MRAM) is a non-volatile memory that exploits electronic spin, rather than charge, to store data. Instead of moving charge on and off a floating gate to alter the threshold voltage of a CMOS transistor (creating different bit states), MRAM uses magnetic fields to flip the polarization of a ferromagnetic material thus switching its resistance and bit state. These polarized states are immune to radiation-induced upset, thus making MRAM very attractive for space application. These magnetic memory elements also have infinite data retention and erase/program endurance. Presented here are results of reliability testing of two space-qualified MRAM products from Aeroflex and Honeywell.

Heidecker, Jason↗
NASA NTRS2016

An Evaluation of Flash Cells Used in Critical Applications

Due to the common use of Flash technology in many commercial and industrial Programmable Logic Devices (PLDs) such as FPGAs and mixed-signal microcontrollers, flash technology is being utilized in fuzed munition applications. This presents a long-term reliability issue for both DoD and NASA safety- and mission-critical applications. A thorough understanding of the data retention failure modes and statistics associated with Flash data retention is of vital concern to the fuze safety community. A key retention parameter for a flash cell is the threshold voltage (VTH), which is an indirect indicator of the amount of charge stored on the cells floating gate. Initial test results based on a study of charge loss in flash cells in an FPGA device is presented. Statistical data taken from a small sample set indicates quantifiable charge loss for devices stored at both room temperature and 150 C. Initial evaluation of the distribution of threshold voltage in a large sample set (800 devices) is presented. The magnitude of charge loss from exposure to electrostatic discharge and electromagnetic fields is measured and presented. Simulated data (and measured data as available) resultant from harsh-environment testing (neutron, heavy ion, EMP) is presented.

data retention↗
NASA NTRS2016

An Evaluation of Flash Cells Used in Critical Applications

Due to the common use of Flash technology in many commercial and industrial Programmable Logic Devices (PLDs) such as FPGAs and mixed-signal microcontrollers, flash technology is being utilized in fuzed munition applications. This presents a long-term reliability issue for both DoD and NASA safety- and mission-critical applications. A thorough understanding of the data retention failure modes and statistics associated with Flash data retention is of vital concern to the fuze safety community. A key retention parameter for a flash cell is the threshold voltage (VTH), which is an indirect indicator of the amount of charge stored on the cells floating gate. Initial test results based on a study of charge loss in flash cells in an FPGA device is presented. Statistical data taken from a small sample set indicates quantifiable charge loss for devices stored at both room temperature and 150 C. Initial evaluation of the distribution of threshold voltage in a large sample set (800 devices) is presented. The magnitude of charge loss from exposure to electrostatic discharge and electromagnetic fields is measured and presented. Simulated data (and measured data as available) resultant from harsh-environment testing (neutron, heavy ion, EMP) is presented.

Data Retention↗
NASA NTRS2000

Quantitative analysis of charge injection and discharging of Si nanocrystals and arrays by electrostatic force microscopy

NASA requirements for computing and memory for microspacecraft emphasizes high density, low power, small size, and radiation hardness. The distributed nature of a storage elements in nanocrystal floating-gate memories leads to instrinsic fault tolerance and radiation-hardness. Nanocrystal-based memories also offer the possibility of a faster, lower power operation.

atomic↗