Search NASA⌕ Search

SEARCH · Search NASA

Results for “INTEGRATED CIRCUIT”

Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

Quote a phrase for an exact phrase match. Source license links do not imply unrestricted reuse.

At least 37 records · Page 2
All sourcesNASA NTRSDOE OSTI
DOE OSTI2024

Internship Work Report

I worked on two projects during my summer internship at Sandia. My official title was “Intern - Mission Tech Electrical Eng./Computer Eng.- R&D Undergraduate Summer.” I worked at the central location, which is Albuquerque, New Mexico. The department you are placed in at Sandia doesn’t always correspond to the people you will be working with. For example, I only directly worked with one person from my department this summer. On one of my projects, I worked with a diverse team of engineers from many different departments. On my other project, I mainly worked with two departments, as the project had two distinct parts. As mentioned earlier, I worked on two projects during my summer at Sandia. The first project focused on a lightweight embedded controller in an advanced FPGA System-on-Chip for radar signal processing applications. The term “controller” refers to a hardware device that directs the flow of data between two entities. An FPGA is a reprogrammable integrated circuit (as opposed to an integrated circuit with one purpose). An FPGA was used on this project so in order to protype various ideas for our System-on-Chip. My role on the project was to implement designs on the fabric of the FPGA and design a state machine (written in C) for the processor. My second project was also heavily involved with embedded systems but had a different application. It focused on using a Newton-Raphson control algorithm to stabilize an inverted pendulum using a novel microcontroller. The pendulum dynamics were derived, and it was successfully simulated in MATLAB. I worked on integrating the microcontroller with the inverted pendulum machinery, and converting the Newton-Raphson control algorithm from MATLAB into C. The inverted pendulum was successfully stabilized using a simple PID controller and industry-standard microcontroller. The project is still ongoing, and the team is gearing up for more tests using the novel Newton-Raphson control algorithm and novel microcontroller

42 ENGINEERING↗
DOE OSTI2025

Aligned carbon nanotubes for 1,000x improvement in computing (CRADA Final Report)

As part of the Cyclotron Road program, the Aligned Carbon team worked to improve and bring to market their technology to manufacture carbon nanotubes (CNTs) for integrated circuits. There are multiple applications which can benefit from the use of CNT based transistors in integrated circuits, including high performance computing, RF data transmission, and biosensing. Each of these applications faces a problem of poor starting CNT material to come to market. Aligned Carbon offers material with the highest ceiling of performance based around a fully aligned, uniform, on-wafer growth of CNTs and our proprietary purification process to remove metallic CNTs leaving only the semi-conducting ones behind. Further, Aligned Carbon has been guided by scalable manufacturing processes that will fit seamlessly into the integrated circuit foundry model of chip fabrication.

36 MATERIALS SCIENCE↗
DOE OSTI2024

Post-processing of phase change material in a zero-change commercial silicon photonic process

Integration of phase change material (PCM) with photonic integrated circuits can transform large-scale photonic systems by providing non-volatile control over phase and amplitude. The next generation of commercial silicon photonic processes can benefit from the addition of PCM to enable ultra-low power, highly reconfigurable, and compact photonic integrated circuits for large-scale applications. Despite all the advantages of PCM-based photonics, today’s commercial foundries do not provide them in their silicon photonic processes yet. We demonstrate the first-ever electrically programmable PCM device that is monolithically post-processed in a commercial foundry silicon photonics process using a few fabrication steps and coarse-resolution photolithography. These devices achieved 1.4 dB/μm of amplitude switching contrast using a thin layer of 12.5 nm GeSbTe in this work. We have also characterized the reconfiguration speed as well as repeatability of these devices over 20,000 switching cycles. Our solution enables non-volatile photonic VLSI systems that can be fabricated at low cost and high reliability in a commercial foundry process, paving the way for the development of non-volatile programmable photonic integrated circuits for a variety of emerging applications.

Optics↗
DOE OSTI2024

Tunable quantum emitters on large-scale foundry silicon photonics

Abstract Controlling large-scale many-body quantum systems at the level of single photons and single atomic systems is a central goal in quantum information science and technology. Intensive research and development has propelled foundry-based silicon-on-insulator photonic integrated circuits to a leading platform for large-scale optical control with individual mode programmability. However, integrating atomic quantum systems with single-emitter tunability remains an open challenge. Here, we overcome this barrier through the hybrid integration of multiple InAs/InP microchiplets containing high-brightness infrared semiconductor quantum dot single photon emitters into advanced silicon-on-insulator photonic integrated circuits fabricated in a 300 mm foundry process. With this platform, we achieve single-photon emission via resonance fluorescence and scalable emission wavelength tunability. The combined control of photonic and quantum systems opens the door to programmable quantum information processors manufactured in leading semiconductor foundries.

Larocque, Hugo (ORCID:000900095849780X)↗
DOE OSTI2026

Nanophotonic waveguide chip-to-world beam scanning

A seamless chip-to-world photonic interface enables broad advancements in optical ranging, display, communication, computation and quantum information science. The ideal solution enables two-dimensional scanning of a diffraction-limited beam from anywhere on a photonic integrated circuit to a large number of resolvable spots. Current beam-scanning technologies are limited by a fundamental trade-off: photonic-integrated-circuits with diffractive optics offer scalability but have poor mode quality, whereas inertially limited micromechanical scanners provide high-quality beams but lack scalable integration. Here we report a photonic ski-jump—a nanoscale waveguide monolithically integrated on a piezoelectric cantilever—to overcome these limitations. It passively curls ~90° out-of-plane within a less-than-0.1 mm 2 footprint, emits a submicrometre, broadband diffraction-limited beam, and exhibits kilohertz-rate mechanical resonances with quality factors of over 10,000. Fabricated in a volume complementary metal–oxide–semiconductor (CMOS) foundry, our device enables scalable two-dimensional beam scanning. Driven on-resonance at CMOS-level voltages, it achieves a footprint-adjusted spot rate of 68.6 mega spots s –1 mm–², exceeding state-of-the-art micro-electro-mechanical systems mirrors by more than 50-fold, which is sufficient for one million pixels at 100 Hz from an approximately 1.5 mm diameter footprint. We demonstrate full-colour image and video projection, and single-photon initialization and readout from silicon vacancy centres in diamond. Finally, by demonstrating uniformity across a 64 ski-jump array, we establish a pathway to achieving greater than one gigaspot resolution at kilohertz rates within a sub-5-cm-diameter footprint, creating a seamless optical pipeline between integrated photonic processors and the free-space world.

Displays↗
DOE OSTI2025

One-Step Transfer of Symmetric and Asymmetric Contacts for Large-Scale 2D Electronics and Optoelectronics

Two-dimensional (2D) semiconductors are highly promising candidates for thin-film transistor applications due to their scalability, transferability, atomic thickness, and relatively high carrier mobility. However, a substantial performance gap remains between individual devices based on single-crystalline 2D films and wafer-scale integrated circuits, primarily due to defects introduced during conventional fabrication processes. Here, we report a diamond-assisted electrode transfer technique for the van der Waals integration of wafer-scale prefabricated electrode arrays onto 2D materials, enabling scalable electronics and optoelectronics. Implemented on metal–organic chemical vapor deposition-grown monolayer molybdenum disulfide, this method forms ultraclean metal–semiconductor interfaces, yielding field-effect transistors with excellent ohmic contacts, a low contact resistance of 400 Ω·μm, and a Schottky barrier height of only 9 meV. Furthermore, we demonstrate a scalable transistor array on monolayer molybdenum disulfide with excellent device performance uniformity, achieving an average field-effect mobility of 30 cm 2 V –1 s –1 and an on/off current ratio exceeding 105. Additionally, high photocurrent and responsivity were demonstrated in the array devices, showing their potential for excellent image detection. We further demonstrate the versatility of this technique by fabricating a Schottky diode array through a single-step transfer of asymmetric electrodes─low work function aluminum and high work function gold─onto monolayer tungsten diselenide. This approach provides a clean, effective solution for contact engineering in 2D materials, offering a viable pathway toward wafer-scale, high-performance 2D electronics, optoelectronics, and integrated circuits.

2D electronics↗
DOE OSTI2025

Characterizing and Modeling the Influence of Geometry on the Performance of Superconducting Nanowire Cryotrons

The scaling of superconducting nanowire detectors to larger arrays is often limited by room-temperature-readout cabling. Cryogenic integrated circuits constructed from nanowire cryotrons, or nanocryotrons, can address this limitation by performing signal processing on chip. In this study, we characterize key performance metrics of the nanocryotron to elucidate its potential as a logical element in cryogenic integrated circuits and develop an electro-thermal model to connect material parameters with device performance. We find that the performance of the nanocryotron depends on the device geometry, and trade-offs are associated with optimizing the gain, jitter, and energy dissipation. Here, we demonstrate that nanocryotrons fabricated on niobium nitride can achieve a grey zone less than 210 nA wide for a 5 ns long input pulse corresponding to a maximum achievable gain of 48 dB, an energy dissipation of less than 20 aJ per operation, and a jitter of less than 60 ps.

Superconductor↗
DOE OSTI2026

Evaluation of an event-driven 3FI ASIC for spectroscopic X-ray detection with synchrotron radiation

The novel design and evaluation on the NSLS-II beamline of the 3FI application-specific integrated circuit (ASIC) bump-bonded to a simple, planar, 2D segmented silicon sensor are presented. The ASIC was developed for full-field fluorescence spectral X-ray imaging (3FI). It is a small-scale prototype that features a square array of 32 × 32 pixels, and the size of the pixels is 100 µm × 100 µm. The ASIC was implemented in a 65 nm CMOS integrated circuit fabrication process. Each pixel incorporates a charge-sensitive amplifier, a shaping filter, a discriminator, a peak detector and a sample-and-hold circuit, allowing detection of events and storage of signal amplitudes. The system operates in a frameless event-driven readout mode, outputting analog values for threshold-triggered events, allowing high-speed multi-element X-ray fluorescence data acquisition. The 3FI ASIC achieves per-channel spectrometric performance at a power consumption of only 200 µW per pixel, with nearly all dissipation confined to the analog front-end. An energy resolution is measured at the level of 308 eV full width at half-maximum (FWHM) at 8.04 keV (Cu Kα), and 138 eV FWHM at 3.69 keV (Ca Kα). This per-pixel capability makes the prototype suitable for in situ trace element microanalysis in biological and environmental studies. Moreover, the frameless architecture of the detector is designed to address limitations of conventional X-ray fluorescence microscopy, which typically requires mechanical scanning, by enabling continuous high-throughput data acquisition in future full-field implementations.

47 OTHER INSTRUMENTATION↗
DOE OSTI2025

Tale of Two Domains: Cyber - Physical

As devices and systems continue to modernize and adopt integrated circuits, the use of cyber technology to deploy an application is the expectation. This deployment through cyber assets brings new cyber risk and cybersecurity is the practice of managing this risk. Cyber-risk is constantly changing due to the speed of technology advancement and the changing quality of the adversary. Cyber-Informed Engineering (CIE) mitigates cyber-risk through engineering controls where as the traditional practice of cybersecurity mitigates cyber-risk through cybersecurity controls. By clearly defining the cyber-physical boundary, engineering controls and cybersecurity controls can clearly demonstrate their complementary nature to provide layered defenses and successfully mitigate cyber-risk through independent controls. In this paper, a layered model of device decomposition of the the cyber-physical boundary is presented to provide clarity where engineering controls are used to reduce cyber-risk within the physics, functional materials, electronic, or integrated circuit layers and where cybersecurity controls are used to reduce cyber-risk within the machine code and application layers. By implementing both traditional cybersecurity controls and engineering controls, a more holistic approach to cybersecurity is achieved in protecting modern devices and systems, as well as a clear awareness in identifying, documenting, and authorizing the system’s cybersecurity protection scheme is achieved.

42 - ENGINEERING↗
DOE OSTI2025

PtCoO 2 for Scaled Interconnects

Copper (Cu) interconnects are an increasingly important bottleneck in integrated circuits due to energy consumption and latency caused by the notable increase in Cu resistivity as dimensions decrease, primarily due to electron scattering at surfaces. Herein, the potential of a directional conductor, PtCoO 2 , which has a low bulk resistivity and a distinctive anisotropic structure that mitigates electron surface scattering is showcased. Thin films of PtCoO 2 of various thicknesses are synthesized by molecular beam epitaxy (MBE) coupled with a postdeposition annealing process and the superior quality of PtCoO 2 films is demonstrated by multiple characterization techniques. The thickness‐dependent resistivity curve illustrates that PtCoO 2 significantly outperforms effective Cu (Cu with TaN barriers) and Ru in resistivity below 20.0 nm with a more than 6x reduction compared to effective Cu below 6.0 nm, having a value of only 6.32 μΩ cm at 3.3 nm. It is determined that grain boundary scattering can still be improved for even lower resistivities in this material system through a combination of experiments and theoretical simulations. PtCoO 2 is therefore a highly promising alternative material for future interconnect technologies promising lower resistivities, better stability, and significant improvements in energy efficiency and latency for advanced integrated circuits.

Li, Yansong [Department of Electrical Engineering ↗
DOE OSTI2026

IMPACT 2025-2026 Internship Poster

At Sandia National Laboratories, I developed a C++ program that converts printed circuit boards(PCB) and integrated circuits(IC) design files to be compatible for computed tomography (CT) simulations through Monte Carlo methods.

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2024

Electric-Field-Driven Localization of Molecular Nanowires in Wafer-Scale Nanogap Electrodes

As integrated circuits continue to scale toward the atomic limit, bottom-up processes, such as epitaxial growth, have come to feature prominently in their fabrication. At the same time, chemistry has developed highly tunable molecular semiconductors that can perform the functions of ultimately scaled circuit components. Hybrid techniques that integrate programmable structures comprising molecular components into devices however are sorely lacking. Here we demonstrate a wafer-scale process that directs the localization of a conductive polymer, M w = 20 kg mol –1 polyaniline, from dilute solutions into 50 nm vertical nanogap device architectures using electric-field-driven self-assembly. The resulting metal–polymer–metal junctions were characterized by electron microscopy, Raman spectroscopy and transport measurements demonstrating that our technique is highly selective, assembling conductive polymers only in electrically activated nanogaps. Our results represent a step toward scalable hybrid nanoelectronics that seamlessly integrate established lithographic top-down fabrication with bottom-up synthesized molecular functional circuit components.

77 NANOSCIENCE AND NANOTECHNOLOGY↗
DOE OSTI2024

A 32-Channel Cryo-CMOS ASIC for SNSPD Biasing and Readout with Picosecond

Superconducting nanowire single-photon detectors (SNSPD) are a promising technology for particle detection. Although SNSPDs have demonstrated picosecond timing accuracy, scaling up large arrays has proved challenging. In this work, we introduce a 32-channel cryo-CMOS application-specific integrated circuit (ASIC) that can be tightly integrated with SNSPD arrays. The ASIC is designed to operate at a temperature of 4K and can perform up to 32 simultaneous timing measurements with a root-mean-square (RMS) accuracy of 8.0ps. The ASIC includes on-chip circuitry for externally biasing superconducting devices, low-noise amplifiers for reading superconducting devices, high-resolution time-to-digital converters (TDC) for time-tagging events, and serializers for transmitting data to room-temperature electronics. The ASIC is manufactured in a 22nm FDSOI process and occupies an area of 4.0mm x 1.0mm. The performance of the ASIC was verified using custom cryogenic device models internally developed for the 22nm SOI process. Measurement results will be presented at the conference.

Fredenburg, Jeff↗
DOE OSTI2024

A 32-Channel Cryo-CMOS ASIC for SNSPD Biasing and Readout with Picosecond Timing

Superconducting nanowire single-photon detectors (SNSPD) are a promising technology for particle detection. Although SNSPDs have demonstrated picosecond timing accuracy, scaling up large arrays has proved challenging. In this work, we introduce a 32-channel cryo-CMOS application-specifc integrated circuit (ASIC) that can be tightly integrated with SNSPD arrays. The ASIC is designed to operate at a temperature of 4K and can perform up to 32 simultaneous timing measurements with a root-mean-square (RMS) accuracy of 8.0ps. The ASIC includes on-chip circuitry for externally biasing superconducting devices, low-noise amplifers for reading superconducting devices, high-resolution time-to-digital converters (TDC) for time-tagging events, and serializers for transmitting data to room-temperature electronics. The ASIC is manufactured in a 22nm FDSOI process and occupies an area of 4.0mm x 1.0mm. The performance of the ASIC was verifed using custom cryogenic device models internally developed for the 22nm SOI process. Measurement results will be presented at the conference.

Fredenburg, Jeff↗
DOE OSTI2025

Signal propagation in reversible digital mechanics

Digital mechanics explores information processing through binary, mechanical circuits. This work demonstrates a flexural, mechanical integrated circuit (m-IC) that achieves reversible, non-reciprocal signal propagation through integrated AND logic and memory. Our approach exploits sequential bistable transitions with symmetric energy wells, tunable stiffness, impedance matching, and AND gate non-linearity, to enable signal propagation, repeatability, and reversibility. We present a generalized model of logic kinematics and energetics, validated experimentally, to study energy flows, quantify energetic limits, and identify operating regimes for reversible logic. Macro-scale experiments confirm propagation dynamics, and new fabrication methods extend the architecture to micro-scale devices. By achieving controlled, reversible signal transmission across interconnected logic and memory, this work establishes a scalable platform for robust mechanical computing and adaptive sensing.

Johnson, Hilary A. [Lawrence Livermore National La↗
DOE OSTI2026

TTDAQ: A Continuous Flow, Timing and Trigger DAQ System

Final Scientific/Technical Report for DOE Award DE-SC0019581, “TTDAQ: A Continuous Flow, Timing and Trigger DAQ System.” The report summarizes Telluric Labs’ Phase II STTR work developing silicon-photonic building blocks for a software-defined, continuous-flow, trigger-less data acquisition system for next-generation high-energy and nuclear-physics detectors. The project focused on radiation-hard photonic integrated circuits, remote optical illumination, dense wavelength-division multiplexing, and a differential microring-resonator transceiver architecture designed to improve high-speed optical link stability and bandwidth. The report describes project objectives, technical accomplishments, AIM Photonics tape-outs, bench characterization, radiation-hardness testing, deferred integration work, and potential applications beyond physics readout.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗
DOE OSTI2024

Toward an integrated multi-gigahertz ionizing particle diagnostic

Needs arising at both current and future accelerator facilities call for the development of radiation-hardened position-sensing diagnostics that can operate with multi-GHz repetition rates. Such instruments are likely to also have applications in the diagnosis of rapid plasma behavior. Here, building on the recent work of our Advanced Accelerator Diagnostics Collaboration, we are exploring the development of integrated multi-GHz ionizing particle detection systems based on chemical-vapor deposition diamond sensors, with the initial goal of producing a quadrant detector that can determine the intensity and centroid position of a particle beam at a repetition rate between 5 and 10 GHz. Results from our initial high-speed characterization work are presented, including those from a single-channel sensor with a GHz response. Approaches to achieving multi-GHz (5–10 GHz) rate capability, including the design of a dedicated Application Specific Integrated Circuit and the use of 3D RF-solver computer aided design software, are presented and discussed in more detail. 3D RF simulations suggest clean pulses of duration less than 250 ps (FWHM less than 125 ps) can be achieved with the approaches developed by this work.

43 PARTICLE ACCELERATORS↗
DOE OSTI2026

On-chip probabilistic inference for charged-particle tracking at the sensor edge

Modern scientific instruments operate under increasingly extreme constraints on bandwidth, latency, and power. Inference at the sensor edge determines experimental data collection efficiency by deciding which information to save for further analysis. Particle tracking detectors at the Large Hadron Collider exemplify this challenge: pixelated silicon sensors generate rich spatiotemporal ionization patterns, yet most of this information is discarded due to data-rate limitations. Concurrently, advancements in co-design tools provide rapid turn-around for incorporating machine learning into application-specific integrated circuits, motivating designs for particle detectors with new integrated technologies. We demonstrate that neural networks embedded in the front-end electronics can infer charged-particle kinematic parameters from a single silicon layer. We regress hit positions and incident angles with calibrated uncertainties, while satisfying stringent constraints on numerical precision, latency, and silicon area. Our results establish a path toward probabilistic inference directly at the edge, opening new opportunities for intelligent sensing in high-rate scientific instruments.

Das, Arghya Ranjan [Purdue U.] (ORCID:000000018451↗