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DOE OSTI2025

Implementation of ISO 15118-202 messages within Everest EV Charging Open Source Framework [SWR-25-56]

This software implements the messages defined in the ISO 15118-202 standard within the Everest EV Charging open source framework. The protocol and messages defined in the ISO 15118-202 standard enable the exchange of additional information which is not available for exchange within the currently deployed EV/EVSE communications protocols. This information includes co-identification parameters, error message exchange and more. This fork of the everest-core repository adds a prototype of the Extensible Supply Equipment Communication Controller (SECC) Discovery Protocol (ESDP) implemented based on a draft of the ISO 15118-202 standard. This is achieved through additions and modifications to the EvseV2G module. The implementation provides a demonstration of the ESDP messages, encoding and decoding but does not include a full integration within the Everest framework. Much of the information being sent over ESDP in this implementation is set statically for the sake of demonstrating the protocol itself. This fork of the ext-switchev-iso15118 repository adds a prototype of the Extensible Supply Equipment Communication Controller (SECC) Discovery Protocol (ESDP) implemented based on a draft of the ISO 15118-202 standard. The implementation provides a demonstration of the ESDP messages, encoding and decoding but does not include a full integration within the Everest framework. Much of the information being sent over ESDP in this implementation is set statically for the sake of demonstrating the protocol itself. This fork adds the ESDP features for only the EVCC controller because that is the only portion that is utilized in the everest Software-in-the-Loop.

Watt, Ed [National Renewable Energy Laboratory (NR↗

NASA NTRS1994

Toward fidelity between specification and implementation

This paper describes the methods used to specify and implement a complex communications protocol that provides reliable delivery of data in multicast-capable, packet-switching telecommunication networks. The protocol, called the Reliable Multicasting Protocol (RMP), was developed incrementally by two complementary teams using a combination of formal and informal techniques in an attempt to ensure the correctness of the protocol implementation. The first team, called the Design team, initially specified protocol requirements using a variant of SCR requirements tables and implemented a prototype solution. The second team, called the V&V team, developed a state model based on the requirements tables and derived test cases from these tables to exercise the implementation. In a series of iterative steps, the Design team added new functionality to the implementation while the V&V team kept the state model in fidelity with the implementation through testing. Test cases derived from state transition paths in the formal model formed the dialogue between teams during development and served as the vehicles for keeping the model and implementation in fidelity with each other. This paper describes our experiences in developing our process model, details of our approach, and some example problems found during the development of RMP.

Callahan, John R.↗

NASA NTRS2002

Implementation of Adaptive Digital Controllers on Programmable Logic Devices

Much has been made of the capabilities of FPGA's (Field Programmable Gate Arrays) in the hardware implementation of fast digital signal processing (DSP) functions. Such capability also makes and FPGA a suitable platform for the digital implementation of closed loop controllers. There are myriad advantages to utilizing an FPGA for discrete-time control functions which include the capability for reconfiguration when SRAM- based FPGA's are employed, fast parallel implementation of multiple control loops and implementations that can meet space level radiation tolerance in a compact form-factor. Other researchers have presented the notion that a second order digital filter with proportional-integral-derivative (PID) control functionality can be implemented in an FPGA. At Marshall Space Flight Center, the Control Electronics Group has been studying adaptive discrete-time control of motor driven actuator systems using digital signal processor (DSF) devices. Our goal is to create a fully digital, flight ready controller design that utilizes an FPGA for implementation of signal conditioning for control feedback signals, generation of commands to the controlled system, and hardware insertion of adaptive control algorithm approaches. While small form factor, commercial DSP devices are now available with event capture, data conversion, pulse width modulated outputs and communication peripherals, these devices are not currently available in designs and packages which meet space level radiation requirements. Meeting our goals requires alternative compact implementation of such functionality to withstand the harsh environment encountered on spacecraft. Radiation tolerant FPGA's are a feasible option for reaching these goals.

Gwaltney, David A.↗

NASA NTRS2011

Interplanetary Overlay Network Bundle Protocol Implementation

The Interplanetary Overlay Network (ION) system's BP package, an implementation of the Delay-Tolerant Networking (DTN) Bundle Protocol (BP) and supporting services, has been specifically designed to be suitable for use on deep-space robotic vehicles. Although the ION BP implementation is unique in its use of zero-copy objects for high performance, and in its use of resource-sensitive rate control, it is fully interoperable with other implementations of the BP specification (Internet RFC 5050). The ION BP implementation is built using the same software infrastructure that underlies the implementation of the CCSDS (Consultative Committee for Space Data Systems) File Delivery Protocol (CFDP) built into the flight software of Deep Impact. It is designed to minimize resource consumption, while maximizing operational robustness. For example, no dynamic allocation of system memory is required. Like all the other ION packages, ION's BP implementation is designed to port readily between Linux and Solaris (for easy development and for ground system operations) and VxWorks (for flight systems operations). The exact same source code is exercised in both environments. Initially included in the ION BP implementations are the following: libraries of functions used in constructing bundle forwarders and convergence-layer (CL) input and output adapters; a simple prototype bundle forwarder and associated CL adapters designed to run over an IPbased local area network; administrative tools for managing a simple DTN infrastructure built from these components; a background daemon process that silently destroys bundles whose time-to-live intervals have expired; a library of functions exposed to applications, enabling them to issue and receive data encapsulated in DTN bundles; and some simple applications that can be used for system checkout and benchmarking.

Burleigh, Scott C.↗

NASA NTRS2018

Implementation of J-A Methodology Elastic-Plastic Crack Instability Analysis Capability into the WARP-3D Code

Characterization of the near crack-tip stress/strain fields is the foundation of fracture mechanics. The description of the near tip stress field and the prediction of when fracture occurs is well established for brittle materials that exhibit linear elastic behavior. However, in ductile materials or conditions that violate linear elastic assumptions (Aluminum alloys, Al 2024-T3, Al 2024- T351 etc.), the elastic-plastic crack-tip stress fields are characterized by the Hutchison-Rice-Rosengren (HRR) field. The J-integral is commonly used to characterize amplitude of the HRR field under elastic-plastic conditions. The J-integral has been demonstrated for crack-tip fields that are under high constraint conditions (i.e., small-scale plasticity where the J-dominance is maintained). However, as the external load increases, yielding changes from small- to largescale plasticity and usually a loss of constraint (i.e., reduction in the triaxial stress field along the crack front). The loss of constraint leads to the deviation of the crack-tip stress fields from that given by the HRR field. Hence, the J-dominance will be gradually lost and additional parameter(s) are required to quantify the crack-tip stress fields and predict fracture behavior. The assessment objectives were to: 1) implement a two-parameter (i.e., J-A) fracture criterion into an elastic-plastic three-dimensional (3D) finite element analysis (FEA), 2) validate the implementation by comparison with the A parameter from literature data, 3) conduct material characterization tests to quantify the material behavior and provide fracture data for validation of the J-A fracture criteria, and (4) perform evaluations to establish if the J-A criteria can be used to predict fracture in a ductile metallic material (e.g., aluminum alloys). The A parameter in these criteria is the second parameter in a three-term elastic-plastic asymptotic expansion of the neartip stress behavior. A series of extensive FEAs were performed using WARP3D software package to obtain solutions for the A parameter for different specimen configurations. The methodology needed for the estimation of the A parameter in the asymptotic expansion was developed and implemented using Matlab®. A user material (UMAT) routine was used to model the material stress-strain response using a Ramberg-Osgood power law with a hardening exponent (n) and a material coefficient (alpha). This UMAT routine was successfully implemented in WARP3D software and validated through comparison with the experimental data. Three configurations were extracted from published results: 1) center cracked plate (CCP), 2) single edge-cracked plate (SECP), and 3) double edge-cracked plate (DECP). These configurations and four other configurations (three-hole tension (THT)), three-point bend (3PTB), three-hole compact tension (3PCT), and compact tension (CT)) were analyzed to verify the methodology that was developed and implemented into WARP3D. Solutions of the A parameter were obtained for remote tension loading conditions that started with small-scale yielding and continued into the large-scale plasticity regime. The results indicate that the methodology developed can be used to calculate the elastic-plastic J-A parameters for test specimens with a range of crack geometries, material strain hardening behaviors, and loading conditions. The J-A parameters were implemented as fracture criteria and used to predict the test results. For comparison, other fracture criteria were used to predict the same test results. Major findings include: The A constraint parameter A varies with specimen type and applied load thus accurate determination is crucial in predicting the failure load, and the A parameter is asymptotic as the failure load is approached, making an accurate determination difficult (i.e., small differences in the A parameter can cause large variations in failure load) for materials exhibiting elastic-plastic behavior. The failure predictions from J-A methodology were more accurate than the traditionally used KC and J methods, and have comparable scatter to that observed when using the crack-tip opening angle (CTOA) method. However, the J-A methodology requires considerable effort (expertise level and labor) to implement and to evaluate the A parameter for different specimen types and materials, or to apply this methodology to part-through crack (e.g., 3D problems) structural applications.

Hamm, Kenneth R., Jr.↗

NASA NTRSDate not supplied

Implementation of Human Systems Integration Technical and Management Process for the Lunar Gateway Program

NASA recognizes Human Systems Integration (HSI) as part of the overall systems engineering and acquisition strategy for space systems. The Lunar Gateway Program is implementing HSI technical and management process across the lifecycle of the mission, as required by NPR 7123.1C NASA Systems Engineering Processes and Requirements, and led by the Gateway HSI team as required by NPR 8705.2C Human-Rating Requirements for Space Systems, now HEOMD-003 Crewed Deep Space Systems Human Rating Certification Requirements and Standards for NASA Missions. NASA has been using HSI principles for many years and has applied them to many of its previous human spaceflight Programs. As NASA returns to the Moon in a more sustainable manner, the Gateway Program is maturing the application of HSI by implementing it more visibly as part of Artemis, with guidance from the NASA/SP-20210010952 NASA HSI Handbook. This paper discusses how HSI is being implemented in the Gateway Program, challenges faced with its implementation during the development phase, and strategies/approaches used to overcome those. The paper also covers HSI implementation for flight systems, vehicle processing, and interfaces across the six identified NASA HSI Domains: human factors engineering, operations, safety, training, maintainability and supportability, habitability and environment. The goal is to provide an overview of the implementation process of HSI in the Gateway Program as an example for other Programs/Projects/Missionsthat are looking to implement HSI.

Jackelynne Silva-Martinez↗

NASA NTRSDate not supplied

Implementing JEDI into NASA GMAO’s Real Time Production Suite

NASA’s Global Modeling and Assimilation Office (GMAO) has prepared their first production system involving the Joint Effort for Data assimilation Integration (JEDI) framework. In this system the central analysis, that drives the deterministic forecast, will be provided using JEDI. This talk outlines the phased approach to implementing JEDI into production that GMAO has designed, and how this approach will allow for a careful analysis of the system against the existing data assimilation framework (GSI). In the first phase of implementation the existing data assimilation system will perform certain actions that are still under development in JEDI. These include thinning the observations and producing satellite bias correction coefficients. JEDI is hooked up to the existing workflow so a single line switch can activate whether the existing or JEDI-based analysis is cycled. Outside of the monumental effort to construct JEDI that is ongoing at the Joint Center for Satellite Data Assimilation (JCSDA), GMAO have undertaken two areas of considerable effort. The talk will describe these efforts and highlight the main challenges that have been encountered. The first area of work is to implement the background error model from the existing data assimilation system into JEDI. The second is to validate the observing system in JEDI against the one in GSI, which has involved several new features being added to the observation operators in JEDI. While the longer-term plans involve trying to improve on the GSI in these two areas, GMAO is keen to have JEDI start from a trusted baseline. This is also key to implementing JEDI quickly so other priorities, such as increasing the number of model levels, can be easily worked on in parallel. GMAO is actively working on a framework to shepherd in the next generation coupled data assimilation system and model. As JEDI is implemented for the first time the plan is to ambitiously cycle through implementations, frequently bringing JEDI features to production. Details of these plans will be given in the talk and we will highlight key implementation and product milestones that we hope to achieve, as well as touch on the development environment that we will use to support frequent refreshing of the production system.

JEDI↗

NASA NTRSDate not supplied

Human Systems Integration (HSI) Framework and Training - Shifting the View of HSI for Better Implementation

The Implementation of Human Systems Integration (HSI) presents challenges within the acquisition community for two reasons. The first is that misconceptions of HSI still exist, with many Program Managers (PMs) and leadership uncertain of the value or where to begin. The second is due to an unbalanced approach to HSI in its own framework. These implementation challenges lead to barriers in the early prevention of mishaps. Understanding HSI practices and how they should be implemented in the Acquisition Product Life Cycle (PLC) has been a challenge across the government, leaving the value of HSI unknown and misunderstood with Program Managers. In the case for many acquisition programs, HSI is not implemented in early design, losing the perspective on human capabilities and limitations, creating impacts on human-centered design. Expectations in human performance are not clearly set and operations are baselined with no margin for changes in technology and processes that will affect system performance. The HSI framework addresses total system performance holistically using collaboration as the primary tool. The goal is to create a system with efficiencies while minimizing risk to the operators, maintainers, and support personnel, as well as any collateral personnel and systems. To accomplish this, HSI should be implemented as part of preemptive measures to minimize potential human error and mishaps during the operation phase. Investigative and assessment tools exist that consider events, issues, and other outside influences of a system that may not fall under the current construct of the HSI domains, leaving gaps in early HSI implementation and affecting the prevention of human errors and mishaps. This presentation will outline what NASA HSI is doing to support Early HSI implementation and Operational Performance shifts that affect human performance.

Anthony T Thomas↗

DOE OSTI2025

Formulation and Experimental Validation of an Agricultural Implement-Only MPR System for Maximum Compatibility with Existing Agricultural Tractors

Tightening emissions regulations and rising fuel costs have driven a desire across many industries for more efficient actuation systems. This is particularly true of the agricultural sector. An extremely common arrangement in this sector is the tractor and implement pairing, in which actuators on an implement are powered by a hydraulic supply system on the towing tractor. This arrangement complicates the development of energy efficient hydraulic systems, as many new system designs require modification of both machines to reap efficiency benefits. Past work by the authors’ team has demonstrated great potentials for Multi-Pressure-Rail (MPR) technology involving both the tractor and implement subsystems. However, applicability of this MPR technology in a more realistic scenario where only one vehicle is equipped with such technology was not addressed. This work proposes an implementation of the MPR technology to an agricultural planter that allows significant savings, while only modifying the implement machine. This is done by manipulating the load sense network of a stock tractor to set system pressures to those required by the MPR system. This greatly reduces the barrier to implementation of MPR technology in agriculture. The work begins by outlining the reference machine for the system, then reviews the MPR system working principle. After this, the proposed expansion to the MPR concept is laid out and applied to the reference system. Finally, experimental validation is carried out, demonstrating up to a 35% reduction in system power consumption when paired with a state of the art, double-LS System tractor, and 15% with a single-LS System tractor.

24 POWER TRANSMISSION AND DISTRIBUTION↗

NASA NTRS1990

Validation environment for AIPS/ALS: Implementation and results

The work is presented which was performed in porting the Fault Injection-based Automated Testing (FIAT) and Programming and Instrumentation Environments (PIE) validation tools, to the Advanced Information Processing System (AIPS) in the context of the Ada Language System (ALS) application, as well as an initial fault free validation of the available AIPS system. The PIE components implemented on AIPS provide the monitoring mechanisms required for validation. These mechanisms represent a substantial portion of the FIAT system. Moreover, these are required for the implementation of the FIAT environment on AIPS. Using these components, an initial fault free validation of the AIPS system was performed. The implementation is described of the FIAT/PIE system, configured for fault free validation of the AIPS fault tolerant computer system. The PIE components were modified to support the Ada language. A special purpose AIPS/Ada runtime monitoring and data collection was implemented. A number of initial Ada programs running on the PIE/AIPS system were implemented. The instrumentation of the Ada programs was accomplished automatically inside the PIE programming environment. PIE's on-line graphical views show vividly and accurately the performance characteristics of Ada programs, AIPS kernel and the application's interaction with the AIPS kernel. The data collection mechanisms were written in a high level language, Ada, and provide a high degree of flexibility for implementation under various system conditions.

Segall, Zary↗

NASA NTRS2000

Ames Research Center FY 2000 Implementation Plan: Leading Technology into the New Millennium

This document presents the implementation plan for Ames Research Center (ARC) within the overall framework of the NASA Strategic Plan. It describes how ARC intends to implement its Center of Excellence responsibilities, Agency assigned missions, Agency and Enterprise lead programs, and other roles in support of NASA's vision and mission. All Federal agencies are required by the 1993 Government Performance and Results Act to implement a long-term strategic planning process that includes measurable outcomes and strict accountability. At NASA, this planning process is shaped by the Space Act of 1958, annual appropriations, and other external mandates, as well as by customer requirements. The resulting Strategic Plan sets the overall architecture for what we do, identifies who our customers are, and directs where we are going and why. The Strategic Plan is the basis upon which decisions regarding program implementation and resource deployment are made. Whereas the strategic planning process examines the long-term direction of the organization and identifies a specific set of goals, the implementation planning process examines the detailed performance of the organization and allocates resources toward meeting these goals. It is the purpose of this implementation document to provide the connection between the NASA Strategic Plan and the specific programs and support functions that ARC employees perform. This connection flows from the NASA Strategic Plan, through the various Strategic Enterprise plans to the ARC Center of Excellence, primary missions, Lead Center programs, program support responsibilities, and ultimately, to the role of the individual ARC employee.

Source record↗

NASA NTRS2001

Improved Equivalent Linearization Implementations Using Nonlinear Stiffness Evaluation

This report documents two new implementations of equivalent linearization for solving geometrically nonlinear random vibration problems of complicated structures. The implementations are given the acronym ELSTEP, for "Equivalent Linearization using a STiffness Evaluation Procedure." Both implementations of ELSTEP are fundamentally the same in that they use a novel nonlinear stiffness evaluation procedure to numerically compute otherwise inaccessible nonlinear stiffness terms from commercial finite element programs. The commercial finite element program MSC/NASTRAN (NASTRAN) was chosen as the core of ELSTEP. The FORTRAN implementation calculates the nonlinear stiffness terms and performs the equivalent linearization analysis outside of NASTRAN. The Direct Matrix Abstraction Program (DMAP) implementation performs these operations within NASTRAN. Both provide nearly identical results. Within each implementation, two error minimization approaches for the equivalent linearization procedure are available - force and strain energy error minimization. Sample results for a simply supported rectangular plate are included to illustrate the analysis procedure.

Rizzi, Stephen A.↗

NASA NTRS2001

Pre-Hardware Optimization of Spacecraft Image Processing Software Algorithms and Hardware Implementation

Spacecraft telemetry rates have steadily increased over the last decade presenting a problem for real-time processing by ground facilities. This paper proposes a solution to a related problem for the Geostationary Operational Environmental Spacecraft (GOES-8) image processing application. Although large super-computer facilities are the obvious heritage solution, they are very costly, making it imperative to seek a feasible alternative engineering solution at a fraction of the cost. The solution is based on a Personal Computer (PC) platform and synergy of optimized software algorithms and re-configurable computing hardware technologies, such as Field Programmable Gate Arrays (FPGA) and Digital Signal Processing (DSP). It has been shown in [1] and [2] that this configuration can provide superior inexpensive performance for a chosen application on the ground station or on-board a spacecraft. However, since this technology is still maturing, intensive pre-hardware steps are necessary to achieve the benefits of hardware implementation. This paper describes these steps for the GOES-8 application, a software project developed using Interactive Data Language (IDL) (Trademark of Research Systems, Inc.) on a Workstation/UNIX platform. The solution involves converting the application to a PC/Windows/RC platform, selected mainly by the availability of low cost, adaptable high-speed RC hardware. In order for the hybrid system to run, the IDL software was modified to account for platform differences. It was interesting to examine the gains and losses in performance on the new platform, as well as unexpected observations before implementing hardware. After substantial pre-hardware optimization steps, the necessity of hardware implementation for bottleneck code in the PC environment became evident and solvable beginning with the methodology described in [1], [2], and implementing a novel methodology for this specific application [6]. The PC-RC interface bandwidth problem for the class of applications with moderate input-output data rates but large intermediate multi-thread data streams has been addressed and mitigated. This opens a new class of satellite image processing applications for bottleneck problems solution using RC technologies. The issue of a science algorithm level of abstraction necessary for RC hardware implementation is also described. Selected Matlab functions already implemented in hardware were investigated for their direct applicability to the GOES-8 application with the intent to create a library of Matlab and IDL RC functions for ongoing work. A complete class of spacecraft image processing applications using embedded re-configurable computing technology to meet real-time requirements, including performance results and comparison with the existing system, is described in this paper.

Kizhner, Semion↗

NASA NTRS2006

Implementing Scientific Simulation Codes Highly Tailored for Vector Architectures Using Custom Configurable Computing Machines

The motivation for this work comes from an observation that amidst the push for Massively Parallel (MP) solutions to high-end computing problems such as numerical physical simulations, large amounts of legacy code exist that are highly optimized for vector supercomputers. Because re-hosting legacy code often requires a complete re-write of the original code, which can be a very long and expensive effort, this work examines the potential to exploit reconfigurable computing machines in place of a vector supercomputer to implement an essentially unmodified legacy source code. Custom and reconfigurable computing resources could be used to emulate an original application's target platform to the extent required to achieve high performance. To arrive at an architecture that delivers the desired performance subject to limited resources involves solving a multi-variable optimization problem with constraints. Prior research in the area of reconfigurable computing has demonstrated that designing an optimum hardware implementation of a given application under hardware resource constraints is an NP-complete problem. The premise of the approach is that the general issue of applying reconfigurable computing resources to the implementation of an application, maximizing the performance of the computation subject to physical resource constraints, can be made a tractable problem by assuming a computational paradigm, such as vector processing. This research contributes a formulation of the problem and a methodology to design a reconfigurable vector processing implementation of a given application that satisfies a performance metric. A generic, parametric, architectural framework for vector processing implemented in reconfigurable logic is developed as a target for a scheduling/mapping algorithm that maps an input computation to a given instance of the architecture. This algorithm is integrated with an optimization framework to arrive at a specification of the architecture parameters that attempts to minimize execution time, while staying within resource constraints. The flexibility of using a custom reconfigurable implementation is exploited in a unique manner to leverage the lessons learned in vector supercomputer development. The vector processing framework is tailored to the application, with variable parameters that are fixed in traditional vector processing. Benchmark data that demonstrates the functionality and utility of the approach is presented. The benchmark data includes an identified bottleneck in a real case study example vector code, the NASA Langley Terminal Area Simulation System (TASS) application.

Rutishauser, David↗

NASA NTRS2006

Integrated System Health Management (ISHM): Systematic Capability Implementation

This paper provides a credible approach for implementation of ISHM capability in any system. The requirements and processes to implement ISHM capability are unique in that a credible capability is initially implemented at a low level, and it evolves to achieve higher levels by incremental augmentation. In contrast, typical capabilities, such as thrust of an engine, are implemented once at full Functional Capability Level (FCL), which is not designed to change during the life of the product. The approach will describe core ingredients (e.g. technologies, architectures, etc.) and when and how ISHM capabilities may be implemented. A specific architecture/taxonomy/ontology will be described, as well as a prototype software environment that supports development of ISHM capability. This paper will address implementation of system-wide ISHM as a core capability, and ISHM for specific subsystems as expansions and evolution, but always focusing on achieving an integrated capability.

Figueroa, Fernando↗

NASA NTRS2009

Economical Implementation of a Filter Engine in an FPGA

A logic design has been conceived for a field-programmable gate array (FPGA) that would implement a complex system of multiple digital state-space filters. The main innovative aspect of this design lies in providing for reuse of parts of the FPGA hardware to perform different parts of the filter computations at different times, in such a manner as to enable the timely performance of all required computations in the face of limitations on available FPGA hardware resources. The implementation of the digital state-space filter involves matrix vector multiplications, which, in the absence of the present innovation, would ordinarily necessitate some multiplexing of vector elements and/or routing of data flows along multiple paths. The design concept calls for implementing vector registers as shift registers to simplify operand access to multipliers and accumulators, obviating both multiplexing and routing of data along multiple paths. Each vector register would be reused for different parts of a calculation. Outputs would always be drawn from the same register, and inputs would always be loaded into the same register. A simple state machine would control each filter. The output of a given filter would be passed to the next filter, accompanied by a "valid" signal, which would start the state machine of the next filter. Multiple filter modules would share a multiplication/accumulation arithmetic unit. The filter computations would be timed by use of a clock having a frequency high enough, relative to the input and output data rate, to provide enough cycles for matrix and vector arithmetic operations. This design concept could prove beneficial in numerous applications in which digital filters are used and/or vectors are multiplied by coefficient matrices. Examples of such applications include general signal processing, filtering of signals in control systems, processing of geophysical measurements, and medical imaging. For these and other applications, it could be advantageous to combine compact FPGA digital filter implementations with other application-specific logic implementations on single integrated-circuit chips. An FPGA could readily be tailored to implement a variety of filters because the filter coefficients would be loaded into memory at startup.

Kowalski, James E.↗

NASA NTRS2009

Integrated System Health Management: Foundational Concepts, Approach, and Implementation.

Implementation of integrated system health management (ISHM) capability is fundamentally linked to the management of data, information, and knowledge (DIaK) with the purposeful objective of determining the health of a system. It is akin to having a team of experts who are all individually and collectively observing and analyzing a complex system, and communicating effectively with each other in order to arrive to an accurate and reliable assessment of its health. We present concepts, procedures, and a specific approach as a foundation for implementing a credible ISHM capability. The capability stresses integration of DIaK from all elements of a system. The intent is also to make possible implementation of on-board ISHM capability, in contrast to a remote capability. The information presented is the result of many years of research, development, and maturation of technologies, and of prototype implementations in operational systems (rocket engine test facilities). The paper will address the following topics: 1. ISHM Model of a system 2. Detection of anomaly indicators. 3. Determination and confirmation of anomalies. 4. Diagnostic of causes and determination of effects. 5. Consistency checking cycle. 6. Management of health information 7. User Interfaces 8. Example implementation ISHM has been defined from many perspectives. We define it as a capability that might be achieved by various approaches. We describe a specific approach that has been matured throughout many years of development, and pilot implementations. ISHM is a capability that is achieved by integrating data, information, and knowledge (DIaK) that might be distributed throughout the system elements (which inherently implies capability to manage DIaK associated with distributed sub-systems). DIaK must be available to any element of a system at the right time and in accordance with a meaningful context. ISHM Functional Capability Level (FCL) is measured by how well a system performs the following functions: (1) detect anomalies, (2) diagnose causes, (3) predict future anomalies/failures, and (4) provide the user with an integrated awareness about the condition of every element in the system and guide user decisions.

Figueroa, Fernando↗

NASA NTRS2009

Hardware Implementation of a Bilateral Subtraction Filter

A bilateral subtraction filter has been implemented as a hardware module in the form of a field-programmable gate array (FPGA). In general, a bilateral subtraction filter is a key subsystem of a high-quality stereoscopic machine vision system that utilizes images that are large and/or dense. Bilateral subtraction filters have been implemented in software on general-purpose computers, but the processing speeds attainable in this way even on computers containing the fastest processors are insufficient for real-time applications. The present FPGA bilateral subtraction filter is intended to accelerate processing to real-time speed and to be a prototype of a link in a stereoscopic-machine- vision processing chain, now under development, that would process large and/or dense images in real time and would be implemented in an FPGA. In terms that are necessarily oversimplified for the sake of brevity, a bilateral subtraction filter is a smoothing, edge-preserving filter for suppressing low-frequency noise. The filter operation amounts to replacing the value for each pixel with a weighted average of the values of that pixel and the neighboring pixels in a predefined neighborhood or window (e.g., a 9 9 window). The filter weights depend partly on pixel values and partly on the window size. The present FPGA implementation of a bilateral subtraction filter utilizes a 9 9 window. This implementation was designed to take advantage of the ability to do many of the component computations in parallel pipelines to enable processing of image data at the rate at which they are generated. The filter can be considered to be divided into the following parts (see figure): a) An image pixel pipeline with a 9 9- pixel window generator, b) An array of processing elements; c) An adder tree; d) A smoothing-and-delaying unit; and e) A subtraction unit. After each 9 9 window is created, the affected pixel data are fed to the processing elements. Each processing element is fed the pixel value for its position in the window as well as the pixel value for the central pixel of the window. The absolute difference between these two pixel values is calculated and used as an address in a lookup table. Each processing element has a lookup table, unique for its position in the window, containing the weight coefficients for the Gaussian function for that position. The pixel value is multiplied by the weight, and the outputs of the processing element are the weight and pixel-value weight product. The products and weights are fed to the adder tree. The sum of the products and the sum of the weights are fed to the divider, which computes the sum of products the sum of weights. The output of the divider is denoted the bilateral smoothed image. The smoothing function is a simple weighted average computed over a 3 3 subwindow centered in the 9 9 window. After smoothing, the image is delayed by an additional amount of time needed to match the processing time for computing the bilateral smoothed image. The bilateral smoothed image is then subtracted from the 3 3 smoothed image to produce the final output. The prototype filter as implemented in a commercially available FPGA processes one pixel per clock cycle. Operation at a clock speed of 66 MHz has been demonstrated, and results of a static timing analysis have been interpreted as suggesting that the clock speed could be increased to as much as 100 MHz.

Huertas, Andres↗