Search NASA⌕ Search

SEARCH · Search NASA

Results for “JFETs”

Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

Quote a phrase for an exact phrase match. Source license links do not imply unrestricted reuse.

At least 37 records · Page 2
All sourcesNASA NTRSDOE OSTI
NASA NTRS2009

Characterization of 6H-SiC JFET Integrated Circuits Over A Broad Temperature Range from -150 C to +500 C

The NASA Glenn Research Center has previously reported prolonged stable operation of simple prototype 6H-SiC JFET integrated circuits (logic gates and amplifier stages) for thousands of hours at +500 C. This paper experimentally investigates the ability of these 6H-SiC JFET devices and integrated circuits to also function at cold temperatures expected to arise in some envisioned applications. Prototype logic gate ICs experimentally demonstrated good functionality down to -125 C without changing circuit input voltages. Cascaded operation of gates at cold temperatures was verified by externally wiring gates together to form a 3-stage ring oscillator. While logic gate output voltages exhibited little change across the broad temperature range from -125 C to +500 C, the change in operating frequency and power consumption of these non-optimized logic gates as a function of temperature was much larger and tracked JFET channel conduction properties.

Neudeck, Philip G.↗
NASA NTRS2010

Low Earth Orbit Space Environment Testing of Extreme Temperature 6H-SiC JFETs on the International Space Station

This paper reports long-term electrical results from two 6H-SiC junction field effect transistors (JFETs) presently being tested in Low Earth Orbit (LEO) space environment on the outside of the International Space Station (ISS). The JFETs have demonstrated excellent functionality and stability through 4600 hours of LEO space deployment. Observed changes in measured device characteristics tracked changes in measured temperature, consistent with wellknown JFET temperature-dependent device physics.

Neudeck, Philip G.↗
NASA NTRS2014

Electrical Characterization of 4H-SiC JFET Wafer: DC Parameter Variations for Extreme Temperature IC Design

This work reports DC electrical characterization of a 76 mm diameter 4H-SiC JFET test wafer fabricated as part of NASA's on-going efforts to realize medium-scale ICs with prolonged and stable circuit operation at temperatures as high as 500 degC. In particular, these measurements provide quantitative parameter ranges for use in JFET IC design and simulation. Larger than expected parameter variations were observed both as a function of position across the wafer as well as a function of ambient testing temperature from 23 degC to 500 degC.

Microelectronics↗
NASA NTRS2018

Yearlong 500 C Operational Demonstration of Up-Scaled 4H-SiC JFET Integrated Circuits

This work describes recent progress in the design, processing, and testing of significantly up-scaled 500 C durable 4H-SiC junction field effect transistor (JFET) integrated circuit (IC) technology with two-level interconnect undergoing development at NASA Glenn Research Center. For the first time, stable electrical operation of semiconductor ICs for over one year at 500 C in air atmosphere is reported. These groundbreaking durability results were attained on two-level interconnect JFET demonstration ICs with 175 or more transistors on each chip. This corresponds to a more than 7-fold increase in 500 C-durable circuit complexity from the 24 transistor ring oscillator ICs reported at HiTEC 2016. These results advance the technology foundation for realizing long-term durable 500 C ICs with increased functional capability for combustion engine sensing and control, planetary exploration, deep-well drilling monitoring, and other harsh-environment applications.

Silicon carbides↗
NASA NTRS2018

Room Temperature Total-Ionizing Dose Testing of Glenn Research Center (GRC) 500 °C Durable 4H-SiC JFET IC Technology

The purpose of this testing was to obtain total ionizing dose (TID) information about custom-built research prototype silicon carbide (SiC) junction field effect transistor (JFET) integrated circuits (ICs) capable of prolonged operation in extremely high-temperature (500 degrees Centigrade) environments. The circuits included ring oscillators and operational amplifiers as well as individual n-channel JFETs. This technology is being considered for use in high temperature, high pressure applications such as Long-Lives Surface System Explorer (LLISSE). These devices were developed at NASA Glenn Research Center (GRC). Testing occurred from July 9th-July 13th, 2018.

Radiation↗
NASA NTRS2018

Operational Testing of 4H-SiC JFET ICs for 60 Days Directly Exposed to Venus Surface Atmospheric Conditions

Prolonged Venus surface missions (lasting months instead of hours) have proven infeasible to date in the absence of a complete suite of electronics able to function for such durations without protection from the planet’s extreme conditions of ~460 °C, ~9.3 MPa (~ 92 Earth atmospheres) chemically reactive environment. Here we report testing data from a successful two-month (60-day) operational demonstration of two 175-transistor 4H-SiC junction field effect transistor (JFET) semiconductor integrated circuits (ICs) directly exposed (no cooling and no protective chip packaging) to a high-fidelity physical and chemical reproduction of Venus surface atmospheric conditions in a test chamber. These results extend the longest reported duration of electronics operation in Venus surface atmospheric conditions almost 3-fold and were accomplished using prototype SiC JFET chips of more than 7-fold increased complexity. The demonstrated advancement marks a significant step towards realization of electronics with sufficient complexity and durability for implementing robotic landers capable of returning months of scientific data from the surface of Venus.

Integrated Circuit↗
NASA NTRSDate not supplied

Early Burn-In Parasitic Conduction in 500 °C Durable SiC JFET ICs

All prior reports of long-term 500 °C operation of SiC JFET-R ICs have noted the existence of an initial “burn-in” period of changes in measured electrical characteristics for the first few hundred hours oven-testing. This work reports measurements of “burn-in parasitic MOSFET conduction” that can substantially impact the performance of some circuits during initial heat-up of JFET ICs, but then subsequently disappears after a few hours of operation at 500 °C. The behavior appears generally consistent with the known MOS phenomenon of bias-temperature driven redistribution of mobile ionic contamination. Approaches for further mitigating this initial burn-in conduction mechanism are discussed.

silicon carbide↗
NASA NTRSDate not supplied

Early Burn-In Parasitic Conduction in 500 °C Durable SiC JFET ICs

All prior reports of long-term 500 °C operation of SiC JFET-R ICs have noted the existence of an initial “burn-in” period of changes in measured electrical characteristics for the first few hundred hours oven-testing. This work reports measurements of “burn-in parasitic MOSFET conduction” that can substantially impact the performance of some circuits during initial heat-up of JFET ICs, but then subsequently disappears after a few hours of operation at 500 °C.

silicon carbide↗
NASA NTRS2025

Design and Simulation of Greatly Improved Future Generation 4H-SiC JFET-R Integrated Circuits for Prolonged 500 °C Operation

This work compares design layouts and circuit simulations of the next two prototype NASA Glenn SiC JFET-R IC fabrication runs designated “IC Gen. 12” and “IC Gen. 13”. Even though both generations employ the same physical JFET gate length and chip size, SPICE simulations predict drastic improvements to IC capabilities and performance metrics for Gen. 13 over Gen. 12. The main factors behind simulated performance differences are thinner n-channel layer leading to reduced operating voltages and switch to stepper-based photolithography that enables roughly 4-fold layout area reductions for functionally identical circuit blocks.

Silicon Carbide↗
NASA NTRS1986

Progress in the development of integrating JFET amplifiers

A new approach to infrared detector readout has appeared with the development of integrating JFET amplifiers. This brief progress report includes results on the operation of commercially available devices at a temperature of 40 K, on their sensitivity and on an effort to develop a new JFET with properties optimized for cryogenic applications. Even with presently available devices it will be shown that for applications such as the Space Infrared Telescope Facility (SIRTF), the most strigent sensitivity requirements of noise currents as low as 1 electron/sec in less than 100 seconds of integration can be met.

Low, F. J.↗
NASA NTRS2010

N channel JFET based digital logic gate structure

A circuit topography is presented which is used to create usable digital logic gates using N (negatively doped) channel Junction Field Effect Transistors (JFETs) and load resistors, level shifting resistors, and supply rails whose values are based on the direct current (DC) parametric distributions of those JFETs. This method has direct application to the current state of the art in high temperature, for example 300.degree. C. to 500.degree. C. and higher, silicon carbide (SiC) device production. The ability to produce inverting and combinatorial logic enables the production of pulse and edge triggered latches. This scale of logic synthesis would bring digital logic and state machine capabilities to devices operating in extremely hot environments, such as the surface of Venus, near hydrothermal vents, within nuclear reactors (SiC is inherently radiation hardened), and within internal combustion engines. The basic logic gate can be configured as a driver for oscillator circuits allowing for time bases and simple digitizers for resistive or reactive sensors. The basic structure of this innovation, the inverter, can be reconfigured into various analog circuit topographies through the use of feedback structures.

Krasowski, Michael J.↗
NASA NTRS2011

Source-Coupled, N-Channel, JFET-Based Digital Logic Gate Structure Using Resistive Level Shifters

A circuit topography is used to create usable, digital logic gates using N (negatively doped) channel junction field effect transistors (JFETs), load resistors, level shifting resistors, and supply rails whose values are based on the DC parametric distributions of these JFETs. This method has direct application to the current state-of-the-art in high-temperature (300 to 500 C and higher) silicon carbide (SiC) device production, and defines an adaptation to the logic gate described in U.S. Patent 7,688,117 in that, by removing the level shifter from the output of the gate structure described in the patent (and applying it to the input of the same gate), a source-coupled gate topography is created. This structure allows for the construction AND/OR (sum of products) arrays that use far fewer transistors and resistors than the same array as constructed from the gates described in the aforementioned patent. This plays a central role when large multiplexer constructs are necessary; for example, as in the construction of memory. This innovation moves the resistive level shifter from the output of the basic gate structure to the front as if the input is now configured as what would be the output of the preceding gate, wherein the output is the two level shifting resistors. The output of this innovation can now be realized as the lone follower transistor with its source node as the gate output. Additionally, one may leave intact the resistive level shifter on the new gate topography. A source-coupled to direct-coupled logic translator will be the result.

Krasowski, Michael J.↗
NASA NTRS2008

Prolonged 500 C Operation of 6H-SiC JFET Integrated Circuitry

This paper updates the long-term 500 C electrical testing results from 6H-SiC junction field effect transistors (JFETs) and small integrated circuits that were introduced at ICSCRM-2007. Two packaged JFETs have now been operated in excess of 7000 hours at 500 degC with less than 10% degradation in linear I-V characteristics. Several simple digital and analog demonstration integrated circuits successfully operated for 2000-6500 hours at 500 C before failure.

Neudeck, Philip G.↗
NASA NTRS2018

Yearlong 500 °C Operational Demonstration of Up-Scaled 4H-SiC JFET Integrated Circuits

This work describes recent progress in the design, processing, upscaling, and testing of 500°C durable two-level interconnect 4H-SiC JFET IC technology undergoing development at NASA Glenn Research Center. For the first time, stable electrical operation of semiconductor ICs for 1 year (8760 hours) at 500°C in air atmosphere is reported. These groundbreaking durability results were attained on two-level interconnect JFET demonstration ICs with 175 or more transistors on each chip. This corresponds to a more than 7-fold increase in 500°C-durable circuit complexity from the 24 transistor ring oscillator ICs reported at HiTEC 2016.

Neudeck, Philip G.↗
NASA NTRS2015

Processing and Prolonged 500 C Testing of 4H-SiC JFET Integrated Circuits with Two Levels of Metal Interconnect

Complex integrated circuit (IC) chips rely on more than one level of interconnect metallization for routing of electrical power and signals. This work reports the processing and testing of 4H-SiC junction field effect transistor (JFET) prototype ICs with two levels of metal interconnect capable of prolonged operation at 500 C. Packaged functional circuits including 3-and 11-stage ring oscillators, a 4-bit digital to analog converter, and a 4-bit address decoder and random access memory cell have been demonstrated at 500 C. A 3-stage oscillator functioned for over 3000 hours at 500 C in air ambient.

Silicon Carbide↗
NASA NTRS2015

4H-SiC JFET Multilayer Integrated Circuit Technologies Tested Up to 1000 K

Testing of semiconductor electronics at temperatures above their designed operating envelope is recognized as vital to qualification and lifetime prediction of circuits. This work describes the high temperature electrical testing of prototype 4H silicon carbide (SiC) junction field effect transistor (JFET) integrated circuits (ICs) technology implemented with multilayer interconnects; these ICs are intended for prolonged operation at temperatures up to 773K (500 C). A 50 mm diameter sapphire wafer was used in place of the standard NASA packaging for this experiment. Testing was carried out between 300K (27 C) and 1150K (877 C) with successful electrical operation of all devices observed up to 1000K (727 C).

JFET↗
NASA NTRS2015

Processing and Prolonged 500 C Testing of 4H-SiC JFET Integrated Circuits with Two Levels of Metal Interconnect

Complex integrated circuit (IC) chips rely on more than one level of interconnect metallization for routing of electrical power and signals. This work reports the processing and testing of 4H-SiC junction field effect transistor (JFET) prototype IC's with two levels of metal interconnect capable of prolonged operation at 500 C. Packaged functional circuits including 3- and 11-stage ring oscillators, a 4-bit digital to analog converter, and a 4-bit address decoder and random access memory cell have been demonstrated at 500 C. A 3-stage oscillator functioned for over 3000 hours at 500 C in air ambient. Improved reproducibility remains to be accomplished.

JFET↗