A phase locked dual channel spacecraft receiver for phase and group path measurements
Phase locked dual channel spacecraft receiver for phase and group path measurements
SPACECRAFT↗
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A 2-to-48-MHz Phase-Locked Loop
A 2-to-48-MHz phase-locked loop (PLL), developed for the U.S. space program, meets or exceeds all space shuttle clock electrical interface requirements by taking as its reference a 2-to-48-MHz clock signal and outputting a phaselocked clock signal set at the same frequency as the reference clock with transistor- transistor logic (TTL) voltage levels. Because it is more adaptable than other PLLs, the new PLL can be used in industries that employ signaling devices and as a tool in future space missions. A conventional PLL consists of a phase/frequency detector, loop filter, and voltage-controlled oscillator in which each component exists individually and is integrated into a single device. PLL components phase-lock to a single frequency or to a narrow bandwidth of frequencies. It is this design, however, that prohibits them from maintaining phase lock to a dynamically changing reference clock when a large bandwidth is required a deficiency the new PLL overcomes. Since most PLL components require their voltage-controlled oscillators to operate at greater than 2-MHz frequencies, conventional PLLs often cannot achieve the low-frequency phase lock allowed by the new PLL. The 2-to-48-MHz PLL is built on a wire-wrap board with pins wired to three position jumpers; this makes changing configurations easy. It responds to variations in voltage-controlled oscillator (VCO) ranges, duty cycle, signal-to-noise ratio (SNR), amplitude, and jitter, exceeding design specifications. A consensus state machine, implemented in a VCO range detector which assures the PLL continues to operate in the correct range, is the primary control state machine for the 2-to-48-MHz PLL circuit. By using seven overlapping frequency ranges with hysteresis, the PLL output sets the resulting phase-locked clock signal at a frequency that agrees with the reference clock with TTL voltage levels. As a space-shuttle tool, the new PLL circuit takes the noisy, degraded reference clock signals as input and outputs phase-locked clock signals of the same frequency but with a corrected wave shape. Since its configuration circuit can be easily changed, the new PLL can do the following: readily respond to variations in VCO ranges, duty cycle, SNR, amplitude, and jitter; continuously operate in the correct VCO range because of its consensus state machine; and use its range detector implements to overlap seven frequency ranges with hysteresis, thus giving the current design a flexibility that exceeds anything available at the time of this development. These features will benefit any industry in which safe and timely clock signals are vital to operation.
Koudelka, Robert D.↗
Phase-lock-loop application for fiber optic receiver
Phase-locked loop circuits are frequently employed in communication systems. In recent years, digital phase-locked loop circuits were utilized in optical communications systems. In an optical transceiver system, the digital phase-locked loop circuit is connected to the output of the receiver to extract a clock signal from the received coded data (NRZ, Bi-Phase, or Manchester). The clock signal is then used to reconstruct or recover the original data from the coded data. A theoretical approach to the design of a digital phase-locked loop circuit operation at 1 and 50 MHz is described. Hardware implementation of a breadboard design to function at 1 MHz and a printed-circuit board designed to function at 50 MHz were assembled using emitter coupled logic (ECL) to verify experimentally the theoretical design.
Ruggles, Stephen L.↗
Phase-locked loops
The basic analysis and design procedures are described for the realization of analog phase-locked loops (APLL), hybrid phase-locked loops (HPLL), discrete phase-locked loops, and digital phase-locked loops (DPLL). Basic configurations are diagrammed, and performance curves are given. A discrete communications model is derived and developed. The use of the APLL as an optimum angle demodulator and the Kalman-Bucy approach to APLL design are discussed. The literature in the area of phase-locked loops is reviewed, and an extensive bibliography is given. Although the design of APLLs is fairly well documented, work on discrete, hybrid, and digital PLLs is scattered, and more will have to be done in the future to pinpoint the formal design of DPLLs.
Gupta, S. C.↗
Phase-locked laser array
A phase-locked laser array comprises a body of semiconductor material having means for defining a plurality of substantially parallel lasing zones which are spaced an effective distance apart so that the modes of the adjacent lasing zones are phase-locked to one another. One of the array electrodes comprises a plurality of electrical contacts to the body between the lasing zones. These contacts provide an enhanced current density profile and thus an increase in the gain in the regions between the lasing zones so that zero degree phase-shift operation between adjacent lasing zones is achievable.
Botez, Dan↗
A phase lock loop system with a modulo 2n pi phase detector
Phase lock loop system with modulo 2n pi phase detector
MODULUS↗
Fast Offset Laser Phase-Locking System
Figure 1 shows a simplified block diagram of an improved optoelectronic system for locking the phase of one laser to that of another laser with an adjustable offset frequency specified by the user. In comparison with prior systems, this system exhibits higher performance (including higher stability) and is much easier to use. The system is based on a field-programmable gate array (FPGA) and operates almost entirely digitally; hence, it is easily adaptable to many different systems. The system achieves phase stability of less than a microcycle. It was developed to satisfy the phase-stability requirement for a planned spaceborne gravitational-wave-detecting heterodyne laser interferometer (LISA). The system has potential terrestrial utility in communications, lidar, and other applications. The present system includes a fast phasemeter that is a companion to the microcycle-accurate one described in High-Accuracy, High-Dynamic-Range Phase-Measurement System (NPO-41927), NASA Tech Briefs, Vol. 31, No. 6 (June 2007), page 22. In the present system (as in the previously reported one), beams from the two lasers (here denoted the master and slave lasers) interfere on a photodiode. The heterodyne photodiode output is digitized and fed to the fast phasemeter, which produces suitably conditioned, low-latency analog control signals which lock the phase of the slave laser to that of the master laser. These control signals are used to drive a thermal and a piezoelectric transducer that adjust the frequency and phase of the slave-laser output. The output of the photodiode is a heterodyne signal at the difference between the frequencies of the two lasers. (The difference is currently required to be less than 20 MHz due to the Nyquist limit of the current sampling rate. We foresee few problems in doubling this limit using current equipment.) Within the phasemeter, the photodiode-output signal is digitized to 15 bits at a sampling frequency of 40 MHz by use of the same analog-to-digital converter (ADC) as that of the previously reported phasemeter. The ADC output is passed to the FPGA, wherein the signal is demodulated using a digitally generated oscillator signal at the offset locking frequency specified by the user. The demodulated signal is low-pass filtered, decimated to a sample rate of 1 MHz, then filtered again. The decimated and filtered signal is converted to an analog output by a 1 MHz, 16-bit digital-to-analog converters. After a simple low-pass filter, these analog signals drive the thermal and piezoelectric transducers of the laser.
Shaddock, Daniel↗
Linear phase demodulator including a phase locked loop with auxiliary feedback loop
A phase modulated wave that may have no carrier power is demodulated by a phase locked loop including a phase detector for deriving an A.C. data output signal having a magnitude and a phase indicative of the phase of the modulated wave. A feedback loop responsive to the data output signal restores power to the carrier frequency component to the loop. In one embodiment, the feedback loop includes a phase modulator responsive to the phase modulated wave and the data output signal. In a second embodiment, carrier frequency power is restored by differentiating the data output signal and supplying the differentiated signal to an input of a voltage controlled oscillator included in the phase locked loop.
Rippy, R. R.↗
Fundamental Noise-Limited Optical Phase Locking at Femtowatt Light Levels
We describe an optical phase lock loop (PLL) designed to recover an optical carrier at powers below one picowatt in a Deep Space optical transponder. Previous low power optical phase lock has been reported with powers down to about 1 pW. We report the demonstration and characterization of the optical phase locking at femtowatt levels. We achieved a phase slip rate below one cycle-slip/second at powers down to 60 femtowatts. This phase slip rate corresponds to a frequency stability of 1 10(exp -14) at 1 s, a value better than any frequency standard available today for measuring times equal to a typical two-way delay between Earth and Mars. The PLL shows very robust stability at these power levels. We developed simulation software to optimize parameters of the second order PLL loop in the presence of laser flicker frequency noise and white phase (photon) noise, and verified the software with a white phase noise model by Viterbi. We also demonstrated precise Doppler tracking at femtowatt levels.
Doppler ranging↗
SEU/SET Tolerant Phase-Locked Loops
The phase-locked loop (PLL) is an old and widely used circuit for frequency and phase demodulation, carrier and clock recovery, and frequency synthesis [1]. Its implementations range from discrete components to fully integrated circuits and even to firmware or software. Often the PLL is a highly critical component of a system, as for example when it is used to derive the on-chip clock, but as of this writing no definitive single-event upset (SET)/single-event transient (SET) tolerant PLL circuit has been described. This chapter hopes to rectify that situation, at least in regard to PLLs that are used to generate clocks. Older literature on fault-tolerant PLLs deals with detection of a hard failure, which is recovered by replacement, repair, or manual restart of discrete component systems. Several patents exist along these lines (6349391, 6272647, and 7089442). A newer approach is to harden the parts of a PLL system, to one degree or another, such as by using a voltage-based charge pump or a triple modular redundant (TMR) voted voltage-controlled oscillator (VCO). A more comprehensive approach is to harden by triplication and voting (TMR) all the digital pieces (primarily the divider) of a frequency synthesis PLL, but this still leaves room for errors in the VCO and the loop filter. Instead of hardening or voting pieces of a system, such as a frequency synthesis system (i.e., clock multiplier), we will show how the entire system can be voted. There are two main ways of doing this, each with advantages and drawbacks. We will show how each has advantages in certain areas, depending on the lock acquisition and tracking characteristics of the PLL. Because of this dependency on PLL characteristics, we will briefly revisit the theory of PLLs. But first we will describe the characteristics of voters and their correct application, as some literature does not follow the voting procedure that guarantees elimination of errors. Additionally, we will find that voting clocks is a bit trickier than voting data where an infallible clock is assumed. It is our job here to produce (or recover) that assumed infallible clock!
Shuler, Robert L., Jr.↗
Phase-locked servo system
A phase lock servo system is described for synchronizing the rotation of a slip ring assembly with the rotation of an air bearing table so that a minimum of torque will be imparted through cables extending from the slip ring assembly to the air bearing table as such is rotated. The system includes two servo loops. The first servo loop includes a rate gyroscope carried on the air bearing table which generates a signal through a summing junction to be compared with a signal coming from a tachometer coupled to the slip ring assembly. The corrective signal is applied to a torque motor for rotating the slip ring assembly. The second servo loop includes a pair of photo detector cells which generate pulses responsive to the rotation of the air bearing table and slip ring assembly which are fed through a phase detector, and a variable gain amplifier to the summing junction circuit to provide a fine adjustment for rotating the slip ring assembly.
Burdin, C.↗
Optimum design of hybrid phase locked loops
The design procedure of phase locked loops is described in which the analog loop filter is replaced by a digital computer. Specific design curves are given for the step and ramp input changes in phase. It is shown that the designed digital filter depends explicitly on the product of the sampling time and the noise bandwidth of the phase locked loop. This technique of optimization can be applied to the design of digital analog loops for other applications.
Lee, P.↗
Improved phase locked loop receiver
Improved phase locked loop receiver tracks and demodulates a signal whose signal-to-noise ratio may be low and whose information sidebands are close in frequency. This receiver recovers the carrier from input signals and applies it to a demodulator which recovers the sidebands.
Daley, T. J.↗
Error rate minimization for improved phase- locked loop damping characteristics
Phase locked loop damping characteristics optimization based on input rms error rate minimization and transient error integral square value limitation
Jones, T. J.↗
Control of mutual phase locking of monolithically integrated semiconductor lasers
The degree of phase locking between the individual laser apertures is the major issue in phase-locked laser arrays. A description is presented of a series of experiments in which the mutual coherence of two laser apertures is characterized by measuring the visibility of the far-field interference fringes. Attention is given to an approach which makes it possible to control continuously the degree of coherence by means of a separate contact configuration. An investigation was conducted of the far-field radiation patterns of pairs of lasers obtained under various conditions. The results of the present study demonstrate the feasibility of controlling the mutual phase locking between semiconductor lasers by varying the gain distribution between their pumped stripes.
Kapon, E.↗
Phase-locked loop FM demodulator
A conventional phase-locked loop is improved by replacing its phase detector with one comprising a linear ramp generator and a sample-and-hold circuit, thus eliminating the need for a lowpass loop filter, although the output of the sample-and-hold circuit may be filtered in the case of a very low level modulating signal on the incoming FM signal, but then filtering is not a difficult problem as in a conventional phase-locked loop. The result is FM demodulation by zero-order estimation. For FM demodulation by first-order estimation, the arithmetic difference between adjacent samples is formed, and using a second sample-and-hold circuit an arithmetic difference signal is produced as an input to a second ramp generator that is reset after each sampling cycle to generate a ramp the slope of which is a function of the arithmetic difference signal stored in the second sample-and-hold circuit. The ramp thus generated by the second ramp generator is arithmetically summed with the zero-estimation signal from the first sample-and-hold circuit to form a first-order estimation signal. Filtering such a first-order estimation signal is less of a problem than filtering a zero-order estimation signal.
Kirkham, Harold↗
Wideband Phase-Locked Angle Modulator
Modified configuration for phase-locked angle modulator circuit makes possible to design filters in modulating portion of circuit independently of filter in phase-locked-loop portion. Bandwidth of phase- or frequency-modulated output not limited by low-pass nature of loop filter.
Nguyen, Lim↗
A model distribution for the phase error in second-order phase-locked loops.
Model distribution for phase error in second-order phase locked loop used to complement analytical model in signal to noise region
PHASE ERROR↗