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At least 37 records · Page 2

Factors and Considerations for Modeling Loss of a GaN-based Inverter

The article investigates the impacts of four often-neglected factors on the loss model of a GaN-based full-bridge inverter: parasitic capacitance of the devices, dynamics of junction temperature (Tj) under time-varying power dissipation (Ploss), case temperature estimation, and detailed considerations of the passive components. Procedures to calculate the converter loss considering the above factors are proposed and implemented. A 4.5-kW hard-switching inverter prototype using gallium nitrite (GaN) high-electron-mobility transistors is used to experimentally demonstrate the impact of each factor on the converter loss model. Furthermore, it is found that the accuracy of a converter loss model is mainly affected by the passive components at the light load condition, whereas the thermal and loss models of the active components become the major factors as the output power increases. The results show that after considering the above factors, the converter loss discrepancy between calculation and measurement can be reduced from 30.6 W (28%) to 2.5 W (less than 3%) at heavy load (Po = 4.5 kW), while at the light load condition (Po = 500 W), it is reduced from 3.9 W (28%) to 2.6 W (16%). Furthermore, the difference between simulated and measured case temperature of the GaN devices is within 6 °C.

42 ENGINEERING↗

A high-volume resonator for L-band DNP-NMR

DNP-NMR and EPR experiments that operate at or greater than L-band (i.e., ν 0 (e – ) = 1–2 GHz) are typically limited to maximum sample volumes of several hundred µL. These experiments rely on well-known resonator designs for DNP/EPR irradiation such as the loop-gap resonator and Alderman-Grant coil, where their maximum volumes limit further application to imaging experiments and high-throughput screening beyond L-band. Herein, we demonstrate a birdcage (BC) resonator design that can accommodate several mL of sample while operating around 1.5 GHz. The sample volume is maximized by using two identical BC resonators in a stacked configuration. Simulations are used to optimize the BC design and the performance is validated experimentally with liquid-state Overhauser-DNP-NMR experiments. This BC design exploits just the parasitic capacitance of conductive rings and features no fixed tuning capacitors. An enhancement of –77 is achieved on a 10 mM 4-Amino-TEMPO in H 2 O sample for a 5 mL sample volume. Finally, the associated sample heating is minimal due to the low-E-fields generated and the large sample mass with +3.4 K when driving 100 W for several seconds.

47 OTHER INSTRUMENTATION↗

Single channel PICOSEC Micromegas detector with improved time resolution

This paper presents design guidelines and the experimental verification of a single-channel PICOSEC Micromegas (MM) detector with an improved time resolution. The design encompasses the detector board, vessel, auxiliary mechanical parts, and electrical connectivity for high voltage (HV) and signals, focusing on improving the stability, reducing noise, and ensuring signal integrity to optimize timing performance. A notable feature is the simple and fast reassembly procedure, facilitating quick replacement of the detector internal components that allows for an efficient measurement strategy involving different detector components. The paper also examines the influence of parasitic capacitance and inductance on the output signal integrity. To validate the design, a prototype assembly and three interchangeable detector boards with varying readout pad diameters were manufactured. Detectors were initially tested in the laboratory. Finally, the timing performance of the detectors with different pad sizes was verified using 150 GeV muons. Notably, a record time resolution for a PICOSEC Micromegas detector technology with a CsI photocathode of 12.5 ± 0.8 ps was achieved for a detector with 10 mm diameter readout pad size.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗

Skipper-CCD Output Sensitivity Improvement with a Common Source Cascode Amplifier

A Skipper-CCD output has been traditionally readout in a source follower configuration, also known as common drain, mainly because in this configuration a good compromise between sensitivity, noise and speed is achieved. In this work a different approach is presented: the output transistor is connected in a common source configuration and an external cascode device is added in series, obtaining a voltage gain higher than unity without increasing significantly the parasitic capacitance due to Miller effect and thus increasing the obtained voltage per electron of charge. The proposed output stage improves the sensitivity 3.4 times when compared with the traditionally used stage while keeping almost the same equivalent noise charge.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗

Towards Scalable 3D Integration of 2T-nC FeRAM with Hundreds of Layer Stacking

In this article, we study the limits of the number of capacitors and read history dependence in a 2T-nC ferroelectric random-access memory (FeRAM) cell, paving the way for its high-density integration toward hundreds of stacked layers. Through a comprehensive experimental and simulation study on the scaling behavior of the 2T-nC FeRAM architecture, we demonstrate: (i) successful fabrication of 2T-64C cells with robust memory operation and clearly distinguishable ‘0’ and ‘1’ states, even in 64- capacitor configurations; (ii) that the parasitic capacitance of the floating node originates predominantly from the linear component of the ferroelectric capacitor, and its impact on n-scaling—due to degraded sense margin—can be mitigated by floating unselected capacitors with enough TΩ isolation; (iii) that sharing write and read transistors among n capacitors introduces a read history dependence issue due to fluctuating floating node voltage (VFN); and (iv) that a proposed FN discharge scheme can effectively eliminate read-sequence dependence, at the cost of reduced read endurance.

36 MATERIALS SCIENCE↗

Demonstration of Vertical 2T-nC FeRAM Hybrid Cell and Its Scalability for High-Density 3-D Ferroelectric Capacitor Memory

In this work, we present a comprehensive experimental and modeling study on the scaling of vertical 2T-nC ferroelectric random access memory (FeRAM) hybrid cells, comprising n metal-ferroelectric–metal (MFM) capacitors, to demonstrate a high-performance and high-density 3-D capacitor memory. Our contributions include: 1) successful process integration of vertical 2T-3C FeRAM cells by stacking MFM structures on top of Si CMOS transistors; 2) experimental validation of memory cell functionality, confirming the feasibility of the vertical 2T-nC FeRAM architecture; 3) an analysis of scaling effects on parasitic capacitance in densely integrated 3-D arrays, using 3-D technology computer-aided design (TCAD) simulations; 4) exploration of aggressive stacking of write bitlines (WBLs) to enhance memory density, where ferroelectric linear capacitance ( C FE ) enables self-boosted inhibition under the V W /2 scheme, but renders the V W /3 scheme ineffective due to intolerable write disturbances; and 5) assessment of horizontal scaling, revealing significant increases in read disturbances caused by interplane capacitance between adjacent WBLs ( C Z ). This work represents an early exploration into the potential of 2T-nC FeRAM as a scalable and efficient 3-D memory solution.

42 ENGINEERING↗

Planar Transformer With Asymmetric Integrated Leakage Inductance Using Horizontal Air Gap

This article presents a novel planar-based transformer winding and core structure with controllable leakage inductance generation for integrated magnetics applications. As a result of limitations in integrated magnetics from the literature, a new approach is proposed utilizing semi-interleaved windings and controllable leakage via a leakage flux core leg featuring a horizontal air gap. Here, the proposed transformer design is analyzed via detailed reluctance modeling to determine closed-form equations for the magnetizing and asymmetrically distributed leakage inductances. Next, a genetic-algorithm-based multiobjective design optimization problem is developed, seeking to minimize the core and winding losses of the proposed transformer subject to a set of parametric and geometric constraints in a dc-ac dual-active-bridge topology for microinverter applications. The optimization was extended to include other integrated magnetic structures from the literature, where it is determined that the proposed transformer is superior from the perspectives of efficiency, footprint area, and parasitic capacitance. Based on the results of the optimization analysis, two designs with theoretical transformer California Energy Commission (CEC) efficiency drops (i.e., CEC efficiency reduction specifically due to the transformer loss mechanisms) of 1.19% and 0.83% were fabricated and evaluated for electrical and thermal performance in the proposed 40 V, 400 W microinverter.

42 ENGINEERING↗

IGFET/SOI fabrication method

Technique increases switching speeds, shortens channel length, reduces parasitic capacitance and gate overlap, and minimizes gate-to-channel capacitance. The p and n sections may be reversed, allowing fabrication of complementary devices.

Feltner, W. R.↗

Time delay and integration array (TDI) using charge transfer device technology. Phase 2, volume 1: Technical

The 20x9 TDI array was developed to meet the LANDSAT Thematic Mapper Requirements. This array is based upon a self-aligned, transparent gate, buried channel process. The process features: (1) buried channel, four phase, overlapping gate CCD's for high transfer efficiency without fat zero; (2) self-aligned transistors to minimize clock feedthrough and parasitic capacitance; and (3) transparent tin oxide electrode for high quantum efficiency with front surface irradiation. The requirements placed on the array and the performance achieved are summarized. This data is the result of flat field measurements only, no imaging or dynamic target measurements were made during this program. Measurements were performed with two different test stands. The bench test equipment fabricated for this program operated at the 8 micro sec line time and employed simple sampling of the gated MOSFET output video signal. The second stand employed Correlated Doubled Sampling (CDS) and operated at 79.2 micro sec line time.

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Stress-relieved solder joints

Mechanical stress on solder joints is reduced by procedure for soldering electronic components to circuit boards. Procedure was developed for radio-frequency (RF) strip-line circuits, for which dimensions must be carefully controlled to minimize parasitic capacitance and inductance. Procedure consists of loosening component from its mounting after each lead is soldered relieving induced stresses before next soldering step.

Zemenick, C. J.↗

Ultra high speed image processing techniques

Packaging techniques for ultra high speed image processing were developed. These techniques involve the development of a signal feedthrough technique through LSI/VLSI sapphire substrates. This allows the stacking of LSI/VLSI circuit substrates in a 3 dimensional package with greatly reduced length of interconnecting lines between the LSI/VLSI circuits. The reduced parasitic capacitances results in higher LSI/VLSI computational speeds at significantly reduced power consumption levels.

Anthony, T.↗

Advances in SIS receiver technology

Significant advances in SIS receiver technology since the last Asilomar meeting include: superconductor materials, integrated inductive tuning elements, and planar mounting structures. The effect of these advances is to push the upper frequency operating limit from about 600 to 1500 GHz, and to enhance the feasibility of focal plane arrays of heterodyne receivers. A fundamental high frequency operating limit of SIS mixers is set by the superconducting energy gap. A practical limitation for high frequency operation of SIS junctions is their parasitic capacitance and resistance. The performance of the mixer will be degraded by the Resistor-Capacitor rolloff. Several designs were reported for inductive elements integrated on the same substrate as the SIS junctions to tune out the bulk junction capacitance. Most millimeter SIS-based heterodyne receivers have used waveguide coupling structures. Technology has advanced to the state where programs that have a high probability of success can be defined to produce arrays of SIS receivers for frequencies as high as 1500 GHz.

Frerking, M. A.↗

Improved Planar Schottky Diode

Modifications of design and fabrication of surface-channel planar Schottky diode (GSC-13063) reduce parasitic capacitances to theoretical minimum, eliminate buried layer of conductive material between anode contact and semi-insulating substrate, and reduce thickness of diode chip. Changes in epitaxial layer structure and additional fabrication steps reduce conversion loss in millimeter and submillimeter mixers.

Bishop, William↗

A 250 GHz planar low noise Schottky receiver

A planar quasi-optical Schottky receiver based on the quasi-integrated horn antenna has been developed and tested over the 230-280 GHz bandwidth. The receiver consists of a planar GaAs Schottky diode placed at the feed of a dipole-probe suspended on a thin dielectric membrane in an etched-pyramidal horn cavity. The diode has a 1.21 micron anode diameter and a low parasitic capacitance due to the use of an etched surface channel. The antenna-mixer results in a measured DSB conversion loss and noise temperature at 258 GHz of 7.2 dB +/- 0.5 dB and 1310 K +/- 70 K, respectively, at room temperature. The design is compatible with SIS mixers, and the low cost of fabrication and simplicity makes it ideal for submillimeter-wave imaging arrays requiring a 10-20 percent bandwidth.

Ali-Ahmad, Walid Y.↗

An 86-106 GHz quasi-integrated low noise Schottky receiver

An integrated planar receiver was developed and tested over the 82-112 GHz bandwidth. The quasi-integrated antenna used in the receiver has a high gain, a high Gaussian coupling efficiency, and a wide bandwidth. The novel mixer design consists of a planar GaAs Schottky diode placed at the feed of a dipole-probe suspended inside an integrated horn antenna. The diode uses an etched surface channel and a planar air bridge for reduced parasitic capacitance. At 92 GHz, the room-temperature antenna-mixer exhibits a double sideband conversion loss and noise temperature of 5.5 +/- 0.5 dB and 770 K +/- 50 K, respectively. The measured DSB conversion loss and noise temperature over a 20 GHz bandwidth (86 GHz-106 GHz) remain less than 6.2 dB +/- 0.5 dB and 1000 K +/- 50 K, respectively. The low cost of fabrication and simplicity of the design makes it ideal for millimeter- and submillimeter-wave receivers.

Ali-Ahmad, Walid Y.↗

Fully-depleted silicon-on-sapphire and its application to advanced VLSI design

In addition to the widely recognized advantages of full dielectric isolation, e.g., reduced parasitic capacitance, transient radiation hardness, and processing simplicity, fully-depleted silicon-on-sapphire offers reduced floating body effects and improved thermal characteristics when compared to other silicon-on-insulator technologies. The properties of this technology and its potential impact on advanced VLSI circuitry will be discussed.

Offord, Bruce W.↗

BIB mixers

We have determined that the multi-pin 'microprocessor style' packages in which current Blocked Impurity Band (BIB) devices are mounted will not meet our IF bandwidth spec of greater than 2 GHz for a practical mixer. Hence we have started to repackage the Ga:Ge BIB devices in new microwave compatible packages. The smaller size of the microwave package mount necessitates cutting the BIB array down to include only the 3 smallest detectors: 0.2, 0.4, and 0.6 mm sq. A FIR beam incident at f/1.5 can be focussed on the smallest element for wavelengths shorter than 100 microns. A more typical (easier) beam convergence of f/3 will require 0.4 mm elements at 100 microns and 0.6 mm elements at 170 microns wavelength. Since the device capacitance (parasitic loss) scales with detector size, there is a tradeoff of speed of response and optical convenience. Our existing optics produce only the slower convergence beam, so we need to redesign the optical layout and are looking at long focal length all-reflective microscope objectives. BIB detectors and the edge-coupled microbolometers have restricted IF bandwidths, an order of magnitude less than what is possible with the Schottky-diode mixers we currently use for astronomical observations. Consequently the frequencies of the FIR laser lines must be close to the astronomical line of interest to be an effective Local Oscillator (LO). We have therefore begun a coordinated effort to discover and measure new FIR laser transition lines in close frequency coincidence with important astrophysical lines. Most of this effort involves pumping isotopic variants of known good laser molecules with laser lines from isotopic variants of CO2. We have been most successful in detecting new FIR lines in deuterated ammonia. One line in particular is very close to the frequency of HD rotational line at 2675 GHz.

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