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At least 37 records · Page 2

Cryogenic Front-End ASICs for Low-Noise Readout of Charge Signals

This paper presents design details and measurement results of LArASIC, a front-end application specific integrated circuit (ASIC) designed for low-noise readout of charge signals generated in neutrino study experiments within liquid argon time projection chambers. LArASIC comprises of 16-channels of programmable charge amplification and pulse shaping stages that provide a voltage readout proportional to the input charge and was optimized for operation at liquid argon temperature, i.e., 89 K. The chip was fabricated in a 180 nm CMOS process. Measurements at liquid nitrogen temperature, i.e., 77 K, indicate that the channel outputs have high linearity (INL < 0.1%) within the operating range, an equivalent noise charge of 534 electrons for a peaking time of 1 µs and a detector capacitance of 150 pF, and a worst-case inter-channel cross-talk of 0.35%. The paper also presents design choices made in the process of migrating LArASIC to CHARMS, an ASIC to be fabricated in a 65 nm process that includes all features provided by LArASIC, along with additional digital programmability for improved robustness and flexibility. CHARMS is intended for use in future high-energy physics experiments that require high-resolution charge or light readout with shorter pulse peaking times.

47 OTHER INSTRUMENTATION

Skipper-in-CMOS: Nondestructive Readout With Subelectron Noise Performance for Pixel Detectors

The Skipper-in-CMOS image sensor integrates the nondestructive readout capability of skipper charge coupled devices (Skipper-CCDs) with the high conversion gain of a pinned photodiode (PPD) in a CMOS imaging process while taking advantage of in-pixel signal processing. This allows both single photon counting as well as high frame rate readout through highly parallel processing. The first results obtained from a ${15} \times {15}~\mu $ m2 pixel cell of a Skipper-in-CMOS sensor fabricated in Tower Semiconductor’s commercial 180-nm CMOS image sensor process are presented. Measurements confirm the expected reduction of the readout noise with the number of samples down to deep subelectron noise of $0.15\text {e}^ - $ , demonstrating the charge transfer operation from the PPD and the single photon counting operation when the sensor is exposed to light. This article also discusses new testing strategies employed for its operation and characterization.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND

Versatile High-Gain Low-Noise Readout ASIC for Silicon Microstrip Tracking Detectors

This work presents Turpial, a custom-designed low- power front-end readout ASIC for microstrip silicon sensors. Implemented in 130 nm CMOS technology, the chip integrates 64 identical readout channels, each including a configurable charge-sensitive amplifier, a bipolar pulse shaper, a 32-sample 50 Msps analog memory, and a 12-bit RC-hybrid SAR ADC operating at 1 Msps. To satisfy the target power budget of 5 mW per channel, the architecture employs a time-decoupled readout scheme in which fast transient signals are first captured in the analog memory and subsequently digitized at a lower rate. Turpial supports a wide dynamic range from 1 kℎ+ to 1 Mℎ+ while maintaining low noise performance, targeting an equivalent noise charge (ENC) below 200 𝑒−including the sensor, and providing a maximum gain of 1500 mV/fC. A digital block manages slow control, data acquisition, and data serialization through dual CML 300 Mb/s serializers. In addition, an on-chip reference circuit, based on a sub-1 V bandgap reference and an integrated LDO regulator, eliminates the need for external reference circuitry. Experimental results demonstrate that both the individual building blocks and the fully integrated ASIC meet the design specifications.

Hernandez, Hugo [Stanford University] (ORCID:00000

SQUID Readout of a High-$Q$ Superconducting $LC$ Resonator

We demonstrate the readout of a superconducting $LC$ resonator, with $Q \approx 2 \times 10^{6}$ at approximately 250 kHz, using a dc SQUID followed by a SQUID series-array amplifier readout chain. We find that $Q$ depends on the SQUID flux-bias point, increasing near the shallow-slope point of the SQUID modulation curve and decreasing near the steep-slope point, consistent with the previously observed SQUID damping effects. From this variation, we infer the SQUID effective input impedance. We further infer the effective temperature of the resonator circuit from the resonance peak in the noise spectrum and show that it also depends on the SQUID flux-bias point, suggesting a possible contribution from SQUID back-action noise. This system provides a working prototype for future experiments based on lumped-element resonators with SQUID readout, in particular low-mass axion searches within the DMRadio program.

FOS: Physical sciences

Optimization and Performance Characterization of the Second Generation Fermilab Constant Fraction Discriminator Readout ASIC

We present the optimization and performance characterization of the second-generation Fermilab Constant Fraction Discriminator ASIC (FCFD), designed for the readout of AC-coupled low-gain avalanche detector (LGAD) strip-sensors. The FCFD is explicitly engineered to be insensitive to signal-amplitude variations, thereby removing the need for time-walk correction that is required in other LGAD time-stamping readout ASICs. This updated version, referred to as FCFD1.1, incorporates several enhancements over the first iteration to address key challenges in AC-coupled LGAD front-end design. We outline the primary readout-ASIC design considerations for these applications, describe the methodology used to evaluate critical sensor and system parameters, and summarize the additionally implemented features. Performance measurements using injected charge signals and minimum-ionizing particles in test-beams demonstrate a time resolution of approximately 40 ps and a position resolution of roughly \SI{15}{\micro\meter} when tested with beam particles uniformly over the active area of the sensor.

Apresyan, Artur [Fermilab] (ORCID:0000000261860130

SALSA: a new versatile readout chip for MPGD detectors

The SALSA chip is a future readout ASIC foreseen for the MPGD detectors, developed in the framework of the EIC collider project, to equip the MPGD trackers of the EPIC experiment. It is designed to be versatile, to be adapted to other usages of MPGD detectors like TPC or photon detectors. It integrates a frontend block and an ADC for each of the 64 channels, associated to a configurable DSP processor meant to correct data and reduce the raw data flux to limit the output bandwidth. It will be compatible with the continuous readout foreseen for the EPIC DAQ, but will also work in a triggered environment. Several prototypes are already produced in order to qualify the different blocks of the chip, in particular the frontend, the ADC and the clock generation. The next 32-channel prototype is currently under development and is planed to be produced in 2025. In conclusion, the final prototype will be produced and tested from 2026 for a production of the SALSA chip at the horizon of 2027.

Data processing

Readout electronics for low occupancy High-Pressure Gas TPCs

High-Pressure Gas Time Projection Chambers (HPgTPCs) have benefits such as low energy thresholds, magnetisability, and 4π acceptance, making them ideal for neutrino experiments such as DUNE. We present the design of an FPGA-based solution optimised for Gaseous Argon Near Detector (ND-GAr), which is part of the Phase-II more capable near detector for DUNE. These electronics reduce the cost significantly compared to using collider readout electronics, which are typically designed for much higher occupancy and therefore, for example, need much larger numbers of FPGAs and power per channel. We demonstrate the performance of our electronics with the Teststand for an Overpressurised Argon Detector (TOAD) at Fermilab in the US at a range of pressures and gas mixtures up to 4.5 barA, reading out ∼10 000 channels from a Multi-Wire Proportional Chamber (MWPC). The operation took place between April and July of 2024. We measure the noise characteristics of the system to be sufficiently low, and we identify sources of noise that can be further mitigated in the next iteration. We also note that the cooling scheme used in the test requires improvement before full-scale deployment. Despite these necessary improvements, we show that the system can fulfil the needs of a HPgTPC for a fraction of the price of collider readout electronics.

Data acquisition concepts

Strip-based Scintillation Detector for Dual-readout High-granularity Calorimetry

New calorimeter technology is being developed for future collider experiments. We are developing a calorimeter that integrates two technologies, a high-granularity calorimeter and a dual-readout calorimeter, and has high time resolution at a picosecond level. The proposed calorimeter is a sampling calorimeter based on scintillation and Cherenkov detectors with high-granularity readout. The Cherenkov detector has a picosecond level time resolution. For the high-granularity scintillation detector, scintillator strips of 300mm × 30mm ×3mm-thick are aligned horizontally and vertically to realize an effective 30mm-square-cell segmentation. Prototype strips with different designs and scintillator materials were tested to compare the performance.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND

Overview of the front-end electronics of CMS HGCal - including readout and powering

The end-cap calorimeters of CMS will be upgraded to a single High Granularity Calorimeter (HG-Cal) for the HL-LHC, including both silicon sensors and scintillator tiles with on-tile SiPMs as active elements. The readout of the active elements is performed by an ASIC (HGCROC in 130 nm CMOS technology) that measures the amplitude and arrival time of the signals. The amplitude is measured over a large dynamic range to allow calibration with single particles and the measurement of TeV showers. The time of arrival of high-energy showers will be measured with a precision of around 30 ps. A second pair of “concentrator” ASICs - ECON-T and ECON-D - takes the data from the HGCROC channels and packages them for transmission via optical links to the off-detector electronics. The ECON-T transmits trigger data at 40 MHz, to form part of the level-1 trigger. The ECON-D transmits concentrated data packets at up to 1 MHz, upon reception of a level-1 trigger signal. In addition to these ASICs, HGCal will use modified versions of common HL-LHC electronics developments, for the power chain and the optical control and readout. The dense nature of the HGCal provides additional challenges for the electronic boards and cabling. In this proceedings the overall HGCal front electronics scheme, including the latest performance of the HGCROC and ECON ASICs is presented.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND

Opportunities and challenges to study solar neutrinos with a Q-Pix pixel readout

The study of solar neutrinos presents significant opportunities in astrophysics, nuclear physics, and particle physics. However, the low-energy nature of these neutrinos introduces considerable challenges to isolate them from background events, requiring detectors with low-energy threshold, high spatial and energy resolutions, and low data rate. We present the study of solar neutrinos with a kiloton-scale liquid argon detector located underground, instrumented with a pixel readout using the Q-Pix technology. We explore the potential of using volume fiducialization, directional topological information, light signal coincidence, and pulse-shape discrimination to enhance solar neutrino sensitivity. We find that discriminating neutrino signals below 5 MeV is very difficult. However, we show that these methods are useful for the detection of solar neutrinos when external backgrounds are sufficiently understood and when the detector is built using low-background techniques. When building a workable background model for this study, we identify 𝛾 background from the cavern walls and from capture of 𝛼 particles in radon decay chains as both critical to solar neutrino sensitivity and significantly underconstrained by existing measurements. Finally, we highlight that the main advantage of the use of Q-Pix for solar neutrino studies lies in its ability to enable the continuous readout of all low-energy events with minimal data rates and manageable storage for further off-line analyses.

multi-purpose particle detectors

Radiation-Hard Smart-Pixel Detector ASIC ReadOut with Digital AI in 28nm

Detectors at future high energy colliders will face enormous technical challenges. Disentangling the unprecedented numbers of particles expected in each event will require highly granular silicon pixel detectors with billions of readout channels. With event rates as high as 40 MHz, these detectors will generate petabytes of data per second. To enable discovery within strict bandwidth and latency constraints, future trackers must be capable of fast, power efficient, and radiation hard data-reduction at the source. This effort is pursuing the co-design development of high-performance readout smart pixel ASICs for a future Phase III High Luminosity upgrade of the Large Hadron Collider. A 1.6mm2 ASIC prototype was designed by Fermilab in CMOS 28 nm bulk process and submitted for manufacturing in February 2024. It leverages the analog front-end pixel design of a previous prototype fabricated and tested in 2023, which achieved a simulated detection level of ~400e- with 30fF input capacitance. The ROIC consists of two matrices of 16×16 smart pixels, each 25×25 μm2 in size. Each smart pixel contains a charge-sensitive preamplifier with leakage current compensation and three auto-zero comparators for a 2-bit flash-type ADC. There is digital space for the integration of our fully combinatorial AI that performs momentum classification at the bunch crossing rate. The total power consumption is ∼6μW per pixel, which corresponds to ~1mW/cm2. The ASIC incorporates programmable front-end charge injection circuitry to generate pixel cluster charges during characterization. The cluster profile will be generated to duplicate hit characteristics of various momentum (pT). We will present early results from chip testing.

Parpillon, Benjamin

2x2 Demonstrator High-Coverage Light Readout System in a Novel LArTPC

DUNE is a long-baseline Liquid Argon Time Projection Chamber (LArTPC) neutrino oscillation experiment. Its near detectors, located at Fermi National Laboratory, will constrain systematic errors on far detector measurements. The 2x2 Demonstrator, a novel proof of concept prototype for the ND LArTPC, has a modular TPC design that mitigates event pileup in a high-occupancy nearline beam environment, further aided by a native 3D pixelated charge readout and a 30% coverage, low profile light readout. This will be the first large-scale LArTPC to utilize pixels in place of wire planes

72 PHYSICS OF ELEMENTARY PARTICLES AND FIELDS

Dual Readout in Homogenous Inorganic Scintillators for Precision Calorimeters

Homogeneous inorganic scintillator-based calorimeters are the gold standard for electromagnetic energy resolution, but often degrade the hadronic energy resolution achievable at colliders. By incorporating the dual readout technique, we seek to improve the hadronic energy resolution of these calorimeters through the measurement and separation of the scintillation and Cherenkov light in hadronic showers. In April 2024, CalVision performed single-crystal tests using the electron test beam at DESY. Using a single delay line technique for waveform analysis, sufficient cerenkov light can be extracted to fully capitalize on the dual readout technique. This talk will present the results of PWO, BGO, BSO, PbF2, and two novel scintillating glasses.

Anderson, Thomas [Virginia U.]

ACHILLES-GENIE Interface for Neutrino Simulations, ADRIANO2 Tile Prototype for High-Granularity Dual-Readout Calorimetry

ICARUS (Imaging Cosmic And Rare Underground Signals) is a liquid argon time projection chamber (LArTPC) detector that pursues the sterile neutrino, which relies on accurate simulations of neutrino-argon interactions. REDTOP (Rare Eta Decays To Observe new Physics) is a proposed low-energy, high-intensity meson factory designed to explore rare $\eta$/$\eta'$ meson decays and probe physics beyond the Standard Model. As a next-generation experiment, this requires both accurate simulations and innovative detector technologies. This project contributes to both ICARUS, from a simulation perspective, and REDTOP, from both a simulation and detection perspective, through the event generation of lepton-nucleon interactions and the physical enhancement of the calorimeter technology within the REDTOP detector. We developed an interface between ACHILLES (A CHIcago Land Lepton Event Simulator), a theory-driven lepton-level event generator, and GENIE, a robust event generator framework used for neutrino physics. By incorporating the precise theoretical cross-section calculations of ACHILLES into the experimental realism of GENIE, the interface allows for improved accuracy of neutrino-nucleon simulations, which can be adapted for the proton beam specifications of the REDTOP meson factory as well as for the ICARUS experiment. In parallel, we developed an improved prototype for the ADRIANO2 (A Dual Readout Integrally Active Non-segmented Option) dual-readout calorimeter tiles for the REDTOP detector. To improve the efficiency of the lead-glass tiles trapping Cherenkov light for energy reconstruction and particle identification, we optimized the application of a highly reflective coating. Through viscosity and thickness control, masking, and a custom spray technique, we refined the coating process to reduce surface defects and improve light yield. Together, these efforts strengthen the ICARUS neutrino program and REDTOP's capability of detecting rare decay events.

Visser, Erin [Michigan State U.]

MIP dQ/dx Calibration in DUNE ND-LAr Prototypes with Pixelated Charge Readout

The Deep Underground Neutrino Experiment (DUNE) will be a next-generation long baseline neutrino oscillation experiment that will employ LArTPC technology in a near detector placed at Fermilab and a far detector at the Sanford Underground Research Facility, at a baseline of 1300 km. The DUNE Liquid Argon Near Detector (ND-LAr) design takes into account the high neutrino intensity expected from the beam at the Long-Baseline Neutrino Facility (LBNF): 35 modules, each containing two optically separated time projection chambers, are instrumented with a pixel-based, true 3D charge readout alongside scintillation light traps to disentangle the O(100) interactions expected per 10us beam spill. A robust prototyping program supports ND-LAr’s design: the 2x2 Demonstrator consists of four scaled-down ND-LAr modules exposed to the NuMI beam at Fermilab, and the Full Scale Demonstrator (FSD) is a single ND-LAr module tested with cosmic rays at the University of Bern. We present here an analysis of minimum ionizing particle (MIP) tracks selected from 2x2 beam data and FSD cosmic ray data used to benchmark the pixel-based charge readout simulation and calibration in both detectors, with the ultimate goal of validating the design of DUNE ND-LAr as well as informing future calibration methods. This poster will showcase the dependence of the charge response on track inclination as well as a per-pixel dQ/dX extraction.

Mandujano, Roberto [UC, Irvine]

Status of the Mu2e calorimeter readout electronics

The Mu2e experiment [1] at Fermilab will search for the neutrino-less coherent conversion of a muon into an electron in the field of a nucleus. Mu2e detectors comprise a straw tracker, an electromagnetic calorimeter and a veto for cosmic rays. The calorimeter employs 1348 Cesium Iodide crystals readout by silicon photomultipliers and fast front-end and digitization electronics. The front-end electronics consists of two discrete readout circuits (AMP-HV) for each crystal. These provide the amplification, shaping stage and linear regulation of the SiPM bias voltage and monitoring. The SiPM and front-end control electronics is implemented in a battery of mezzanine boards each equipped with an ARM processor that controls a group of 20 Amp-HV circuits distributing the low voltage and the high-voltage. The electronic is hosted in crates located on the external surface of calorimeter disks. The crates also host the waveform digitizer board (DIRAC) that performs digitization of the front end signals and transmit the digitized data to the Mu2e DAQ. Calorimeter electronic is hosted inside the cryostat and must sustain very high radiation and magnetic field so it was necessary to fully qualify it. The system design and quality assurance procedures will be reviewed.

72 PHYSICS OF ELEMENTARY PARTICLES AND FIELDS

A Sub-electron-noise Skipper-CCD Readout ASIC with Improved Channel-to-channel Isolation and an Integrated Cryogenic Voltage Reference

The MIDNA application specific integrated circuits (ASICs) are a series of skipper-CCD readout chips fabricated in a 65 nm low-power CMOS process that implement a correlated double sampling signal processing chain based on dual-slope integrators. They are capable of working from room to cryogenic temperatures, down to 84 K. The present iteration of the ASIC has been fabricated including several design updates and the addition of an on-chip voltage reference, resulting in improved performance. This work presents the main vulnerabilities solved, the changes carried out, and the resulting performance benefits. Measurements with a skipper-CCD and the ASIC at 140 K showed that the single-electron resolution can be reached by averaging the measured charge in the analog domain using the analog pile-up technique with a readout noise as low as 0.11 erms of equivalent charge for 1200 samples. The channel-to-channel crosstalk was also characterized showing values better than -62 dB.

Alcalde Bessia, Fabricio

A Sub-electron-noise Skipper-CCD Readout ASIC with Improved Channel-to-channel Isolation and an Integrated Cryogenic Voltage Reference

The MIDNA application specific integrated circuits (ASICs) are a series of skipper-CCD readout chips fabricated in a 65 nm low-power CMOS process that implement a correlated double sampling signal processing chain based on dual-slope integrators. They are capable of working from room to cryogenic temperatures, down to 84 K. The present iteration of the ASIC has been fabricated including several design updates and the addition of an on-chip voltage reference, resulting in improved performance. This work presents the main vulnerabilities solved, the changes carried out, and the resulting performance benefits. Measurements with a skipper-CCD and the ASIC at 140 K showed that the single-electron resolution can be reached by averaging the measured charge in the analog domain using the analog pile-up technique with a readout noise as low as 0.11 erms of equivalent charge for 1200 samples. The channel-to-channel crosstalk was also characterized showing values better than -62 dB.

Alcalde Bessia, Fabricio