Search NASA⌕ Search

SEARCH · Search NASA

Results for “SEMICONDUCTOR DEVICE”

Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

Quote a phrase for an exact phrase match. Source license links do not imply unrestricted reuse.

At least 37 records · Page 2
All sourcesNASA NTRSDOE OSTI
DOE OSTI2013

Method to determine the position-dependant metal correction factor for dose-rate equivalent laser testing of semiconductor devices

A method reconstructs the charge collection from regions beneath opaque metallization of a semiconductor device, as determined from focused laser charge collection response images, and thereby derives a dose-rate dependent correction factor for subsequent broad-area, dose-rate equivalent, laser measurements. The position- and dose-rate dependencies of the charge-collection magnitude of the device are determined empirically and can be combined with a digital reconstruction methodology to derive an accurate metal-correction factor that permits subsequent absolute dose-rate response measurements to be derived from laser measurements alone. Broad-area laser dose-rate testing can thereby be used to accurately determine the peak transient current, dose-rate response of semiconductor devices to penetrating electron, gamma- and x-ray irradiation.

75 CONDENSED MATTER PHYSICS, SUPERCONDUCTIVITY AND↗
DOE OSTI2015

Semiconductor devices having a recessed electrode structure

An electrode structure is described in which conductive regions are recessed into a semiconductor region. Trenches may be formed in a semiconductor region, such that conductive regions can be formed in the trenches. The electrode structure may be used in semiconductor devices such as field effect transistors or diodes. Nitride-based power semiconductor devices are described including such an electrode structure, which can reduce leakage current and otherwise improve performance.

32 ENERGY CONSERVATION, CONSUMPTION, AND UTILIZATI↗
DOE OSTI2023

Semiconductor device and inverter

In an embodiment, a semiconductor device is provided that includes a lateral transistor device having a source, a drain and a gate, and a monolithically integrated capacitor coupled between the gate and the drain.

Haeberlen, Oliver↗
DOE OSTI2014

Reproducible bipolar resistive switching in entire nitride AlN/n-GaN metal-insulator-semiconductor device and its mechanism

Reproducible bipolar resistive switching characteristics are demonstrated in entire nitride AlN/n-GaN metal-insulator-semiconductor devices. The mechanism involved confirms to trap-controlled space charge limited current theory and can be attributed to the nitrogen vacancies of AlN serving as electron traps that form/rupture electron transport channel by trapping/detrapping electrons. This study will lead to the development of in-situ growth of group-III nitrides by metal-organic chemical vapor deposition as a candidate for next-generation nonvolatile memory device. Moreover, it will be benefit to structure monolithic integrated one-transistor-one-resistor memory with nitride high electron mobility transistors.

71 CLASSICAL AND QUANTUM MECHANICS, GENERAL PHYSIC↗
DOE OSTI2014

Accumulation capacitance frequency dispersion of III-V metal-insulator-semiconductor devices due to disorder induced gap states

The origin of the anomalous frequency dispersion in accumulation capacitance of metal-insulator-semiconductor devices on InGaAs and InP substrates is investigated using modeling, electrical characterization, and chemical characterization. A comparison of the border trap model and the disorder induced gap state model for frequency dispersion is performed. The fitting of both models to experimental data indicate that the defects responsible for the measured dispersion are within approximately 0.8 nm of the surface of the crystalline semiconductor. The correlation between the spectroscopically detected bonding states at the dielectric/III-V interface, the interfacial defect density determined using capacitance-voltage, and modeled capacitance-voltage response strongly suggests that these defects are associated with the disruption of the III-V atomic bonding and not border traps associated with bonding defects within the high-k dielectric.

75 CONDENSED MATTER PHYSICS, SUPERCONDUCTIVITY AND↗
DOE OSTI2025

Real-Time Lifetime Prediction of Semiconductor Devices Using Hardware-in-the-Loop

This paper presents a unique approach to enable real-time lifespan prediction of semiconductor power modules using a Hardware-in-the-Loop (HIL) system. By integrating the module's overall loss characteristics-specifically switching and conduction losses-with a thermoelectric model of the thermal management system, this research demonstrates that the model can dynamically estimates the junction temperature profile of the semiconductor devices in response to a changing torque demand profile for the motor drive system. This capability enables continuous monitoring of the module's operational time and cumulative stress induced on the devices to compute accumulated remaining lifetime or time-to-failure (TTF). This study provides an architectural framework for the HIL system with high-fidelity component models of multiple physical domains, allowing simulation of dynamic behaviors of a closely-coupled motor drive system. The advanced real-time computation and measurement functionalities of the HIL system allow for both dynamic lifetime calculations based on simulated data and aggregate lifetime predictions utilizing historical data. Moreover, this paper details an algorithm that not only computes cumulative damage but also synthesizes these data into a comprehensive aggregated lifetime metric. This methodology can enhance the maintenance scheduling strategies and operational reliability of semiconductor devices in critical applications, ultimately extending their service life while optimizing performance.

hardware-in-the-loop (HIL)↗
DOE OSTI2017

Resistive field structures for semiconductor devices and uses therof

The present disclosure relates to resistive field structures that provide improved electric field profiles when used with a semiconductor device. In particular, the resistive field structures provide a uniform electric field profile, thereby enhancing breakdown voltage and improving reliability. In example, the structure is a field cage that is configured to be resistive, in which the potential changes significantly over the distance of the cage. In another example, the structure is a resistive field plate. Using these resistive field structures, the characteristics of the electric field profile can be independently modulated from the physical parameters of the semiconductor device. Additional methods and architectures are described herein.

36 MATERIALS SCIENCE↗
DOE OSTI2016

Methods for dry etching semiconductor devices

The present invention provides methods for etching semiconductor devices, such aluminum nitride resonators. The methods herein allow for devices having improved etch profiles, such that nearly vertical sidewalls can be obtained. In some examples, the method employs a dry etch step with a primary etchant gas that omits BCl.sub.3, a common additive.

36 MATERIALS SCIENCE↗
DOE OSTI2018

High voltage semiconductor devices and methods of making the devices

Metal-oxide-semiconductor field-effect transistor (MOSFET) devices are described which have a p-type region between the p-type well regions of the device. The p-type region can be either floating or connected to the p-type well regions by additional p-type regions. MOSFET devices are also described which have one or more p-type regions connecting the p-type well regions of the device. The p-type well regions can be arranged in a various geometric arrangements including square, diamond and hexagonal. Methods of making the devices are also described.

36 MATERIALS SCIENCE↗
DOE OSTI2017

neutron-Induced Failures in semiconductor Devices

Single Event Effects are a very significant failure mode in modern semiconductor devices that may limit their reliability. Accelerated testing is important for semiconductor industry. Considerable more work is needed in this field to mitigate the problem. Mitigation of this problem will probably come from Physicists and Electrical Engineers working together

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗
DOE OSTI2015

Damage free Ar ion plasma surface treatment on In{sub 0.53}Ga{sub 0.47}As-on-silicon metal-oxide-semiconductor device

In this paper, we investigated the effect of in-situ Ar ion plasma surface pre-treatment in order to improve the interface properties of In{sub 0.53}Ga{sub 0.47}As for high-κ top-gate oxide deposition. X-ray photoelectron spectroscopy (XPS) and metal-oxide-semiconductor capacitors (MOSCAPs) demonstrate that Ar ion treatment removes the native oxide on In{sub 0.53}Ga{sub 0.47}As. The XPS spectra of Ar treated In{sub 0.53}Ga{sub 0.47}As show a decrease in the AsO{sub x} and GaO{sub x} signal intensities, and the MOSCAPs show higher accumulation capacitance (C{sub acc}), along with reduced frequency dispersion. In addition, Ar treatment is found to suppress the interface trap density (D{sub it}), which thereby led to a reduction in the threshold voltage (V{sub th}) degradation during constant voltage stress and relaxation. These results outline the potential of surface treatment for III-V channel metal-oxide-semiconductor devices and application to non-planar device process.

71 CLASSICAL AND QUANTUM MECHANICS, GENERAL PHYSIC↗
DOE OSTI2023

Two-dimensional perovskite heterostructures for single crystal semiconductor devices

Two-dimensional (2D) perovskites have gained much attention lately owing to their excellent optoelectronic properties, chemical tunability, and environmental stability. Multiple methods have been devised to synthesize high quality 2D perovskite single crystals, and recent progress in fabricating its heterostructures is notable as well. In particular, with growing interest in 2D van der Waals heterostructures, 2D perovskites have become a strong candidate as a new building block for heterostructures to reveal unique physical properties across different interfaces. Until now, various heterostructure devices of 2D perovskite single crystals with other types of 2D materials such as transition metal dichalcogenides (TMDs) and graphene have been studied, which have shown intriguing results including interlayer excitons and enhanced electronic properties. Here, we introduce various synthetic approaches to realize 2D perovskite single crystals and unique characteristics of their single crystal heterostructures fabricated with precision, possessing sharp interfaces. Moreover, recent studies of semiconductor devices based on 2D perovskite single crystal heterostructures are discussed in-depth. New perspectives to further the horizon in the field of 2D perovskite heterostructures are suggested in this work including the consideration of metal–2D material van der Waals contact, application of dry transfer techniques, electric bias driven ion diffusion studies, and nanocrystal array fabrication. 2D perovskite heterostructure single crystal devices factoring in these novel perspectives will further uncover the true potential of these materials for highly efficient and stable semiconductor devices.

Physics↗
DOE OSTI2014

Neutron-Induced Failures in Semiconductor Devices [Slides]

Single Event Effects are a very significant failure mode in modern semiconductor devices that may limit their reliability. Accelerated testing is important for semiconductor industry, so considerably more work is needed in this field to mitigate the problem. Mitigation of this problem will probably come from Nuclear Scientists and Electrical Engineers working together.

42 ENGINEERING↗
DOE OSTI2013

Improved interfacial and electrical properties of vanadyl-phthalocyanine metal-insulator-semiconductor devices with silicon nitride as gate insulator

We have investigated the interfacial and electrical properties of vanadyl-phthalocyanine (VOPc) metal-insulator-semiconductor devices by the measurement of capacitance and conductance. The devices have been fabricated on ordered para-sexiphenyl (p-6P) layer with silicon nitride (SiN{sub x}) as gate insulator. The VOPc/p-6P/SiN{sub x} devices have shown a negligible hysteresis, low series resistance, and high operated frequency. Bulk traps have been distinguished from interface traps by two loss peaks in conductance measurement. Trap densities and distribution of trap energy level have been obtained. The improved properties indicate that VOPc/ p-6P devices with SiN{sub x} insulator hold a great promise of application in flexible displays.

36 MATERIALS SCIENCE↗
DOE OSTI2013

22nd RD50 Workshop on Radiation Hard Semiconductor Devices for High Luminosity Colliders

The 22nd RD50 Workshop on Radiation Hard Semiconductor Devices for High Luminosity Colliders was held on the campus of the University of New Mexico from June 3 to 5, 2013. This was the first North American meeting of the series going back to 2001. The sessions covered Material and Defect Characterization, Detector Characterization, Full Detector Systems, and New Structures. A half-day mini-workshop was allocated to radiation damage at LHC experiments. All talks are archived permanently available to the public at rd50.web.cern.ch. Financial support was used for room rental audiovisual equipment rental, and document preparation services.

47 OTHER INSTRUMENTATION↗
DOE OSTI2014

High precision two-dimensional strain mapping in semiconductor devices using nanobeam electron diffraction in the transmission electron microscope

A classical method used to characterize the strain in modern semiconductor devices is nanobeam diffraction (NBD) in the transmission electron microscope. One challenge for this method lies in the fact that the smaller the beam becomes, the more difficult it becomes to analyze the resulting diffraction spot pattern. We show that a carefully designed fitting algorithm enables us to reduce the sampling area for the diffraction patterns on the camera chip dramatically (∼1/16) compared to traditional settings without significant loss of precision. The resulting lower magnification of the spot pattern permits the presence of an annular dark field detector, which in turn makes the recording of images for drift correction during NBD acquisition possible. Thus, the reduced sampling size allows acquisition of drift corrected NBD 2D strain maps of up to 3000 pixels while maintaining a precision of better than 0.07%. As an example, we show NBD strain maps of a modern field effect transistor (FET) device. A special filtering feature used in the analysis makes it is possible to measure strain in silicon devices even in the presence of other crystalline materials covering the probed area, which is important for the characterization of the next generation of devices (Fin-FETs).

75 CONDENSED MATTER PHYSICS, SUPERCONDUCTIVITY AND↗
DOE OSTI2015

Defect state passivation at III-V oxide interfaces for complementary metal–oxide–semiconductor devices

The paper describes the reasons for the greater difficulty in the passivation of interface defects of III–V semiconductors like GaAs. These include the more complex reconstructions of the starting surface which already possess defect configurations, the possibility of injecting As antisites into the substrate which give rise to gap states, and the need to avoid As-As bonds and As dangling bonds which give rise to gap states. The nature of likely defect configurations in terms of their electronic structure is described. The benefits of diffusion barriers and surface nitridation are discussed.

71 CLASSICAL AND QUANTUM MECHANICS, GENERAL PHYSIC↗
DOE OSTI2021

A High-Efficiency Isolated PFC AC-DC Topology with Reduced Number of Semiconductor Devices

A new three-level isolated ac-dc power factor correction (PFC) topology with a minimum number of semiconductor devices is the focus of this paper. This topology provides a high input power factor (PF), soft-switching, and higher efficiency than existing isolated ac-dc converters. Furthermore, the proposed circuit has lower voltage rating requirements for the secondary side devices, which leads to a lower total cost and minimizes total converter losses. This article presents a theoretical analysis describing the complete characterization of this new topology, and experimental results on a 1-kW prototype showing high PF and efficiency throughout the operating range.

42 ENGINEERING↗