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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 37 records · Page 2
All sourcesNASA NTRSDOE OSTI
DOE OSTI2024

FET Junction Temperature Monitoring Using Novel On-Chip Solution

A novel junction temperature monitoring sensor is proposed and experimentally demonstrated for application in MOS-gate power devices. The sensor is created using the polycide gate electrode layer of the devices to create a temperature-sensitive resistor without any additional fabrication steps. The resistor is located on the field oxide with one end grounded at the device reference terminal to isolate it from the device current and voltage transients. It allows in-situ monitoring of the device junction temperature during active circuit operation. The technology has been implemented to monitor the junction temperature of Silicon Carbide Junction Barrier Schottky Field Effect Transistors (SiC JBSFETs) with the bi-directional FET (BiDFET).

Bidirectional switches, SiC bidirectional FET, BiD↗
DOE OSTI2020

Electrowetting‐Mediated Transport to Produce Electrochemical Transistor Action in Nanopore Electrode Arrays

Abstract Understanding water behavior in confined volumes is important in applications ranging from water purification to healthcare devices. Especially relevant are wetting and dewetting phenomena which can be switched by external stimuli, such as light and electric fields. Here, these behaviors are exploited for electrochemical processing by voltage‐directed ion transport in nanochannels contained within nanopore arrays in which each nanopore presents three electrodes. The top and middle electrodes (TE and ME) are in direct contact with the nanopore volume, but the bottom electrode (BE) is buried beneath a 70 nm silicon nitride (SiN x ) insulating layer. Electrochemical transistor operation is realized when small, defect‐mediated channels are opened in the SiN x . These defect channels exhibit voltage‐driven wetting that mediates the mass transport of redox species to/from the BE. When BE is held at a potential maintaining the defect channels in the wetted state, setting the potential of ME at either positive or negative overpotential results in strong electrochemical rectification with rectification factors up to 440. By directing the voltage‐induced electrowetting of defect channels, these three‐electrode nanopore structures can achieve precise gating and ion/molecule separation, and, as such, may be useful for applications such as water purification and drug delivery.

Kwon, Seung‐Ryong↗
DOE OSTI2021

Radiation-Hardened Instrumentation, Sensors and Electronics

To assist the US Department of Energy in defining a course for Office of Nuclear Energy–funded radiation-hardened (rad-hard) electronics research, Oak Ridge National Laboratory (ORNL) will focus on three main tasks in FY21. The first task will investigate the survivability of silicon junction-gate field-effect transistors (Si-JFETs) through a 100 Mrad total ionizing dose (TID) experiment and report the test results. The second task will investigate wide bandgap (WBG)-based JFET devices and sources. The third task is an investigation into commercially available systems and components and will be performed to determine whether a standardized list of devices can be identified for reactor instrumentation application. If the devices are feasible, then this list will provide direction to designers and equipment suppliers for selection of components to meet specific reactor requirements.

42 ENGINEERING↗
DOE OSTI2020

High‐Performance Zinc Tin Oxide TFTs with Active Layers Deposited by Atomic Layer Deposition

Abstract New deposition techniques for amorphous oxide semiconductors compatible with silicon back end of line manufacturing are needed for 3D monolithic integration of thin‐film electronics. Here, three atomic layer deposition (ALD) processes are compared for the fabrication of amorphous zinc tin oxide (ZTO) channels in bottom‐gate, top‐contact n‐channel transistors. As‐deposited ZTO films, made by ALD at 150–200 °C, exhibit semiconducting, enhancement‐mode behavior with electron mobility as high as 13 cm 2 V −1 s −1 , due to a low density of oxygen‐related defects. ZTO deposited at 200 °C using a hybrid thermal‐plasma ALD process with an optimal tin composition of 21%, post‐annealed at 400 °C, shows excellent performance with a record high mobility of 22.1 cm 2 V –1 s –1 and a subthreshold slope of 0.29 V dec –1 . Increasing the deposition temperature and performing post‐deposition anneals at 300–500 °C lead to an increased density of the X‐ray amorphous ZTO film, improving its electrical properties. By optimizing the ZTO active layer thickness and using a high‐ k gate insulator (ALD Al 2 O 3 ), the transistor switching voltage is lowered, enabling electrical compatibility with silicon integrated circuits. This work opens the possibility of monolithic integration of ALD ZTO‐based thin‐film electronics with silicon integrated circuits or onto large‐area flexible substrates.

Allemang, Christopher R.↗
DOE OSTI2024

A nanoscale photonic thermal transistor for sub-second heat flow switching

Abstract Control of heat flow is critical for thermal logic devices and thermal management and has been explored theoretically. However, experimental progress on active control of heat flow has been limited. Here, we describe a nanoscale radiative thermal transistor that comprises of a hot source and a cold drain (both are ~250 nm-thick silicon nitride membranes), which are analogous to the source and drain electrodes of a transistor. The source and drain are in close proximity to a vanadium oxide (VO x )-based planar gate electrode, whose dielectric properties can be adjusted by changing its temperature. We demonstrate that when the gate is located close ( < ~1 µm) to the source-drain device and undergoes a metal-insulator transition, the radiative heat transfer between the source and drain can be changed by a factor of three. More importantly, our nanomembrane-based thermal transistor features fast switching times ( ~ 500 ms as opposed to minutes for past three-terminal thermal transistors) due to its small thermal mass. Our experiments are supported by detailed calculations that highlight the mechanism of thermal modulation. We anticipate that the advances reported here will open new opportunities for designing thermal circuits or thermal logic devices for advanced thermal management.

42 ENGINEERING↗
DOE OSTI2025

Reduced thermal resistance of Al-rich AlGaN HEMTs via top-side diamond integration

We report back-end-of-line growth of nanocrystalline diamond (NCD) on ultrawide bandgap (UWBG) high Al content aluminum gallium nitride (AlGaN) channel high electron mobility transistors for thermal management. A thin (∼15 nm) silicon nitride (SiN x ) interlayer was deposited to protect the device surface before performing a low temperature (500 °C) NCD growth process in an attempt to protect the gates on these fully fabricated devices. Notably, atomic force microscopy showed that the maximum lateral grain size exceeded 300 nm even though the film thickness was ∼250 nm. Comparing electrical (DC) performance before and after NCD growth, the gate leakage increased by ∼10 2 after NCD growth. Despite the lower NCD growth temperature, intermixing of the Ni and Au was observed in the Schottky gate metal stack; however, we believe there is another mechanism, possibly hydrogen-related, that is responsible for the measured increase in gate leakage. Regarding thermal management, the device-level thermal resistance (quantified using the average gate temperature rise measured by thermoreflectance imaging) was reduced by 29% through the incorporation of the top-side diamond film. Using time-domain thermoreflectance, the thermal conductivity of the ≈250 nm thick NCD film was measured to be 45 ± 25 W m −1 K −1 . This is expected to be at least 5× greater than the thermal conductivity of the thin disordered AlGaN alloy. There could also be a coupled electrothermal component contributing to the reduced temperature rise from electric field spreading and consequent heat spreading. This study demonstrates a promising first step toward device-level thermal management of high power UWBG Al-rich AlGaN devices.

Lundh, James Spencer [U.S. Naval Research Laborato↗
DOE OSTI2025

Rapid Prototyping Techniques for Organic Direct-Bonded-Copper Power Modules

Organic Direct-Bonded-Copper (ODBC) is a novel packaging technology for power modules which allows higher flexibility in layout design. In this work, a set of rapid prototyping techniques are developed for ODBC modules based on a polyimide dielectric material. These techniques enable fast and low-cost fabrication of modules with 3-Dimensional (3D) layout features. An example half-bridge (HB) silicon carbide (SiC) metal oxide semiconductor field effect transistor (MOSFET) module is designed and prototyped using the proposed techniques aiming at ultra-low power loop inductance. Finite element analysis (FEA)-circuit co-simulations results and experimental results validate an approximately 0.71nH power loop inductance for the example module design.

36 MATERIALS SCIENCE↗
DOE OSTI2023

PCB-on-DBC GaN Power Module Design with High-Density Integration and Double-Sided Cooling

Lateral gallium nitride (GaN) high-electron-mobility transistors (HEMTs) present better electrical characteristics compared to silicon or silicon carbide devices such as high switching speed and low gate charge, but also present additional challenges on the module design. Here, this paper discusses a high-density GaN power module with double-sided cooling, low inductance, on-package decoupling capacitors, and integrated gate drivers. The GaN dies as well as the gate drive are sandwiched between the printed circuit board (PCB) and direct bonded copper (DBC) substrate to achieve compact loop and double-sided cooling effect. Design considerations and thermal performance are analyzed. A module assembly procedure is presented utilizing the layer-by-layer attachment process. Finally, a 2.7 cm x 1.8 cm half-bridge GaN power module is fabricated and tested, achieving a low power-loop inductance of 1.03 nH, and the overshoot voltage of the switching waveform is less than 5% under a 400-V/25-A double-pulse test. The thermal resistance is 0.32 K/W, verified by simulation and experimental results. The design and assembly process can be generalized and applied to high power applications to achieve high power density and high performance.

37 INORGANIC, ORGANIC, PHYSICAL, AND ANALYTICAL CH↗
DOE OSTI2022

Drivers for paralleled semiconductor switches

An apparatus includes a plurality of parallel-connected semiconductor switches (e.g., silicon carbide (SiC) metal oxide semiconductor field effect transistors (MOSFETs) or other wide-bandgap semiconductor switches) and a plurality of driver circuits having outputs configured to be coupled to control terminals of respective ones of the plurality of semiconductor switches and configured to drive the parallel-connected semiconductor switches responsive to a common switch state control signal. The driver circuits may have respective different power supplies, which may be adjustable. Respective output resistors may couple respective ones of the driver circuits to respective ones of the semiconductor switches. The output resistors may be adjustable.

Nojima, Geraldo↗
DOE OSTI2024

Power Module Precursors and Prognostics

This project focuses on finding and utilizing electrical properties (precursors) of power electronic devices and modules whose changes have strong correlations with different modes and levels of degradations in order to realize online and lightweight state of health evaluation and fault diagnosis. Results from this project will contribute to higher safety, reliability, and power density of power electronic components. The approaches mainly include reviewing academic literature and industry practices for state of the art precursor identification and extraction, accelerated life cycles (ALC) of various power modules to create different degradations in-house, and developing techniques for gate-driver-integratable precursor detection circuit. In FY24, the results includes two sets of definitively detected aging precursors (on-state resistance and gate threshold voltage) for two sets of power modules respectively, controlled accelerated lifetime cycling of multiple silicon carbide (SiC) metal-oxide-semiconductor field-effect transistor (MOSFET) modules, and the development and validation of a gate voltage detection system.

ADVANCED PROPULSION SYSTEMS↗
DOE OSTI2024

A Multi-Metrics In Situ Aging Detector for SiC Power MOSFET Modules with Full Driver-Integration Capability

In this paper, the concept and prototype of an aging detector for silicon carbide (SiC) power metal oxide semiconductor field effect transistor (MOSFET) are proposed and described. It leverages the resonant peak values of gate-source voltage at different instants during the switching transients to decode the change of multiple aging indicators, such as the increases of on-state resistance and threshold voltage. Modeling-based analysis is conducted to support the idea. The detector can be fully integrated into gate drivers without any additional connection to the power stage and is functional during normal power stage operation. A prototype unit was built, and preliminary tests were conducted to validate the idea and the practicality of the detector.

aging↗
DOE OSTI2020

Graphite-Embedded High-Performance Insulated Metal Substrate for Wide-Bandgap Power Modules

Emerging wide-bandgap (WBG) semiconductor devices such as silicon carbide (SiC) metal–oxide semiconductor field-effect transistors (MOSFETs) and gallium nitride high-electron-mobility transistors can handle high power in reduced semiconductor areas better than conventional Si-based devices owing to superior material properties. With increased power loss density in a WBG-based converter and reduced die size in power modules, thermal management of power devices must be optimized for high performance. Here, we present a graphite-embedded insulated metal substrate (thermally-annealed-pyrolytic-graphite-embedded insulated metal substrate—IMSwTPG) designed for WBG power modules. Theoretical thermal performance analysis of graphite-embedded metal cores is presented, with design details for IMSwTPG with embedded graphite to replace a direct-bonded copper (DBC) substrate. The proposed IMSwTPG is compared with an aluminum nitride-based DBC substrate using finite-element thermal analysis for steady-state and transient thermal performance. The solutions’ thermal performances are compared under different coolant temperature and thermal loading conditions, and the proposed substrate's electrical performance is validated with static and dynamic characterization. Using graphite-embedded substrates, junction-to-case thermal resistance of SiC MOSFETs can be reduced up to 17%, and device current density can be increased by 10%, regardless of the thermal management strategy used to cool the substrate. Reduced transient thermal impedance of up to 40% of dies owing to increased heat capacity is validated in transient thermal simulations and experiments. The half-bridge power module's electrical performance is evaluated for on -state resistance, switching performance, and switching loss at three junction temperature conditions. The proposed substrate solution has minimal impact on conduction and switching performance of SiC MOSFETs.

42 ENGINEERING↗
DOE OSTI2020

Design, Analysis, Comparison, and Experimental Validation of Insulated Metal Substrates for High-Power Wide-Bandgap Power Modules

Direct bonded copper (DBC) substrates used in power modules have limited heat spreading and manufacturing capability due to ceramic properties and manufacturing technology. The ceramic and copper bonding is also subject to high mechanical stress due to coefficient of thermal expansion mismatch between the copper and the ceramic. For wide-bandgap (WBG) devices, it is of interest exploring new substrate technologies that can overcome some of the challenges of direct bonded copper substrates. In this technical paper, the design, analysis, and comparison of insulated metal substrates (IMSs) for high-power wide-bandgap semiconductor-based power modules are discussed. This paper starts with technical description and discussion of state-of-the-art DBC substrates with different ceramic insulators such as aluminum nitride (AlN), Al 2 O 3 , and Si 3 N 4 . Next, an introduction of IMSs and their material properties, and a design approach for SiC (silicon carbide) metal-oxide-semiconductor field-effect transistor (MOSFET)-based power modules for high-power applications is provided. The influence of dielectric thickness on the power handling capability of the substrate are also discussed. The designed IMS and DBC substrates were characterized in terms of steady-state and transient thermal performance using finite element simulation. Finally, the performance of the IMS and DBC are validated in an experimental setup under different loading and cooling temperature conditions. We report the simulation and experimental results showed that the IMS can provide high steady-state thermal performance for high-power modules based on SiC MOSFETs. Furthermore, the IMS provided enhanced transient thermal performance, which provided a reduced junction temperature when the module is operated at low fundamental output frequencies in traction drive systems.

42 ENGINEERING↗
DOE OSTI2022

Thermal Optimization of a Silicon Carbide, Half-Bridge Power Module

This project describes the modeling process to design the packaging and heat exchanger for a half-bridge wide-bandgap (WBG) power semiconductor module. The module uses two silicon carbide, metal-oxide-semiconductor field-effect transistor (MOSFET) devices per switch position that are soldered to an aluminum nitride, direct-bond copper (DBC) substrate. A baseplate cooling configuration (e.g., no thermal grease) is used along with a water-ethylene glycol, jet-impingement-style heat exchanger. The heat exchanger was designed to be fabricated using prototyping equipment from the National Renewable Energy Laboratory, complies with automotive standards (for minimal channel sizes, flow rates, and coolant), and considers reliability aspects (i.e., erosion/corrosion). Device-scale computational fluid dynamics (CFD) is used first to design the slot jet impingement cooling configuration and compute the effective heat transfer coefficient (HTC) of the concept. The computed HTCs are then used as boundary conditions for a finite element study to optimize the package geometry (e.g., device layout and baseplate thickness) to minimize thermal resistance and minimize temperature variation between the module's four devices. Finally, a fluid manifold is designed to generate the slot jets and cool the devices. Module-scale CFD predicts a relatively low junction-to-fluid thermal resistance of 16.7 mm2 K/W, a 1.4 degrees C temperature variation between devices, and a total pressure drop of 5,860 Pa (0.85 psi) for the design. The thermal resistance of the module design is about 67% lower than the 2015 BMW i3 power electronics/modules thermal resistance.

DIRECT ENERGY CONVERSION↗
DOE OSTI2020

Advanced CMOS Reliability Update: Sub 20nm FinFET Assessment

Advances in FinFET design and fabrication enable manufacturing of denser, more compact integrated circuits (ICs) with substantially reduced leakage while shortening the channel-lengths. The same stress-induced leakage and breakdown degradation mechanisms that affect planar transistors also impact FinFET devices. Reliability concerns such as Bias Temperature Instability (BTI), Time Dependent Dielectric Breakdown (TDDB), and Hot Carrier Injection (HCI) become very important with changes to transistor geometry and fin sidewall crystal orientation. Recent testing has shown that FinFETs respond differently to radiation (radiation effects such as total ionizing dose) when compared to planar transistors. These reliability and radiation effects issues become very important when changing transistor geometry and scaling FinFETs towards smaller feature sizes (22-nm, 16-nm, 14- nm, 10-nm, and smaller critical dimensions). The comparable 2019 state of the art transistor densities in current high-volume manufacturing silicon-based foundries is 7-nm (ISMC, Samsung) and 10-nm (Intel) [www.anandtech.com,fuse.wikichip.org]. Released products include supporting components for the cellphone and commercial microprocessor markets respectively. Extensive development in the foundry industry is driving to a 5-nm technology node in late 2020.

47 OTHER INSTRUMENTATION↗
DOE OSTI2025

Annihilation-limited long-range exciton transport in high-mobility conjugated copolymer films

A combination of ultrafast, long-range, and low-loss excitation energy transfer from the photoreceptor location to a functionally active site is essential for cost-effective polymeric semiconductors. Delocalized electronic wavefunctions along π-conjugated polymer (CP) backbone can enable efficient intrachain transport, while interchain transport is generally thought slow and lossy due to weak chain–chain interactions. In contrast to the conventional strategy of mitigating structural disorder, amorphous layers of rigid CPs, exemplified by highly planar poly(indacenodithiophene-co-benzothiadiazole) (IDT-BT) donor-accepter copolymer, exhibit trap-free transistor performance and charge-carrier mobilities similar to amorphous silicon. Here, we report long-range exciton transport in HJ -aggregated IDTBT thin-film, in which the competing exciton transport and exciton–exciton annihilation (EEA) dynamics are spectroscopically separated using a phase-cycling-based scheme and shown to depart from the classical diffusion-limited and strong-coupling regime. In the thin film, we find an annihilation-limited mechanism with ≪100% per-encounter annihilation probability, facilitating the minimization of EEA-induced excitation losses. In contrast, excitons on isolated IDTBT chains diffuse over 350 nm with 0.56 cm 2 s −1 diffusivity, before eventually annihilating with unit probability on first contact. We complement the pump–probe studies with temperature-dependent photocurrent and EEA measurements from 295 K to 77 K and find a remarkable correspondence of annihilation rate and photocurrent activation energies in the 140 K to 295 K temperature range.

Shi, Yuping (ORCID:0000000318289415)↗
DOE OSTI2025

Low Cost High-Performance HRE-Free 3-in-1 Electric Drive Unit

The project team completed work to expand upon American Axle & Manufacturing’s (AAM) baseline technology and develop a high-speed, AC induction electric drive unit (EDU) with total direct-oil-cooling and integrated power electronics. The project accelerated advancements in EDU technology by allowing AAM to build upon the progress made in developing the underlying baseline technologies. The following seven improvements to AAM’s baseline technology were implemented in this research and development program: 1) Increased speed (30k RPM) AC induction motor, 2) Silver-sintering of discrete silicon carbide (SiC) metal-oxide-semiconductor field-effect transistors (MOSFET) to heat sinks, 3) Electrically insulated rotor bars, 4) Optimized lamination steel, 5) EDU-integrated 650VDC inverter package, 6) Over-molded stator with molded liners, and 7) 650VDC power-dense stator design. The successful development of the technology resulted in a meaningful cost reduction for EDU systems in the market. Coupled with falling battery system costs, lower EDU costs will likely accelerate the market acceptance and related production scaling of battery electric vehicles. The objective of this project was to research, develop, and test a Heavy Rare Earth (HRE)-free 3-In-1 electric drive unit (EDU) that has class leading power density and cost. The key technologies to be developed were anticipated to meet or exceed the Department of Energy (DOE) targets of a cost ≤ $\$$7/kilowatt (kW), power density ≥ 12 kW/liter, and operating voltage ≥ 600 VDC.

33 ADVANCED PROPULSION SYSTEMS↗
DOE OSTI2021

Silicon carbide power inverter/rectifier for electric machines

The present disclosure involves a two stage inverter, a system for electrical power conversation, and a method of converting electrical power using silicon carbide (SiC) metal-oxide-semiconductor field-effect transistors (MOSFETs). One example implementation includes using two or more SiC MOSFETs in series with each MOSFET having a gate terminal for triggering a state switch between an on (conducting) and off (non-conducting) state of the MOSFET. An AC terminal is connected between the series SiC MOSFETS, and the series SiC MOSFETs are connected across a DC bus and in parallel with one or more capacitors.

Shenoy, Suratkal P.↗