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All sourcesNASA NTRSDOE OSTI
NASA NTRS2005

PDSOI and Radiation Effects: An Overview

Bulk silicon substrates are a common characteristic of nearly all commercial, Complementary Metal-Oxide-Semiconductor (CMOS), integrated circuits. These devices operate well on Earth, but are not so well received in the space environment. An alternative to bulk CMOS is the Silicon-On-Insulator (SOI), in which a &electric isolates the device layer from the substrate. SO1 behavior in the space environment has certain inherent advantages over bulk, a primary factor in its long-time appeal to space-flight IC designers. The discussion will investigate the behavior of the Partially-Depleted SO1 (PDSOI) device with respect to some of the more common space radiation effects: Total Ionized Dose (TID), Single-Event Upsets (SEUs), and Single-Event Latchup (SEL). Test and simulation results from the literature, bulk and epitaxial comparisons facilitate reinforcement of PDSOI radiation characteristics.

Forgione, Joshua B.↗
NASA NTRS2006

Large format imaging arrays for the Atacama Cosmology Telescope

We describe progress in the fabrication, characterization, and production of detector arrays for the Atacama Cosmology Telescope (ACT). The completed ACT instrument is specified to image simultaneously at 145, 225, and 265 GHz using three 32x32 filled arrays of superconducting transition edge sensors (TES) read out with time-division-multiplexed SQUID amplifiers. We present details of the pixel design and testing including the optimization of the electrical parameters for multiplexed readout. Using geometric noise suppression and careful tuning of operation temperature and device bias resistance, the excess noise in the TES devices is balanced with detector speed for interfacing with the ACT optics. The design also accounts for practical tolerances such as transition temperature gradients and scatter that occur in the production of multiple wafers to populate fully the kilopixel cameras. We have developed an implanted absorber layer compatible with our silicon-on-insulator process that allows for tunable optical resistance with requisite on-wafer uniformity and wafer-to-wafer reproducibility. Arrays of 32 elements have been tested in the laboratory environment including electrical, optical, and multiplexed performance. Given this pixel design, optical tests and modeling are used to predict the performance of the filled array under anticipated viewing conditions. Integration of the filled array of pixels with a tuned backshort and dielectric plate in front of the array maximize absorption and the focal plane and suppress reflections. A mechanical design for the build of the full structure is completed and we report on progress toward the construction of a prototype array for first light on the ACT.

Chervenak, J. A.↗
NASA NTRS2006

Single-Event Upset and Scaling Trends in New Generation of the Commercial SOI PowerPC Microprocessors

SEU from heavy-ions is measured for SOI PowerPC microprocessors. Results for 0.13 micron PowerPC with 1.1V core voltages increases over 1.3V versions. This suggests that improvement in SEU for scaled devices may be reversed. In recent years there has been interest in the possible use of unhardened commercial microprocessors in space because of their superior performance compared to hardened processors. However, unhardened devices are susceptible to upset from radiation space. More information is needed on how they respond to radiation before they can be used in space. Only a limited number of advanced microprocessors have been subjected to radiation tests, which are designed with lower clock frequencies and higher internal core voltage voltages than recent devices [1-6]. However the trend for commercial Silicon-on-insulator (SOI) microprocessors is to reduce feature size and internal core voltage and increase the clock frequency. Commercial microprocessors with the PowerPC architecture are now available that use partially depleted SOI processes with feature size of 90 nm and internal core voltage as low as 1.0 V and clock frequency in the GHz range. Previously, we reported SEU measurements for SOI commercial PowerPCs with feature size of 0.18 and 0.13 m [7, 8]. The results showed an order of magnitude reduction in saturated cross section compared to CMOS bulk counterparts. This paper examines SEUs in advanced commercial SOI microprocessors, focusing on SEU sensitivity of D-Cache and hangs with feature size and internal core voltage. Results are presented for the Motorola SOI processor with feature sizes of 0.13 microns and internal core voltages of 1.3 and 1.1 V. These results are compared with results for the Motorola SOI processors with feature size of 0.18 microns and internal core voltage of 1.6 and 1.3 V.

Irom, Farokh↗
NASA NTRS2002

Complemenary body driving - a low voltage analog circuit technique for SOI

This paper describes several analog circuit primitives that utilize the body terminal as a signal port. A cascode current mirror that can operate with an input and output voltage of 200 mV; and a rail-to-rail, constant transconductance gain block capable of 1 V operation are presented. These circuits have been implemented in a standard 0.35~1 partially-depleted Silicon-on-Insulator (PDSOI) CMOS process and should find wide application in next-generation analog circuit designs.

neuro-prosthetic devices cortical signals↗
NASA NTRS1997

Characterization of Semiconductor Materials Using AOTF Instruments

A non-invasive characterization of silicon-on-insulator (SOI) wafers using white light interference measured by an AOTF polarimetric hyperspectral imaging instrument will be presented an an illustration of the technology potential. Experiments provided high resolution thickness maps of both silicon and oxide layers with accuracy and observed optically active imperfections and distributions in the structure.

polarimetric hyperspectral imaging silicon oxide↗
NASA NTRS2006

Single-Event Upset and Scaling Trends in New Generation of the Commercial SOI PowerPC Microprocessors

Single-event upset effects from heavy ions are measured for Motorola silicon-on-insulator (SOI) microprocessor with 90 nm feature sizes. The results are compared with previous results for SOI microprocessors with feature sizes of 130 and 180 nm. The cross section of the 90 nm SOI processors is smaller than results for 130 and 180 nm counterparts, but the threshold is about the same. The scaling of the cross section with reduction of feature size and core voltage for SOI microprocessors is discussed.

silicon on insulator↗
NASA NTRS2007

Interpretation of TEPC Measurements in Space Flights for Radiation Monitoring

For the proper interpretation of radiation data measured in space, the results of integrated radiation transport models were compared with the tissue equivalent proportional counter (TEPC) measurements. TEPC is a simple, time-dependent approach to radiation monitoring for astronauts on board the International Space Station. Another and a newer approach to microdosimetry is the use of silicon-on-insulator (SOI) technology launched on the MidSTAR-1 mission in low Earth orbit (LEO). In the radiation protection practice, the average quality factor of a radiation field is defined as a function of linear energy transfer (LET), Qave(LET). However, TEPC measures the average quality factor as a function of the lineal energy y, Qave(y), defined as the average energy deposition in a volume divided by the average chord length of the volume. The deviation of y from LET is caused by energy straggling, delta-ray escape or entry, and nuclear fragments produced in the detector volume. The response distribution functions of the wall-less and walled TEPCs were calculated from Monte-Carlo track simulations. Using an integrated space radiation model (which includes the transport codes HZETRN and BRYNTRN, and the quantum nuclear interaction model QMSFRG) and the resultant response distribution functions from Monte-Carlo track simulations, we compared model calculations with the walled-TEPC measurements from NASA missions in LEO and made predictions for the lunar and the Mars missions. Good agreement was found for Qave(y) between the model and measured spectra from past NASA missions. The Qave(y) values for the trapped or the solar protons ranged from 1.9-2.5. This over-estimates the Qave(LET) values which ranged from 1.4-1.6. Both quantities increase with shield thickness due to nuclear fragmentation. The Qave(LET) for the complete GCR spectra was found to be 3.5-4.5, while flight TEPCs measured 2.9-3.4 for Qave(y). The GCR values are decreasing with the shield thickness. Our analysis of the measurements of TEPCs can be used for a proper interpretation of observed data of monitoring the space radiation environment.

Kim, Myung-Hee Y.↗
NASA NTRS2007

Comparison of Integrated Radiation Transport Models with TEPC Measurements for the Average Quality Factors in Spaceflights

The purpose of this work is to test our theoretical model for the interpretation of radiation data measured in space. During the space missions astronauts are exposed to the complex field of radiation type and kinetic energies from galactic cosmic rays (GCR), trapped protons, and sometimes solar particle events (SPEs). The tissue equivalent proportional counter (TEPC) is a simple time-dependent approach for radiation monitoring for astronauts on board the International Space Station. Another and a newer approach to Microdosimetry is the use of silicon-on-insulator (SOI) technology launched on the MidSTAR-1 mission in low Earth orbit (LEO). In the radiation protection practice, the average quality factor of a radiation field is defined as a function of linear energy transfer (LET), Q(sub ave)(LET). However, TEPC measures the average quality factor as a function of the lineal energy y, Q(sub ave)(y), defined as the average energy deposition in a volume divided by the average chord length of the volume. Lineal energy, y, deviates from LET due to energy straggling, delta-ray escape or entry, and nuclear fragments produced in the detector volume. Monte Carlo track structure simulation was employed to obtain the response of a TEPC irradiated with charged particle for an equivalent site diameter of 1 micron of wall-less counter. The calculated data of the energy absorption in the wall-less counter were compiled for various y values for several ion types at various discrete projectile energy levels. For the simulation of TEPC response from the mixed radiation environments inside a spacecraft, such as, Space Shuttle and International Space Station, the complete microdosimetric TEPC response, f( y, E, Z), were calculated with the Monte Carlo theoretical results by using the first order Lagrangian interpolation for a monovariate function at a given y value (y = 0.1 keV/micron 5000 keV/micron) at any projectile energy level (E = 0.01 MeV/u to 50,000 MeV/u) of each specific radiation type (Z = 1 to 28). Because the anomalous response has been observed at large event sizes in the experiment due to the escape of energy out of sensitive volume by delta-rays and the entry of delta-rays from the high-density wall into the low-density gas-volume cavity, Monte Carlo simulation was also made for the response of a walled-TEPC with wall thickness 2 mm and density 1 g/cm(exp 3). The radius of cavity was set to 6.35 mm and a gas density 7.874 x 10(exp -5) g/cm(exp 3). The response of the walled- and the wall-less counters were compared. The average quality factor Q(sub ave)(y) for trapped protons on STS-89 demonstrated the good agreement between the model calculations and flight TEPC data as shown. Using an integrated space radiation model (this includes the transport codes HZETRN and BRYNTRN, the quantum nuclear interaction model QMSFRG) and the resultant response distribution functions of walled-TEPC from Monte-Carlo track simulations, we compared model calculations with walled-TEPC measurements from NASA missions in LEO and made predictions for the lunar and the Mars missions. The Q(sub ave)(y) values for the trapped or the solar protons ranged from 1.9-2.5. This over-estimates the Qave(LET) values which ranged from 1.4-1.6. Both quantities increase with shield thickness due to nuclear fragmentation. The Q(sub ave)(LET) for the complete GCR spectra was found to be 3.5-4.5, while flight TEPCs measured 2.9-3.4 for Q(sub ave)(y). The GCR values are decreasing with the shield thickness. Our analysis for a proper interpretation of data supports the use of TEPCs for monitoring space radiation environment.

Kim, Myung-Hee Y.↗
NASA NTRS2006

Frequency Dependence of Single-Event Upset in Highly Advanced PowerPC Microprocessors

Single-event upset effects from heavy ions were measured for Motorola silicon-on-insulator (SOI) microprocessor with 90 nm feature sizes at three frequencies of 500, 1066 and 1600 MHz. Frequency dependence of single-event upsets is discussed. The results of our studies suggest the single-event upset in registers and D-Cache tend to increase with frequency. This might have important implications for the overall single-event upset trend as technology moves toward higher frequencies.

Cyclotron↗
NASA NTRS2007

Design and Fabrication Highlights Enabling a 2 mm, 128 Element Bolometer Array for GISMO

The Backshort-Under-Grid (BUG) superconducting bolometer array architecture is intended to be highly versatile, operating in a large range of wavelengths and background conditions. We have undertaken a three-year program to develop key technologies and processes required to build kilopixel arrays. To validate the basic array design and to demonstrate its applicability for future kilopixel arrays, we have chosen to demonstrate a 128 element bolometer array optimized for 2 mm wavelength using a newly built Goddard instrument, GISMO (Goddard /RAM Superconducting 2-millimeter Observer). The arrays are fabricated using batch wafer processing developed and optimized for high pixel yield, low noise, and high uniformity. The molybdenum-gold superconducting transition edge sensors are fabricated using batch sputter deposition and are patterned using dry etch techniques developed at Goddard. With a detector pitch of 2 mm 8x16 array for GISMO occupies nearly one half of the processing area of a 100 mm silicon-on-insulator starting wafer. Two such arrays are produced from a single wafer along with witness samples for process characterization. To provide thermal isolation for the detector elements, at the end of the process over 90% of the silicon must be removed using deep reactive ion etching techniques. The electrical connections for each bolometer element are patterned on the top edge of the square grid supporting the array. The design considerations unique to GISMO, key fabrication challenges, and laboratory experimental results will be presented.

Allen, Christine↗
NASA NTRS2006

The USNA MIDN Microdosimeter Instrument

This paper describes the MIcroDosimetry iNstrument (MIDN) mission now under development at the United States Naval Academy. The instrument is manifested to fly on the MidSTAR-1 spacecraft, which is the second spacecraft to be developed and launched by the Academy s faculty and midshipmen. Launch is scheduled for 1 September 2006 on an ATLAS-5 launch vehicle. MIDN is a rugged, portable, low power, low mass, solid-state microdosimeter designed to measure in real time the energy distributions of energy deposited by radiation in microscopic volumes. The MIDN microdosimeter sensor is a reverse-biased silicon p-n junction array in a Silicon-On-Insulator (SOI) configuration. Microdosimetric frequency distributions as a function of lineal energies determine the radiation quality factors in support of radiation risk estimation to humans.

Pisacane, V. L.↗
NASA NTRS2007

Assessment of SOI Devices and Circuits at Extreme Temperatures

Electronics designed for use in future NASA space exploration missions are expected to encounter extreme temperatures and wide thermal swings. Such missions include planetary surface exploration, bases, rovers, landers, orbiters, and satellites. Electronics designed for such applications must, therefore, be able to withstand exposure to extreme temperatures and to perform properly for the duration of mission. The Low Temperature Electronics Program at the NASA Glenn Research Center focuses on research and development of electrical devices, circuits, and systems suitable for applications in deep space exploration missions and aerospace environment. Silicon-On-Insulator (SOI) technology has been under active consideration in the electronics industry for many years due to the advantages that it can provide in integrated circuit (IC) chips and computer processors. Faster switching, less power, radiationtolerance, reduced leakage, and high temp-erature capability are some of the benefits that are offered by using SOI-based devices. A few SOI circuits are available commercially. However, there is a noticeable interest in SOI technology for different applications. Very little data, however, exist on the performance of such circuits under cryogenic temperatures. In this work, the performance of SOI integrated circuits, evaluated under low temperature and thermal cycling, are reported. In particular, three examples of SOI circuits that have been tested for operation at low at temperatures are given. These circuits are SOI operational amplifiers, timers and power MOSFET drivers. The investigations were carried out to establish a baseline on the functionality and to determine suitability of these circuits for use in space exploration missions at cryogenic temperatures. The findings are useful to mission planners and circuit designers so that proper selection of electronic parts can be made, and risk assessment can be established for such circuits for use in space missions.

Elbuluk, Malik↗
NASA NTRS2007

SiC Multi-Chip Power Modules as Power-System Building Blocks

The term "SiC MCPMs" (wherein "MCPM" signifies "multi-chip power module") denotes electronic power-supply modules containing multiple silicon carbide power devices and silicon-on-insulator (SOI) control integrated-circuit chips. SiC MCPMs are being developed as building blocks of advanced expandable, reconfigurable, fault-tolerant power-supply systems. Exploiting the ability of SiC semiconductor devices to operate at temperatures, breakdown voltages, and current densities significantly greater than those of conventional Si devices, the designs of SiC MCPMs and of systems comprising multiple SiC MCPMs are expected to afford a greater degree of miniaturization through stacking of modules with reduced requirements for heat sinking. Moreover, the higher-temperature capabilities of SiC MCPMs could enable operation in environments hotter than Si-based power systems can withstand. The stacked SiC MCPMs in a given system can be electrically connected in series, parallel, or a series/parallel combination to increase the overall power-handling capability of the system. In addition to power connections, the modules have communication connections. The SOI controllers in the modules communicate with each other as nodes of a decentralized control network, in which no single controller exerts overall command of the system. Control functions effected via the network include synchronization of switching of power devices and rapid reconfiguration of power connections to enable the power system to continue to supply power to a load in the event of failure of one of the modules. In addition to serving as building blocks of reliable power-supply systems, SiC MCPMs could be augmented with external control circuitry to make them perform additional power-handling functions as needed for specific applications: typical functions could include regulating voltages, storing energy, and driving motors. Because identical SiC MCPM building blocks could be utilized in a variety of ways, the cost and difficulty of designing new, highly reliable power systems would be reduced considerably. Several prototype DC-to-DC power-converter modules containing SiC power-switching devices were designed and built to demonstrate the feasibility of the SiC MCPM concept. In anticipation of a future need for operation at high temperature, the circuitry in the modules includes high-temperature inductors and capacitors. These modules were designed to be stacked to construct a system of four modules electrically connected in series and/or parallel. The packaging of the modules is designed to satisfy requirements for series and parallel interconnection among modules, high power density, high thermal efficiency, small size, and light weight. Each module includes four output power connectors two for serial and two for parallel output power connections among the modules. Each module also includes two signal connectors, electrically isolated from the power connectors, that afford four zones for signal interconnections among the SOI controllers. Finally, each module includes two input power connectors, through which it receives power from an in-line power bus. This design feature is included in anticipation of a custom-designed power bus incorporating sockets compatible with snap-on type connectors to enable rapid replacement of failed modules.

Lostetter, Alexander↗
NASA NTRS2007

Wide-Temperature-Range Integrated Operational Amplifier

A document discusses a silicon-on-insulator (SOI) complementary metal oxide/semiconductor (CMOS) integrated- circuit operational amplifier to be replicated and incorporated into sensor and actuator systems of Mars-explorer robots. This amplifier is designed to function at a supply potential less than or equal to 5.5 V, at any temperature from -180 to +120 C. The design is implemented on a commercial radiation-hard SOI CMOS process rated for a supply potential of less than or equal to 3.6 V and temperatures from -55 to +110 C. The design incorporates several innovations to achieve this, the main ones being the following: NMOS transistor channel lengths below 1 m are generally not used because research showed that this change could reduce the adverse effect of hot carrier injection on the lifetimes of transistors at low temperatures. To enable the amplifier to withstand the 5.5-V supply potential, a circuit topology including cascade devices, clamping devices, and dynamic voltage biasing was adopted so that no individual transistor would be exposed to more than 3.6 V. To minimize undesired variations in performance over the temperature range, the transistors in the amplifier are biased by circuitry that maintains a constant inversion coefficient over the temperature range.

Mojarradi, Mohammad↗
NASA NTRS2007

Design and Fabrication of High-Efficiency CMOS/CCD Imagers

An architecture for back-illuminated complementary metal oxide/semiconductor (CMOS) and charge-coupled-device (CCD) ultraviolet/visible/near infrared- light image sensors, and a method of fabrication to implement the architecture, are undergoing development. The architecture and method are expected to enable realization of the full potential of back-illuminated CMOS/CCD imagers to perform with high efficiency, high sensitivity, excellent angular response, and in-pixel signal processing. The architecture and method are compatible with next-generation CMOS dielectric-forming and metallization techniques, and the process flow of the method is compatible with process flows typical of the manufacture of very-large-scale integrated (VLSI) circuits. The architecture and method overcome all obstacles that have hitherto prevented high-yield, low-cost fabrication of back-illuminated CMOS/CCD imagers by use of standard VLSI fabrication tools and techniques. It is not possible to discuss the obstacles in detail within the space available for this article. Briefly, the obstacles are posed by the problems of generating light-absorbing layers having desired uniform and accurate thicknesses, passivation of surfaces, forming structures for efficient collection of charge carriers, and wafer-scale thinning (in contradistinction to diescale thinning). A basic element of the present architecture and method - the element that, more than any other, makes it possible to overcome the obstacles - is the use of an alternative starting material: Instead of starting with a conventional bulk-CMOS wafer that consists of a p-doped epitaxial silicon layer grown on a heavily-p-doped silicon substrate, one starts with a special silicon-on-insulator (SOI) wafer that consists of a thermal oxide buried between a lightly p- or n-doped, thick silicon layer and a device silicon layer of appropriate thickness and doping. The thick silicon layer is used as a handle: that is, as a mechanical support for the device silicon layer during micro-fabrication.

Pain, Bedabrata↗
NASA NTRS2006

Four-Quadrant Analog Multipliers Using G4-FETs

Theoretical analysis and some experiments have shown that the silicon-on-insulator (SOI) 4-gate transistors known as G4-FETs can be used as building blocks of four-quadrant analog voltage multiplier circuits. Whereas a typical prior analog voltage multiplier contains between six and 10 transistors, it is possible to construct a superior voltage multiplier using only four G4-FETs. A G4-FET is a combination of a junction field-effect transistor (JFET) and a metal oxide/semiconductor field-effect transistor (MOSFET). It can be regarded as a single transistor having four gates, which are parts of a structure that affords high functionality by enabling the utilization of independently biased multiple inputs. The structure of a G4-FET of the type of interest here (see Figure 1) is that of a partially-depleted SOI MOSFET with two independent body contacts, one on each side of the channel. The drain current comprises of majority charge carriers flowing from one body contact to the other that is, what would otherwise be the side body contacts of the SOI MOSFET are used here as the end contacts [the drain (D) and the source (S)] of the G4-FET. What would otherwise be the source and drain of the SOI MOSFET serve, in the G4-FET, as two junction-based extra gates (JG1 and JG2), which are used to squeeze the channel via reverse-biased junctions as in a JFET. The G4-FET also includes a polysilicon top gate (G1), which plays the same role as does the gate in an accumulation-mode MOSFET. The substrate emulates a fourth MOS gate (G2). By making proper choices of G4-FET device parameters in conjunction with bias voltages and currents, one can design a circuit in which two input gate voltages (Vin1,Vin2) control the conduction characteristics of G4-FETs such that the output voltage (Vout) closely approximates a value proportional to the product of the input voltages. Figure 2 depicts two such analog multiplier circuits. In each circuit, there is the following: The input and output voltages are differential, The multiplier core consists of four G4- FETs (M1 through M4) biased by a constant current sink (Ibias), and The G4-FETs in two pairs are loaded by two identical resistors (RL), which convert a differential output current to a differential output voltage. The difference between the two circuits stems from their input and bias configurations. In each case, provided that the input voltages remain within their design ranges as determined by considerations of bias, saturation, and cutoff, then the output voltage is nominally given by Vout = kVin1Vin2, where k is a constant gain factor that depends on the design parameters and is different for the two circuits. In experimental versions of these circuits constructed using discrete G4- FETs and resistors, multiplication of voltages in all four quadrants (that is, in all four combinations of input polarities) was demonstrated, and deviations of the output voltages from linear dependence on the input voltages were found to amount to no more than a few percent. It is anticipated that in fully integrated versions of these circuits, the deviations from linearity will be made considerably smaller through better matching of devices.

Mojarradi, Mohammad↗
NASA NTRS2005

Making Wide-IF SIS Mixers with Suspended Metal-Beam Leads

A process that employs silicon-on-insulator (SOI) substrates and silicon (Si) micromachining has been devised for fabricating wide-intermediate-frequency-band (wide-IF) superconductor/insulator/superconductor (SIS) mixer devices that result in suspended gold beam leads used for radio-frequency grounding. The mixers are formed on 25- m-thick silicon membranes. They are designed to operate in the 200 to 300 GHz frequency band, wherein wide-IF receivers for tropospheric- chemistry and astrophysical investigations are necessary. The fabrication process can be divided into three sections: 1. The front-side process, in which SIS devices with beam leads are formed on a SOI wafer; 2. The backside process, in which the SOI wafer is wax-mounted onto a carrier wafer, then thinned, then partitioned into individual devices; and 3. The release process, in which the individual devices are separated using a lithographic dicing technique. The total thickness of the starting 4-in. (10.16-cm)-diameter SOI wafer includes 25 m for the Si device layer, 0.5 m for the buried oxide (BOX) layer, and 350 m the for Si-handle layer. The front-side process begins with deposition of an etch-stop layer of SiO2 or AlN(x), followed by deposition of a Nb/Al- AlN(x) /Nb trilayer in a load-locked DC magnetron sputtering system. The lithography for four of a total of five layers is performed in a commercial wafer-stepping apparatus. Diagnostic test dies are patterned concurrently at certain locations on the wafer, alongside the mixer devices, using a different mask set. The conventional, self-aligned lift-off process is used to pattern the SIS devices up to the wire level.

Kaul, Anupama↗