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Results for “Silicon-On-Insulator”

Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 19 records
All sourcesNASA NTRSDOE OSTI
NASA NTRS1988

Optical waveguides in oxygen-implanted buried-oxide silicon-on-insulator structures

An analysis is made of the waveguiding properties of the oxygen-implanted, buried-oxide, silicon-on-insulator structures currently being developed for use in microelectronics. It is found that in spite of the fact that the buried-oxide layer is only a few tenths of a micrometer thick, the single-crystal overlayer can support TEo guided-wave propagation, at subbandgap wavelengths, with losses due to substrate radiation leakage at or below the benchmark level of 1 dB/cm.

Kurdi, B. N.↗
NASA NTRS2004

Single-event upset in highly scaled commercial silicon-on-insulator PowerPc microprocessors

Single event upset effects from heavy ions are measured for Motorola and IBM silicon-on-insulator (SOI) microprocessors with different feature sizes, and core voltages. The results are compared with results for similar devices with build substrates. The cross sections of the SOI processors are lower than their bulk counterparts, but the threshold is about the same, even though the charge collections depth is more than an order of magnitude smaller in the SOI devices. The scaling of the cross section with reduction of feature size and core voltage dependence for SOI microprocessors discussed.

single event upset (SEU)↗
NASA NTRS2002

Silicon-on-insulator (SOI) active pixel sensors with the photosite implemented in the substrate

Active pixel sensors for a high quality imager are fabricated using a silicon-on-insulator (SOI) process by integrating the photodetectors on the SOI substrate and forming pixel readout transistors on the SOI thin-film. The technique can include forming silicon islands on a buried insulator layer disposed on a silicon substrate and selectively etching away the buried insulator layer over a region of the substrate to define a photodetector area. Dopants of a first conductivity type are implanted to form a signal node in the photodetector area and to form simultaneously drain/source regions for a first transistor in at least a first one of the silicon islands. Dopants of a second conductivity type are implanted to form drain/source regions for a second transistor in at least a second one of the silicon islands. Isolation rings around the photodetector also can be formed when dopants of the second conductivity type are implanted. Interconnections among the transistors and the photodetector are provided to allow signals sensed by the photodetector to be read out via the transistors formed on the silicon islands.

Pain, Bedabrata↗
NASA NTRS2003

Single-event upset in evolving commercial silicon-on-insulator microprocessor technologies

Single-event upset effects from heavy ions are measured for Motorola and IBM silicon-on-insulator (SOI) microprocessors with different feature sizes and core voltages. Multiple-bit upsets (MBU) in registers and were measured and compared with single-bit upsets. Also, the scaling of the cross section with reduction of feature size for SOI microprocessors was discussed.

Yoder, G. I.↗
DOE OSTI2026

Slow-Light Mid-IR Silicon Photonic Chips for NO 2 and CH 4 Gas Detection

A compact, chip-scale mid-infrared gas sensor is demonstrated, leveraging a two-dimensional photonic crystal waveguide (PCW) fabricated on a silicon-on-insulator (SOI) platform. The PCW comprises a hexagonal lattice with lattice constant a = 860 nm and hole radius r = 0.22a, incorporating a central line defect of reduced-radius holes (r s = 0.7r) to induce slow-light propagation near the photonic band edge with a group index of approximately 73, thereby enhancing light-matter interaction. The sensor operates at fundamental absorption wavelengths of 3.42 μm for nitrogen dioxide (NO 2 ) and 3.40 μm for methane (CH 4 ), utilizing the strongest molecular vibrational transitions for maximum sensitivity. Experimental validation was conducted using dynamically diluted gas mixtures generated by mass flow controllers, with signal acquisition performed by a liquid nitrogen-cooled InSb detector. For NO 2 , the sensor exhibited excellent linear response over 5–25 ppm (part per million) with coefficient of determination R 2 = 0.9934, achieving a detection limit of 210 ppb (part per billion)─representing the first reported silicon photonic-based NO 2 detection. For CH 4 , exposure to 25 ppm resulted in a 6.4% decrease in transmitted intensity, demonstrating multigas sensing capability. The CMOS-compatible fabrication process and compact 3 mm device footprint establish this SOI-PCW platform as a scalable, low-power solution for integrated mid-infrared gas sensing, with significant potential for environmental monitoring and industrial safety applications.

Crystals↗
DOE OSTI2025

Entanglement of a nuclear spin qubit register in silicon photonics

Colour centres provide an optical interface to quantum registers based on electron and nuclear spin qubits in solids. The T centre in silicon is an emerging spin–photon interface that combines telecom O-band optical transitions and an electron spin in a scalable photonics platform. Here, in this study, we integrate T centres into single-mode photonic waveguides in a silicon-on-insulator platform. We demonstrate the initialization, coherent control and state read-out of a three-qubit register based on the electron spin of a T centre coupled to a hydrogen and a silicon nuclear spin. The spin register exhibits spin echo coherence times of 0.41(2) ms for the electron spin, 112(12) ms for the hydrogen nuclear spin and 67(7) ms for the silicon nuclear spin. We use nuclear–nuclear two-qubit gates to generate entanglement between the two nuclear spins with a fidelity of F = 0.77(3) and a coherence time of ${T}_{2}^{* }=2.60(8)$ ms. Our results show that a T centre in silicon photonics can realize a multi-qubit register with an optical interface for quantum communication.

Song, Hanbin [Lawrence Berkeley National Laborator↗
DOE OSTI2025

Substrate effects on phase formation and interfacial stability in superconducting vanadium silicide thin films

Thin films of vanadium silicide (V-silicide) in the A15 cubic phase (V 3 Si) are promising for superconducting quantum devices due to their high transition temperature and potential compatibility with scalable semiconductor fabrication. However, solid-phase synthesis often yields secondary silicide phases that degrade performance. Here, in this study, we investigate the influence of substrate properties using two silicon-on-insulator architectures: one with a polycrystalline HfO 2 buried layer (group A) and the other with amorphous SiO 2 (group B). Both systems exhibit superconductivity consistent with V 3 Si formation, yet structural analysis reveals mixed-phase films in both cases. Crucially, only group A maintains an atomically sharp and chemically stable interface, a prerequisite for phase purity. Prolonged annealing in group A reduces the unwanted V 5 Si 3 phase but also leads to the emergence of Si-rich VSi 2 , likely due to localized substrate degradation. Preliminary atomic-resolution imaging suggests that HfO 2 crystallinity may promote local phase-selective nucleation. These findings highlight the importance of substrate design in promoting phase control and maintaining interfacial integrity in superconducting silicides.

75 CONDENSED MATTER PHYSICS, SUPERCONDUCTIVITY AND↗
DOE OSTI2024

On the Origin of Holes During Polarization Reset in Floating Body Ferroelectric FETs Towards Improving Switching Efficiency

In this article, we performed a comprehensive combined experimental and modeling study on the polarization reset mechanisms of floating body (i.e., channel) ferroelectric FETs, an important class of device with growing interests due to added functionalities and improved reliabilities. Using fully-depleted silicon-on-insulator (FDSOI) FeFET as a classical example, we demonstrate that: 1) without hole generation mechanisms, floating body FeFETs during reset is simply a capacitor divider, with negligible ferroelectric voltage drop for switching; ii) Band-to-band-tunneling (BTBT) around gate-to-S/D overlap even with zero drain bias generates holes to facilitate the reset in FDSOI FeFET, though at a slower speed and hold the reset state; iii) With scaling, S/D inner fringe field can enable fast reset, thus offering a potential efficiency boost approach; iv) a compact FDSOI FeFET model is developed that can capture the BTBT effect and reproduce the observed behaviors; v) the reset mechanism is also validated in a NAND string composed of FDSOI FeFETs, demonstrating its relevant applications. These insights show the strategies in improving reset efficiency, i.e., enhanced BTBT and inner fringe field.

42 ENGINEERING↗
DOE OSTI2024

High Linearity RF Circuits in CMOS Platforms (CRADA Final Report)

The goal of this CRADA was to understand high linearity silicon-on-insulator (SOI) radio frequency switches. The first direction investigated was high linearity RF mixers as these components are composed of a network of switches. During the course of the investigation, it was determined that while the SOI RF switches were effective in the application in mixers and produced state of the art performance, the use of SOI for mixers is not economically feasible because the technology only worked with advanced CMOS nodes <65nm which can have an NRE cost (from lithography masks) in excess of $\$$500,000.

42 ENGINEERING↗
NASA NTRS1991

Advanced silicon on insulator technology

Undoped, thin-layer silicon-on-insulator was fabricated using wafer bonding and selective etching techniques employing a molecular beam epitaxy (MBE) grown Si0.7Ge0.3 layer as an etch stop. Defect free, undoped 200-350 nm silicon layers over silicon dioxide are routinely fabricated using this procedure. A new selective silicon-germanium etch was developed that significantly improves the ease of fabrication of the bond and etch back silicon insulator (BESOI) material.

Godbey, D.↗
NASA NTRS1992

Fully-depleted silicon-on-sapphire and its application to advanced VLSI design

In addition to the widely recognized advantages of full dielectric isolation, e.g., reduced parasitic capacitance, transient radiation hardness, and processing simplicity, fully-depleted silicon-on-sapphire offers reduced floating body effects and improved thermal characteristics when compared to other silicon-on-insulator technologies. The properties of this technology and its potential impact on advanced VLSI circuitry will be discussed.

Offord, Bruce W.↗
NASA NTRS1995

Characterizing SOI Wafers By Use Of AOTF-PHI

Developmental nondestructive method of characterizing layers of silicon-on-insulator (SOI) wafer involves combination of polarimetric hyperspectral imaging by use of acousto-optical tunable filters (AOTF-PHI) and computational resources for extracting pertinent data on SOI wafers from polarimetric hyperspectral images. Offers high spectral resolution and both ease and rapidity of optical-wavelength tuning. Further efforts to implement all of processing of polarimetric spectral image data in special-purpose hardware for sake of procesing speed. Enables characterization of SOI wafers in real time for online monitoring and adjustment of production. Also accelerates application of AOTF-PHI to other applications in which need for high-resolution spectral imaging, both with and without polarimetry.

Cheng, Li-Jen↗
NASA NTRS1995

Single crystal silicon filaments fabricated in SOI: A potential IR source for a microfabricated photometric CO2 sensor

The objective of this project was to design, fabricate, and test single crystal silicon filaments as potential black body IR sources for a spectrophotometric CO2 sensing microsystem. The design and fabrication of the silicon-on-insulator (SOI) filaments are summarized and figures showing the composite layout of the filament die (which contains four filaments of different lengths -- 500 microns, 1 mm, 1.5 mm and 2 mm -- and equal widths of 15 microns) are presented. The composite includes four mask layers: (1) silicon - defines the filament dimensions and contact pads; (2) release pit - defines the oxide removed from under the filament and hence, the length of the released filament; (3) Pyrex pit - defines the pit etched in the Pyrex cap (not used); and (4) metal - defines a metal pattern on the contact pads or used as a contact hole etch. I/V characteristics testing of the fabricated SOI filaments is described along with the nitride-coating procedures carried out to prevent oxidation and resistance instability.

Tu, Juliana↗
NASA NTRS2002

High-Temperature Electronics: A Role for Wide Bandgap Semiconductors?

It is increasingly recognized that semiconductor based electronics that can function at ambient temperatures higher than 150 C without external cooling could greatly benefit a variety of important applications, especially-in the automotive, aerospace, and energy production industries. The fact that wide bandgap semiconductors are capable of electronic functionality at much higher temperatures than silicon has partially fueled their development, particularly in the case of SiC. It appears unlikely that wide bandgap semiconductor devices will find much use in low-power transistor applications until the ambient temperature exceeds approximately 300 C, as commercially available silicon and silicon-on-insulator technologies are already satisfying requirements for digital and analog very large scale integrated circuits in this temperature range. However, practical operation of silicon power devices at ambient temperatures above 200 C appears problematic, as self-heating at higher power levels results in high internal junction temperatures and leakages. Thus, most electronic subsystems that simultaneously require high-temperature and high-power operation will necessarily be realized using wide bandgap devices, once the technology for realizing these devices become sufficiently developed that they become widely available. Technological challenges impeding the realization of beneficial wide bandgap high ambient temperature electronics, including material growth, contacts, and packaging, are briefly discussed.

Neudeck, Philip G.↗
NASA NTRS2003

Power Electronics Being Developed for Deep Space Cryogenic Applications

Electronic circuits and systems designed for deep space missions need to operate reliably and efficiently in harsh environments that include very low temperatures. Spacecraft that operate in such cold environments carry a large number of heaters so that the ambient temperature for the onboard electronics remains near 20 C. Electronics that can operate at cryogenic temperatures will simplify system design and reduce system size and weight by eliminating the heaters and their associated structures. As a result, system development and launch cost will be reduced. At the NASA Glenn Research Center, an ongoing program is focusing on the development of power electronics geared for deep space low-temperature environments. The research and development efforts include electrical components design, circuit design and construction, and system integration and demonstration at cryogenic temperatures. Investigations are being carried out on circuits and systems that are targeted for use in NASA missions where low temperatures will be encountered: devices such as ceramic and tantalum capacitors, metal film resistors, semiconductor switches, magnetics, and integrated circuits including dc/dc converters, operational amplifiers, voltage references, and motor controllers. Test activities cover a wide range of device and circuit performance under simple as well as complex test conditions, such as multistress and thermal cycling. The effect of low-temperature conditions on the switching characteristics of an advanced silicon-on-insulator field effect transistor is shown. For gate voltages (VGS) below 2.6 V, drain currents at -190 C are lower than drain currents at room temperature (20 C).

Patterson, Richard L.↗
NASA NTRS2002

Complemenary body driving - a low voltage analog circuit technique for SOI

This paper describes several analog circuit primitives that utilize the body terminal as a signal port. A cascode current mirror that can operate with an input and output voltage of 200 mV; and a rail-to-rail, constant transconductance gain block capable of 1 V operation are presented. These circuits have been implemented in a standard 0.35~1 partially-depleted Silicon-on-Insulator (PDSOI) CMOS process and should find wide application in next-generation analog circuit designs.

neuro-prosthetic devices cortical signals↗
NASA NTRS1997

Characterization of Semiconductor Materials Using AOTF Instruments

A non-invasive characterization of silicon-on-insulator (SOI) wafers using white light interference measured by an AOTF polarimetric hyperspectral imaging instrument will be presented an an illustration of the technology potential. Experiments provided high resolution thickness maps of both silicon and oxide layers with accuracy and observed optically active imperfections and distributions in the structure.

polarimetric hyperspectral imaging silicon oxide↗