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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 37 records · Page 2
All sourcesNASA NTRSDOE OSTI
DOE OSTI2021

Fixed Bit Rotary Drilling Failure Criteria Effect on Drilling Vibration

Polycrystalline diamond compact (PDC) bit use has been expanded to geothermal drilling applications due to their improved performance in drilling compared to roller cone bits. Multiple vibration models have been developed yet and there are limited use of field data to study the ability of numerical vibration model to predict recorded vibration in the field. The objective of this paper is to evaluate the capabilities of two different rock-bit interaction models with two different ROP formulations for predicting the actual behavior seen in the field. The first model (Model-I) considers the rock-bit interaction, incorporating the effect of subsurface formation characteristics. The second model (Model-II) is a PDC bit model that uses calculated threshold weight-on-cutter (WOCt) to study the interaction of the bit with the rock surface. The models, which couple the drill stem axial and torsional motions, are solved numerically using the fourth-order Runge-Kutta method and compared with recorded downhole drilling data from the Chocolate Mountain Aerial Gunnery Range (CMAGR) geothermal well located in California. An 8–½" PDC bit with 8 blades was modeled and vibration simulation was performed to investigate stick-slip vibrations at 1400 ft. depth. Simulation results using field data indicate that Model-II encounters a low range of stick-slip severity (SSV) as compared to Model-I, which is in the moderate range. Comparison with the field value for SSV shows Model-II is the best representative of the field case for this depth. The sensitivity analysis shows that results are sensitive to model constants making prediction of SSV from models uncertain.

15 GEOTHERMAL ENERGY↗
NASA NTRS1990

32-Bit-Wide Memory Tolerates Failures

Electronic memory system of 32-bit words corrects bit errors caused by some common type of failures - even failure of entire 4-bit-wide random-access-memory (RAM) chip. Detects failure of two such chips, so user warned that ouput of memory may contain errors. Includes eight 4-bit-wide DRAM's configured so each bit of each DRAM assigned to different one of four parallel 8-bit words. Each DRAM contributes only 1 bit to each 8-bit word.

Buskirk, Glenn A.↗
NASA NTRS1992

Least Reliable Bits Coding (LRBC) for high data rate satellite communications

An analysis and discussion of a bandwidth efficient multi-level/multi-stage block coded modulation technique called Least Reliable Bits Coding (LRBC) is presented. LRBC uses simple multi-level component codes that provide increased error protection on increasingly unreliable modulated bits in order to maintain an overall high code rate that increases spectral efficiency. Further, soft-decision multi-stage decoding is used to make decisions on unprotected bits through corrections made on more protected bits. Using analytical expressions and tight performance bounds it is shown that LRBC can achieve increased spectral efficiency and maintain equivalent or better power efficiency compared to that of Binary Phase Shift Keying (BPSK). Bit error rates (BER) vs. channel bit energy with Additive White Gaussian Noise (AWGN) are given for a set of LRB Reed-Solomon (RS) encoded 8PSK modulation formats with an ensemble rate of 8/9. All formats exhibit a spectral efficiency of 2.67 = (log2(8))(8/9) information bps/Hz. Bit by bit coded and uncoded error probabilities with soft-decision information are determined. These are traded with with code rate to determine parameters that achieve good performance. The relative simplicity of Galois field algebra vs. the Viterbi algorithm and the availability of high speed commercial Very Large Scale Integration (VLSI) for block codes indicates that LRBC using block codes is a desirable method for high data rate implementations.

Vanderaar, Mark↗
NASA NTRS1975

Correction of burst errors containing bit slippages for cyclic block codes

A technique is presented for correction of an (n,k) cyclic block code subjected to a noise disturbance consisting of an arbitrary number of both bit deletions and bit inversions contained within a single error burst. Following the procedure described by Meggitt (1961), the correction of a b-bit burst is attempted by first loading the initial error syndrome into an (n-k) order feedback shift register with taps selected for the code's generating polynomial; the register is then successively shifted one bit position in the direction of lower order. The discussion covers burst correction with m-bit deletion, burst/deletion decoder implementation, false correction probability, and bit slippage involving bit insertions. The principal elements of the burst/deletion correction decoder are presented in schematic form.

Green, E. P.↗
NASA NTRS1980

Critique of the Hughes Aircraft shuttle Ku band leading edge bit synchronizer

A bit synchronizer is analyzed via timing diagrams in a noise-free environment. It is believed that this new bit synchronizer will track the rising edge of the data bits with 25% asymmetry and up to a 90 deg phase shift between the received clock and data bit timing. In addition, the data bits will be demodulated correctly. It is not true that phase shifts larger than 90 deg will necessarily be corrected by this bit synchronizer. However, the specifications currently require the loop to operate over only a + or - 75 deg phase shift between the received data stream leading edges and the bit synchronizer leading edges; consequently, there should be no problem.

Holmes, J. K.↗
NASA NTRS1998

Theoretical Accuracy for ESTL Bit Error Rate Tests

"Bit error rate" [BER] for the purposes of this paper is the fraction of binary bits which are inverted by passage through a communication system. BER can be measured for a block of sample bits by comparing a received block with the transmitted block and counting the erroneous bits. Bit Error Rate [BER] tests are the most common type of test used by the ESTL for evaluating system-level performance. The resolution of the test is obvious: the measurement cannot be resolved more finely than 1/N, the number of bits tested. The tolerance is not. This paper examines the measurement accuracy of the bit error rate test. It is intended that this information will be useful in analyzing data taken in the ESTL. This paper is divided into four sections and follows a logically ordered presentation, with results developed before they are evaluated. However, first-time readers will derive the greatest benefit from this paper by skipping the lengthy section devoted to analysis, and treating it as reference material. The analysis performed in this paper is based on a Probability Density Function [PDF] which is developed with greater detail in a past paper, Theoretical Accuracy for ESTL Probability of Acquisition Tests, EV4-98-609.

Lansdowne, Chatwin↗
DOE OSTI2024

Evaluation of Physics-Based Limiter Redesign Drilling and Alternative Bit Design at The Geysers

As part of a U.S. DOE Geothermal Technologies Office funding opportunity, Geysers Power Company, LLC, an indirect subsidiary of Calpine Corporation, partnered with Sandia National Labs, EGI at the University of Utah, and Texas A&M University to demonstrate increased drilling performance at The Geysers Geothermal Field. The performance target in the drilling demonstrations is at least a 25% improvement in rates of penetration with increased time on bottom for each bit. The project will leverage advances in oil and gas drilling technologies including PDC bits, along with the physics-based limiter redesign techniques championed in drilling demonstrations conducted at the Utah FORGE geothermal site. The planned drilling demonstrations are being conducted as part of an existing drilling campaign intended to enhance reservoir utilization. The wells are typically drilled to the top of the reservoir with mud and then air-drilled to total depth (TD) through fractured zones at temperatures ≥ 450°F. A major goal of the project is to assess the effectiveness of implementing mechanical specific energy (MSE) and drilling dysfunction diagnosis and remediation in these challenging environments, as well as alternate bit technologies. The first demonstration well has been completed, with a total of 15 PDC bit runs in the 17.5”, 12.25” and 8.5” sections. Initial analysis shows ROP gains in all three hole sections, especially in the 17.5” and 12.25” sections, compared with conventional roller cone bit runs in the demonstration well and offset wells. However in the 8.5” hole, wear and damage to the PDC bits resulted in relatively short bit runs. Analysis is underway to take advantage of the positive results and remediate the challenges.

15 GEOTHERMAL ENERGY↗
DOE OSTI2022

Experimental Investigation of Drillstring Torsional Vibration Effect on Rate of Penetration with PDC Bits in Hard Rock

Polycrystalline diamond compact (PDC) bits have shown tremendous performance compared to roller cone bits and have gained attraction in deep geothermal drilling applications. While PDC bits can reach a higher rate of penetration compared to other bits, they are more prone to drilling vibrations. The scope of this paper is to quantify the effects of drillstring torsional vibrations on PDC bit performance using a laboratory testing facility. Here, the tests were performed with three drillstring configurations to evaluate the effect of drillstring vibrations. The results showed that rigid testing overestimates the bit rate of penetration by 35% due to torsional vibrations.

15 GEOTHERMAL ENERGY↗
DOE OSTI2020

Laboratory Drilling Test Data of PDC bits with Sierra White Granite Rock

This file contains unprocessed drilling data tests on Sierra White Granite (SWG) using two new PDC bits. The tests were conducted at Sandia National Laboratories (SNL) in the Hard Rock Drilling Facility (HRDF). The collected data includes ROP data at rotational speeds of 80, 120, and 160 RPMs, with incremental weight on bit (WOB) up to 5100 lbs. The diameter of the 4-bladed and 5-bladed PDC bits was 3 3/4" and supplied by National Oilwell Varco (NOV). Five tests modes were conducted for both bits, which are as follow: (1) Rigid configuration, with no vibration compliance (2) Flywheel configuration (3) Torsional compliance configuration (4) Axial Compliance configuration (5) Combined Axial and Torsional compliance configuration Note: the WOB and torque in the drilling data should be calibrated by zeroing the WOB and torque when the drill bit tags the rock sample.

15 GEOTHERMAL ENERGY↗
DOE OSTI2018

Dissimilar Materials Joining of Carbon Fiber Polymer to Dual Phase 980 by Friction Bit Joining, Adhesive Bonding, and Weldbonding

In the present study, joining of a carbon fiber-reinforced polymer and dual phase 980 steel was studied using the friction bit joining, adhesive bonding, and weldbonding processes. The friction bit joining process was optimized for the maximum joint strength by varying the process parameters. Then, the adhesive bonding and weld bonding (friction bit joining plus adhesive bonding) processes were further developed. Lap shear tensile and cross-tension testing were used to assess the joint integrity of each process. Fractured specimens were compared for the individual processes. The microstructures in the joining bit ranged from tempered martensite to fully martensite in the cross-section view of friction bit-joined specimens. Additionally, the thermal decomposition temperature of the as-received carbon fiber composite was studied by thermogravimetric analysis. Fourier-transform infrared–attenuated total reflectance spectroscopy and X-ray diffraction measurements showed minimal variations in the absorption peak and diffraction peak patterns, indicating insignificant thermal degradation of the carbon fiber matrix due to friction bit joining.

36 MATERIALS SCIENCE↗
NASA NTRS1971

The effect of bandlimiting of a PCM/NRZ signal on the bit-error probability.

The explicit expressions for the intersymbol interference as a function of bandwidth-bit duration product and bit positions for PCM/NRZ systems operating in the presence of Gaussian noise and in a bandlimited channel are determined. Two types of linear bit detectors are considered, integrate and dump, and bandlimit and sample. Restriction of bandwidth results in a performance degradation. The degradation of signal-to-noise ratio is presented as a function of bandwidth-bit duration product and bit patterns. The average probability of bit errors is computed for various bandwidths. The calculations of the upper bound and lower bound on the error probability are also presented.

Tu, K.↗
NASA NTRS1974

Shuttle bit rate synchronizer

A shuttle bit rate synchronizer brassboard unit was designed, fabricated, and tested, which meets or exceeds the contractual specifications. The bit rate synchronizer operates at signal-to-noise ratios (in a bit rate bandwidth) down to -5 dB while exhibiting less than 0.6 dB bit error rate degradation. The mean acquisition time was measured to be less than 2 seconds. The synchronizer is designed around a digital data transition tracking loop whose phase and data detectors are integrate-and-dump filters matched to the Manchester encoded bits specified. It meets the reliability (no adjustments or tweaking) and versatility (multiple bit rates) of the shuttle S-band communication system through an implementation which is all digital after the initial stage of analog AGC and A/D conversion.

Huey, D. C.↗
NASA NTRS1993

A fixed/variable bit-rate data compression architecture

A VLSI architecture for an adaptive data compression encoder capable of sustaining fixed or variable bit-rate output has been developed. There are three modes of operation: lossless with variable bit-rate, lossy with fixed bit-rate and lossy with variable bit-rate. For lossless encoding, the implementation is identical to the USES chip designed for Landsat 7. Obtaining a fixed bit-rate is achieved with a lossy DPCM algorithm using adaptive, nonuniform scalar quantization. In lossy mode, variable bit-rate coding uses the lossless sections of the encoder for post-DPCM entropy coding. The encoder shows excellent compression performance in comparison to other current data compression techniques. No external tables or memory are required for operation.

Zweigle, Gregary C.↗
DOE OSTI2019

Bit error protection in cache memories

A computing device having a cache memory (or “cache”) is described, as is a method for operating the cache. The method for operating the cache includes maintaining, in a history record, a representation of a number of bit errors detected in a portion of the cache. When the history record indicates that no bit errors or a single-bit bit error was detected in the portion of the cache memory, the method includes selecting, based on the history record, an error protection to be used for the portion of the cache memory. When the history record indicates that a multi-bit bit error was detected in the portion of the cache memory, the method includes disabling the portion of the cache memory.

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2025

Use of Rig Parameter Data in Bit Constraint Models for Improved Drilling Performance at The Geysers

Surface parameter measurements are routinely used during deep well construction to monitor and guide drilling conditions for improved performance and reduced costs. However, these measurements are of reduced value without a standard to aid in evaluation and decision making. A method is demonstrated whereby drill bit constraint models are used to interpret drilling response parameters. Drill rig parameter data for well GDC-36 at the Geysers Geothermal Field Power were acquired by Geysers Power Company and drilling contractor Kenai Drilling using Pason US DataHub and evaluated. Drilling parameters are evaluated using laboratory-validated rock reduction models for predicting the phenomenological response of drag bits (Detournay and Defourny, 1992) along with other model constraints in computational algorithms. The method is used to evaluate overall bit performance, monitor bit integrity, and detect the presence of drillstring vibrations and other conditions contributing to bit failure; comparisons are made to observations of bit wear and damage. The method will be applied in real-time to improve decision-making on subsequent wells and has applicability to development of advanced analytics on future geothermal wells using real-time electronic drilling recorder (EDR) data for improved performance and reduced drilling costs.

15 GEOTHERMAL ENERGY↗
DOE OSTI2021

Accelerating Binarized Neural Networks via Bit-Tensor-Cores in Turing GPUs

Despite foreseeing tremendous speedups over conventional deep neural networks, the performance advantage of binarized neural networks (BNNs) has merely been showcased on general-purpose processors such as CPUs and GPUs. In fact, due to being unable to leverage bit-level-parallelism with a word-based architecture, GPUs have been criticized for extremely low utilization (1%) when executing BNNs. Consequently, the latest tensorcores in NVIDIA Turing GPUs start to experimentally support bit computation. In this work, we look into this brand new bit computation capability and characterize its unique features. We show that the stride of memory access can significantly affect performance delivery and a data-format co-design is highly desired to support the tensorcores for achieving superior performance than existing software solutions without tensorcores. We realize the tensorcore-accelerated BNN design, particularly the major functions for fully-connect and convolution layers — bit matrix multiplication and bit convolution. Evaluations on two NVIDIA Turing GPUs show that, with ResNet-18, our BTC-BNN design can process ImageNet at a rate of 5.6K images per second, 77% faster than state-of-the-art. Our BNN approach is released on https://github.com/pnnl/TCBNN.

Li, Ang↗
DOE OSTI2019

BSTC: A Novel Binarized-Soft-Tensor-Core Design for Accelerating Bit-Based Approximated Neural Nets

Binarized neural network (or BNN) promises tremendous performance improvement over traditional DNNs through simplified bit-level computation and significantly reduced memory access/storage cost. In addition, it has other advantages of low-cost, low-energy and high-robustness, showing great utilization potential in resources-constrained, volatile and latency-critical applications, which are critical for future HPC execution. However, the promised significant performance gain of BNN inference has never been fully demonstrated on general-purpose processors, particularly on GPUs, due to: (i) the challenge to extract and leverage sufficient fine-grained bit-level-parallelism to saturate GPU cores when batch is small; (ii) the fundamental design conflict between bit-based BNN algorithm and underlying word-based architecture; (iii) architecture \& performance unfriendly BNN network design. To address (i) and (ii), we propose binarized-soft-tensor-core as a software-hardware codesign approach to construct bit-manipulation capability for modern GPUs to effectively harvest the emerging bit-level-parallelism. To tackle (iii), we propose intra- and inter-layer fusion techniques so that the entire BNN inference can be packed into a single GPU kernel, to avoid high-cost frequent launching. Experiments demonstrate that our design can achieve over 1000x speedup for raw inference latency and 10x for inference throughput over the state-of-the-art full-precision simulated BNN inference for AlexNet on ImageNet.

Li, Ang↗
NASA NTRS1977

Theoretical and subjective bit assignments in transform picture

It is shown that all combinations of symmetrical input distributions with difference distortion measures give a bit assignment rule identical to the well-known rule for a Gaussian input distribution with mean-square error. Published work is examined to show that the bit assignment rule is useful for transforms of full pictures, but subjective bit assignments for transform picture coding using small block sizes are significantly different from the theoretical bit assignment rule. An intuitive explanation is based on subjective design experience, and a subjectively obtained bit assignment rule is given.

Jones, H. W., Jr.↗