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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 37 records · Page 2
All sourcesNASA NTRSDOE OSTI
DOE OSTI2022

Dynamic Load Inrush Current Mitigation in Islanded Microgrids Powered by Grid-Forming Inverters

Grid-forming inverters in a microgrid may trip due to high inrush current caused by a switched connection of an inductive load, e.g., a relatively large induction motor. The control scheme presented in this article includes virtual inertia control method superimposed on the cascaded controller. This article studies the impact of cascaded control scheme used for grid-forming inverter to mitigate the inrush current effects and enhance the inverter’s robustness for the safe connection of inductive and dynamic loads. Experimental tests are performed using the virtual inertia method for generating the reference angle for synchronous frame conversion. The experimental performance and sensitivity of the controller to different controller gain settings for a switched connection of an induction motor are discussed. The cascaded operation significantly mitigates the inrush currents while the inverters can perform a normal operation. The performance of the control method is tested in a laboratory-scale hardware setup of a 208V microgrid fed by 5kVA and 10kVA inverters, and the results are presented.

Gursoy, Mehmetcan↗
NASA NTRS1997

Solid-state Image Sensor with Focal-plane Digital Photon-counting Pixel Array

A solid-state focal-plane imaging system comprises an NxN array of high gain. low-noise unit cells. each unit cell being connected to a different one of photovoltaic detector diodes, one for each unit cell, interspersed in the array for ultra low level image detection and a plurality of digital counters coupled to the outputs of the unit cell by a multiplexer(either a separate counter for each unit cell or a row of N of counters time shared with N rows of digital counters). Each unit cell includes two self-biasing cascode amplifiers in cascade for a high charge-to-voltage conversion gain (greater than 1mV/e(-)) and an electronic switch to reset input capacitance to a reference potential in order to be able to discriminate detection of an incident photon by the photoelectron (e(-))generated in the detector diode at the input of the first cascode amplifier in order to count incident photons individually in a digital counter connected to the output of the second cascade amplifier. Reseting the input capacitance and initiating self-biasing of the amplifiers occurs every clock cycle of an integratng period to enable ultralow light level image detection by the may of photovoltaic detector diodes under such ultralow light level conditions that the photon flux will statistically provide only a single photon at a time incident on anyone detector diode during any clock cycle.

Fossum, Eric R.↗
NASA NTRS1996

Switched-Polarization Birefringent Optical Delay Lines

Controllable birefringent optical delay lines proposed for use in photonically controlling phases of signals in radiating elements of phased-array antennas. Features low optical insertion losses and made very compact, enabling high packing densities where multiple delay channels needed. Polarization switched in segments to adjust overall delay. Furthermore, two or more delay lines cascaded increases delay-adjustment range.

Yao, Xiaotian Steve↗
NASA NTRS1972

Design of microstrip components by computer

A number of computer programs are presented for use in the synthesis of microwave components in microstrip geometries. The programs compute the electrical and dimensional parameters required to synthesize couplers, filters, circulators, transformers, power splitters, diode switches, multipliers, diode attenuators and phase shifters. Additional programs are included to analyze and optimize cascaded transmission lines and lumped element networks, to analyze and synthesize Chebyshev and Butterworth filter prototypes, and to compute mixer intermodulation products. The programs are written in FORTRAN and the emphasis of the study is placed on the use of these programs and not on the theoretical aspects of the structures.

Cisco, T. C.↗
NASA NTRS1989

A quasi-passive CMOS pipeline D/A converter

A novel pipeline digital-to-analog converter configuration, based on switched-capacitor techniques, is described. An n-bit D/A conversion can be implemented by cascading n + 1 unit cells. The device count of the circuit increases linearly, not exponentially, with the conversion accuracy. The new configuration can be pipelined. Hence, the conversion rate can be increased without requiring a higher clock rate. An experimental 10-bit DAC prototype has been fabricated using a 3-micron CMOS process. The results show that high-speed, high-accuracy, and low-power operation can be achieved without special process or postprocess trimming.

Wang, Fong-Jim↗
DOE OSTI2021

A Computationally Improved Heuristic Algorithm for Transmission Switching Using Line Flow Thresholds for Load Shed Reduction

We present a computationally improved heuristic algorithm for transmission switching (TS) to recover load shed. Research from the past showed that changing power system topology may control power flows and remove line congestion. Hence, TS may reduce the required load shed. One of the main challenges is to find a potential TS candidate in a suitable time. Here, we propose a novel heuristic method that is capable of finding the potential TS candidate faster than existing algorithms in literature. The proposed method is compatible with both the AC and DC optimal power flows (OPF). Three metrics are used to compare the proposed algorithm with the state-of-the-art from literature to show the speedup and accuracy achieved. The proposed method is implemented on the IEEE 30-bus system, PEGASE 89-bus system, IEEE 118-bus system, and Polish 2383- bus system. The results on the large-scale Polish 2383-bus system shows that the proposed algorithm is scalable to large real-world systems. Parallel computing is implemented to further improve the computational performance of the proposed algorithm.

24 POWER TRANSMISSION AND DISTRIBUTION↗
NASA NTRS2002

Intermittent Flow Regimes in a Transonic Fan Airfoil Cascade

A study was conducted in the NASA Glenn Research Center linear cascade on the intermittent flow on the suction surface of an airfoil section from the tip region of a modern low aspect ratio fan blade. Experimental results revealed that, at a large incidence angle, a range of transonic inlet Mach numbers exist where the leading-edge shock-wave pattern was unstable. Flush mounted high frequency response pressure transducers indicated large local jumps in the pressure in the leading edge area, which generates large intermittent loading on the blade leading edge. These measurements suggest that for an inlet Mach number between 0.9 and 1.0 the flow is bi-stable, randomly switching between subsonic and supersonic flows. Hence, it appears that the change in overall flow conditions in the transonic region is based on the frequency of switching between two stable flow states rather than on the continuous increase of the flow velocity. To date, this flow behavior has only been observed in a linear transonic cascade. Further research is necessary to confirm this phenomenon occurs in actual transonic fans and is not the byproduct of an endwall restricted linear cascade.

Lepicovsky, J.↗
DOE OSTI2020

A Generic Multivector Model Predictive Control With Symmetric Pulse Pattern for Hybrid Multilevel Converters

This article presents a generic multivector model predictive control (MV-MPC) method that has the potential to be applied to all hybrid multilevel converters (HMCs). It first locates the reference voltage vector in the 120° oblique coordinate to select the three adjacent voltage vectors to be applied over one control cycle. Then, the current tracking is guaranteed through duty cycle optimization and dc capacitor voltages are balanced by evaluating possible switching sequences that belong to the voltage vectors with optimal duty cycles. At last, the optimal switching sequence with a symmetric five- or seven-segment pulse pattern is generated using an external modulator. Here, the proposed generic MV-MPC can significantly improve the quality of the output current, while achieving a constant equivalent switching frequency at the same time. Experimental studies on an all silicon carbide HMC prototype, i.e., an active neutral point clamped converter with cascaded H-bridge, are presented to validate the effectiveness of the proposed MV-MPC strategy.

42 ENGINEERING↗
DOE OSTI2026

Ferroelectric Fractals: Switching Mechanism of Wurtzite AlN

The advent of wurtzite ferroelectrics is enabling new ferroelectric devices for computer memory that have the potential to bypass the von Neumann bottleneck due to their robust polarization and silicon compatibility. However, the atomistic switching mechanism of wurtzites is still undetermined due to the limitations of density functional theory simulation size and experimental temporal and spatial resolution. Thus, physics-informed materials engineering to reduce coercive field and breakdown in these devices has been limited. In this work, the atomistic mechanism of domain wall migration and domain growth in aluminum nitride-based wurtzites is uncovered using molecular dynamics and Monte Carlo simulations. We reveal the anomalous switching mechanism of fast 1D single columns of atoms propagating from a slow-moving 2D fractallike domain wall. We find that the critical nucleus is a single aluminum ion that breaks its bond with one nitrogen and bonds to another nitrogen; this creates a cascade that flips atoms directly only in the same column, due to the extreme locality (sharpness) of the domain walls in wurtzites. We further show how the fractallike shape of the domain wall in the 2D plane breaks assumptions in the Kolmogorov, Avrami, and Ishibashi (KAI) model and leads to the anomalously fast switching in wurtzite structured ferroelectrics.

36 MATERIALS SCIENCE↗
DOE OSTI2020

An Improved Transmission Switching Algorithm for Managing Post-(N-1) Contingencies in Electricity Networks

In this presentation, we detail the shortcomings of existing transmission switching (TS) methodologies for preventing post-contingency loss of load in wide area electric power networks. Following that, we present a bi-level algorithm as an improvement to the state of the art. We show proof-of-concept level results that indicate computational viability, fast solutions, and the ability to pick the same best candidate as non computationally viable methods. Further, our method also minimizes load shedding after the contingency, thus enhancing the reliability and security of electricity supply. We also include a futuristic scenario of increased renewables and decreased natural gas sourced generators to show promising results. We grant permission for our presentation to be recorded and uploaded by the conference organizers.

24 POWER TRANSMISSION AND DISTRIBUTION↗
DOE OSTI2020

A Computational Efficient Space-Vector Modulation Scheme for A Hybrid Seven-Level Converter for Medium Voltage Grid-Tied Applications

In this paper, a fast space-vector modulation (SVM) scheme is proposed for a hybrid 7-level (7-L) converter, i.e., cascaded T-type converter and H-bridge converters, for grid-tied applications. Using oblique coordinate reference, the proposed SVM can quickly locate the switching triangle enclosing the reference vector in the 7-L space vector diagram. Then all available switching sequences and vector duty cycles are acquired by straightforward calculation without using any look-up tables, which significantly reduces the computational cost. The floating capacitor voltages are also stabilized by using the proposed SVM. Experimental studies on a scale-down prototype are presented in this work to validate the effectiveness of the proposed scheme.

Diao, Fei↗
DOE OSTI2022

A PWM Strategy for Cascaded H-bridges to Reduce the Loss Caused by Parasitic Capacitances of Medium Voltage Dual Active Bridge Transformers

In this paper, to reduce the power loss caused by the parasitic capacitances of medium voltage medium frequency transformers in a two-stage dc/ac converter, including a dual active bridge (DAB)-based dc/dc stage and a cascaded H-bridge (CHB)-based dc/ac stage, a PWM strategy is proposed for the dc/ac stage. For each H-bridge, by shifting the high switching frequency to one half-bridge and having the other half-bridge switching at the fundamental frequency of the ac voltage, equivalent frequencies of transformer terminal-to-ground voltages are reduced. As a result, the frequencies of charging and discharging current to the parasitic capacitance are reduced, and therefore the loss caused by the parasitic capacitances is reduced. Compared to the conventional phase-shift PWM, the proposed PWM strategy can reduce the parasitic capacitance loss by about 75%. Experimental test results of one phase in the 13.8 kV/ 100 kW converter prototype are provided to validate the approach.

Li, Haiguo↗
DOE OSTI2024

ARC-SAFE: Accelerated Response semiconducting Contactors and Surge Attenuation For DC Electrical systems (Final Scientific/Technical Report)

The landscape of power transmission and distribution is quickly evolving as more power conversion is done through power electronics and transmitted or distributed at medium voltage direct current (MVDC). As power electronics tend to store less energy and be less resilient to faults than conventional power transformers, a reliable and fast protection against faults is critical to protect power electronics (PE) based infrastructure, especially for medium- and high-voltage applications. This motivates the development of PE based protection circuits to replace slower contemporary electromechanical breakers. In this project a novel PE based MVDC circuit breaker is developed; the new design is comprised of 1) a normally-on leg made of commercially-available, cascaded SiC junction field effect transistors (JFETs) with a passive balancing network, and 2) a normally-off leg based on an optically-triggered gallium nitride (GaN) photoconductive semiconductor switch (PCSS). The normally-off leg was designed to be quickly turned on, to divert current to an auxiliary dissipative circuit, as the normally-on leg is turned off. This approach, using solid-state devices, was selected for a high-performance, fast-switching operation for the DC circuit breaker as compared to approaches that use slower mechanical switches. To be practical, the circuit breaker must have low conduction loss (low Ron) in the normally-on leg and fast coordinated triggering of the normally-off leg to avoid damage from inductive flyback, which could be considerable for long lengths of cable.

24 POWER TRANSMISSION AND DISTRIBUTION↗
NASA NTRS1991

Single phase dynamic CMOS PLA using charge sharing technique

A single phase dynamic CMOS NOR-NOR programmable logic array (PLA) using triggered decoders and charge sharing techniques for high speed and low power is presented. By using the triggered decoder technique, the ground switches are eliminated, thereby, making this new design much faster and lower power dissipation than conventional PLA's. By using the charge-sharing technique in a dynamic CMOS NOR structure, a cascading AND gate can be implemented. The proposed PLA's are presented with a delay-time of 15.95 and 18.05 nsec, respectively, which compare with a conventional single phase PLA with 35.5 nsec delay-time. For a typical example of PLA like the Signetics 82S100 with 16 inputs, 48 input minterms (m) and 8 output minterms (n), the 2-SOP PLA using the triggered 2-bit decoder is 2.23 times faster and has 2.1 times less power dissipation than the conventional PLA. These results are simulated using maximum drain current of 600 micro-A, gate length of 2.0 micron, V sub DD of 5 V, the capacitance of an input miniterm of 1600 fF, and the capacitance of an output minterm of 1500 fF.

Dhong, Y. B.↗
DOE OSTI2022

Single DC Source Based Cascaded Multilevel Inverter

The objective of this project is to develop a high-efficiency solid-state transformer that converts a fixed DC voltage to a medium-voltage AC for utility distribution network connections without having the conventional low-frequency bulky transformers and switch gears. The initial target of 99% efficiency was achieved with the use of wide bandgap semiconductor devices using a proposal novel multilevel inverter. The medium-voltage was successfully tested at 7.2/12.47 kV phase/line voltage level for a 100-kW three-phase inverter.

14 SOLAR ENERGY↗
DOE OSTI2024

Multi-resonant switched capacitor power converter architecture

A switched-capacitor (SC) network in an SC converter is controlled to operate at varying resonant modes to achieve high conversion ratio efficiency, at a low circuit component count. These power converters are suited to numerous application areas including improving energy efficiency of data centers. A family of resonant switched capacitor (SC) converters with multiple operating phases are presented “Multi-Resonant SC Converters”. Described in detail are an 8-to-1 Multi-Resonant-Doubler (MRD) converter and a 6-to-1 Cascaded Series-Parallel (CaSP). The topology of these converters make them amenable to combining like units in parallel toward reaching higher power levels.

Ye, Zichao↗
DOE OSTI2024

Comprehensive AI-based System for Control, Sensor Estimation, and Fault Detection of Cascaded Multilevel Inverters

In this paper, an Artificial Intelligence-based (AI) system is proposed for an 11-level cascaded H-bridge multilevel inverter (MLI) with the aims of harmonic suppression and reliability enhancement. The system consists of three seamlessly integrated Neural Networks (NNs). First, a multilayer perceptron is used to generalize the optimal switching angles for selective harmonic elimination under non-equal DC voltages. Next, an autoencoder NN estimates the voltage sensor readings to address potential drifting. Finally, a perceptron NN detects inverter faults based solely on the output voltage of the MLI. Simulation scenarios were evaluated, and the results show that the proposed system provides a comprehensive solution for the robust operation of the MLI. The proposed solution is capable of minimizing the targeted harmonics orders with minimal impact on the fundamental voltage, even when the voltage sensor drifts. Furthermore, the inverter under fault conditions was successfully identified.

Rezende da Costa Reis Kimpara, Renata↗
NASA NTRS1988

Programmable synaptic chip for electronic neural networks

A binary synaptic matrix chip has been developed for electronic neural networks. The matrix chip contains a programmable 32X32 array of 'long channel' NMOSFET binary connection elements implemented in a 3-micron bulk CMOS process. Since the neurons are kept off-chip, the synaptic chip serves as a 'cascadable' building block for a multi-chip synaptic network as large as 512X512 in size. As an alternative to the programmable NMOSFET (long channel) connection elements, tailored thin film resistors are deposited, in series with FET switches, on some CMOS test chips, to obtain the weak synaptic connections. Although deposition and patterning of the resistors require additional processing steps, they promise substantial savings in silicon area. The performance of synaptic chip in a 32-neuron breadboard system in an associative memory test application is discussed.

Moopenn, A.↗