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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 37 records · Page 2
All sourcesNASA NTRSDOE OSTI
NASA NTRS2000

A Parallel Genetic Algorithm for Automated Electronic Circuit Design

We describe a parallel genetic algorithm (GA) that automatically generates circuit designs using evolutionary search. A circuit-construction programming language is introduced and we show how evolution can generate practical analog circuit designs. Our system allows circuit size (number of devices), circuit topology, and device values to be evolved. We present experimental results as applied to analog filter and amplifier design tasks.

Lohn, Jason D.↗
DOE OSTI2021

An Intelligent System for Automatic Selection of DC-DC Converter Topology with Optimal Design

In this paper, we present an intelligent system that has the capabilities of automatically selecting topology classes and optimizing circuit parameters of DC-DC power converters for a given design specification. The system, Machine-Learning-enhanced Automated Circuit Configuration and Evaluation of Power Converters (ML-ACCEPT), uses a hybrid of machine learning technologies, decision tree inference, reinforcement learning and deep neural networks. The system gives high accurate recommendations of design topology classes and computationally efficient results in optimizing power efficiencies in power converter design.

Xue, Lincoln↗
NASA NTRS2000

Automated Design of Quantum Circuits

In order to design a quantum circuit that performs a desired quantum computation, it is necessary to find a decomposition of the unitary matrix that represents that computation in terms of a sequence of quantum gate operations. To date, such designs have either been found by hand or by exhaustive enumeration of all possible circuit topologies. In this paper we propose an automated approach to quantum circuit design using search heuristics based on principles abstracted from evolutionary genetics, i.e. using a genetic programming algorithm adapted specially for this problem. We demonstrate the method on the task of discovering quantum circuit designs for quantum teleportation. We show that to find a given known circuit design (one which was hand-crafted by a human), the method considers roughly an order of magnitude fewer designs than naive enumeration. In addition, the method finds novel circuit designs superior to those previously known.

Williams, Colin P.↗
NASA NTRS2000

Towards Evolving Electronic Circuits for Autonomous Space Applications

The relatively new field of Evolvable Hardware studies how simulated evolution can reconfigure, adapt, and design hardware structures in an automated manner. Space applications, especially those requiring autonomy, are potential beneficiaries of evolvable hardware. For example, robotic drilling from a mobile platform requires high-bandwidth controller circuits that are difficult to design. In this paper, we present automated design techniques based on evolutionary search that could potentially be used in such applications. First, we present a method of automatically generating analog circuit designs using evolutionary search and a circuit construction language. Our system allows circuit size (number of devices), circuit topology, and device values to be evolved. Using a parallel genetic algorithm, we present experimental results for five design tasks. Second, we investigate the use of coevolution in automated circuit design. We examine fitness evaluation by comparing the effectiveness of four fitness schedules. The results indicate that solution quality is highest with static and co-evolving fitness schedules as compared to the other two dynamic schedules. We discuss these results and offer two possible explanations for the observed behavior: retention of useful information, and alignment of problem difficulty with circuit proficiency.

Lohn, Jason D.↗
DOE OSTI2022

A Tri-Port Current-Source Soft-Switching Medium-Voltage String Inverter for Large-Scale Solar-Plus-Storage Farms

This article presents a tri-port current-source soft-switching medium-voltage string inverter (TMVSI) to reduce the Levelized cost of energy (LCOE) of large-scale solar-plus-storage (SPS) farms. Throughout this work, the topology, operating principle, circuit simulation, control, and hardware design of the TMVSI are introduced. In addition, three key challenges compromising the performance of the TMVSI are addressed in this article. First, a new feed-forward compensation for model predictive control of the TMVSI is proposed to compensate for sampling and computational delay and high dc-link ripple with low computational cost and high scalability. Second, the use of laminated permanent magnets is proposed to reduce the losses of the MV medium-frequency transformer (MFT) in the TMVSI while increasing its saturation current. Finally, an improved U-shape winding pattern is proposed to decrease the leakage inductance of the MV MFT and reduce the voltage stress across semiconductor switches without adding cost or complexity. Here, the effectiveness of the TMVSI is validated by experiments at up to 20kW/500V in different test cases with custom-built prototypes. The contributions of this work make the TMVSI a viable solution to SPS farms and unleash its potential for LCOE reduction.

14 SOLAR ENERGY↗
NASA NTRSDate not supplied

Design and Testing of a Hard-Fault Protection Circuit for a 1 kV SiC MOSFET Inverter

Due to increasingly high DC link voltages and further advancements in the current density of silicon carbide (SiC) MOSFETs, it has become evident that conventional IGBT protection methods are not sufficient to prevent exceeding the current rating of these devices during low-inductance fault events. This paper explores the use of an air core Rogowski coil topology to mitigate these hard fault events. The design of this circuit resulted in safe shutdown of a low impedance phase-to-phase fault in under one microsecond, tested up to DC link voltages of 1 kV. This paper details the theory, design, simulation, and successful test results of this method.

hard fault protection↗
DOE OSTI2023

PV Inverter Systems Enabled by Monolithically Integrated SiC based Four Quadrant Power Switch (4-QPS) [BiDFET]

The purpose of this project was to develop a new breed of Power Conversion Systems (PCS) for PV integration that is enabled by the newly developed 4-Quadrant Single Die SiC Power Semiconductor Switches (4-QPS) or also referred to as “Bidirectional FET (BIDFET)”. This work includes semiconductor die development, advanced packaging, converter design, development, and testing of 4-QPS enabled hardware prototypes at 1 kW (for single phase residential application) and 10 kW (for three phase commercial application). The BiDirectional Field-Effect Transistor (BiDFET) can enable circuit topologies requiring four-quadrant switches, that were earlier designed using discrete combinations of MOSFETs, IGBTs, GaN HEMTs, and PiN diodes. The monolithic nature of the BiDFET allows lower device count, smaller switch volume, lower inductance, and simpler packaging, and hence more reliable and commercially viable implementation in power electronics converters. The matrix converter topologies, now feasible using BiDFETs, can eliminate the bulky and unreliable dc link capacitors or inductors required for conventional voltage-source or current-source converters in ac–ac and ac–dc applications. The 1.2 kV BiDFET has the potential to disrupt all the applications utilizing 1.2 kV switches, including electric vehicle (EV) drivetrain, bidirectional EV chargers, industrial motor drives, solid-state transformers, datacenter power supplies, elevator drives, dc microgrids, energy storage grid integration, solid-state breakers, etc.

24 POWER TRANSMISSION AND DISTRIBUTION↗
DOE OSTI2023

Power Conversion Systems Enabled by SiC BiDFET Device

The BiDirectional Field-Effect Transistor (BiDFET) can enable circuit topologies requiring four quadrant switches, that were earlier designed using discrete combinations of MOSFETs, IGBTs, GaN HEMTs and PiN diodes. The monolithic nature of the BiDFET allows lower device count, smaller switch volume, lower inductance, and simpler packaging, and hence more reliable and commercially viable implementation in power electronics converters. Furthermore, the matrix converter topologies, now feasible using BiDFETs, can eliminate the bulky and unreliable dc link capacitors or inductors required for conventional voltage-source or current-source converters in ac-ac and ac dc applications. The 1.2 kV BiDFET has the potential to disrupt all the applications utilizing 1.2 kV switches, including electric vehicle (EV) drivetrain, bidirectional EV chargers, industrial motor drives, solid-state transformers, datacenter power supplies, elevator drives, dc microgrids, energy storage grid integration, solid-state breakers, etc.

42 ENGINEERING↗
NASA NTRS1984

Photovoltaic central-station power conditioner subsystems

The potential of applying new advanced circuit topologies and semiconductors with improved switching characteristics to the design and development of central-station power conditioning subsystems is assessed. State-of-the-art large power conditioners suitable for photovoltaic central-station application are reviewed. Advanced topology power conditioning subsystems, when compared to available production hardware, promise improved performance, significant cost reduction, and lower cost-to-efficiency ratios.

Krauthamer, S.↗
NASA NTRS1978

Modelling, analyses and design of switching converters

A state-space averaging method for modelling switching dc-to-dc converters for both continuous and discontinuous conduction mode is developed. In each case the starting point is the unified state-space representation, and the end result is a complete linear circuit model, for each conduction mode, which correctly represents all essential features, namely, the input, output, and transfer properties (static dc as well as dynamic ac small-signal). While the method is generally applicable to any switching converter, it is extensively illustrated for the three common power stages (buck, boost, and buck-boost). The results for these converters are then easily tabulated owing to the fixed equivalent circuit topology of their canonical circuit model. The insights that emerge from the general state-space modelling approach lead to the design of new converter topologies through the study of generic properties of the cascade connection of basic buck and boost converters.

Cuk, S. M.↗
DOE OSTI2021

A Study of Integrated Signal and Power Transfer for Compact Isolated SiC MOSFET Gate-Drivers

This work discusses a novel set of alternate implementations of isolated gate driver circuits for power electronic transistors. The proposed topologies for the driver have been designed specifically for SiC power MOSFET. Three different solutions are discussed, all of them providing the required gate turn-on and turn-off command signal with galvanic isolation, but also supplying power to the secondary side of the driver by means of magnetic transformers. The resulting solutions, all of them implemented with simple circuitry, enable the integration of the driver into the power cell, allowing for theoretical higher power density values in the final system. The principle of operation of the different solutions is discussed, and then the main relevant implementation details are presented. After that, the operation of the circuits is demonstrated experimentally, by testing a set of prototypes of these drivers. This provides a comprehensive design example that assesses the feasibility of the proposed solutions. Finally, the main results of the performance of the three gate drivers, on an SiC MOSFET-based prototype are presented and compared.

42 ENGINEERING↗
NASA NTRS1975

CMOS array design automation techniques

A low cost, quick turnaround technique for generating custom metal oxide semiconductor arrays using the standard cell approach was developed, implemented, tested and validated. Basic cell design topology and guidelines are defined based on an extensive analysis that includes circuit, layout, process, array topology and required performance considerations particularly high circuit speed.

Ramondetta, P.↗
DOE OSTI2023

Topological Equivalence of VSI and CSI Commutation Cells and Its Application to Switching Resonance Analysis and Damper Design

This paper proposes the concept of the topological equivalence between the commutation cells of a voltage source inverter (VSI) and a current source inverter (CSI) using duality and equivalent circuit transformation techniques. A switching resonance of CSI is analyzed and an effective three-phase RC damper is derived from the dc-link RC damper of VSIs based on the topological equivalence of the VSI and CSI commutation cells. Furthermore, a new three-phase RC damper design framework utilizing the topological equivalence is proposed. Here, experimental results verify that the proposed three-phase RC damper design for CSI significantly reduces the switching resonance and improves the CSI’s output waveform total harmonics distortions (THDs).

42 ENGINEERING↗
NASA NTRS2005

Re-Configurable Electronics Characterization under Extreme Thermal Environment

The need for reconfigurable electronics is driven by requirements to survive longer missions and harsher environments. It is possible to compensate for degradations in Extreme Environments (EE). EE has effect on electronics: circuits are designed to exploit device characteristics and when a certain temperature or radiation range is exceeded the circuit function gradually degrades. It is possible to employ Hardening by reconfiguration (HBR) to mitigate drifts, degradation, or damage on electronic devices in EE by using reconfigurable devices and an adaptive self-reconfiguration of circuit topology. In this manner degraded components can be salvaged, and completely damaged components can be bypassed. The challenge of conventional design is replaced with that of designing a recover process that automatically performs the (re) design in place of the designer. The objective of testing a Digital Signal Processor (DSP) under the extreme temperatures was to determine the lowest temperature at which the DAP can operate. The objective of testing a Xilinx VirtexII Pro FPGA board was to initially find our whether the evaluation board and the FPGA would survive and continue at temperature ranges from -180 C, and 120 C. The Virtex II functioned correctly at the temperatures tested. The next test was done on the GM-C filter building block using the same temperature range as the Virtex II. The current lower and upper limits were shown to be reduced as the temperature gets lower. The device function can be recovered by increasing the Vb from .08V to .85V. The negative and positive saturation voltages increases as the temperature gets higher. The function of the device can be recovered by decreasing the Vb from .8V to around .75V. The next test was performed to test the recovery of the GmC low pass filter through Vb in a filter circuit. The test indicate that bias voltage control adjustment is an efficient mechanism for circuit recovery at extreme temperatures.

reliability↗
NASA NTRS2000

A Parallel Genetic Algorithm for Automated Electronic Circuit Design

Parallelized versions of genetic algorithms (GAs) are popular primarily for three reasons: the GA is an inherently parallel algorithm, typical GA applications are very compute intensive, and powerful computing platforms, especially Beowulf-style computing clusters, are becoming more affordable and easier to implement. In addition, the low communication bandwidth required allows the use of inexpensive networking hardware such as standard office ethernet. In this paper we describe a parallel GA and its use in automated high-level circuit design. Genetic algorithms are a type of trial-and-error search technique that are guided by principles of Darwinian evolution. Just as the genetic material of two living organisms can intermix to produce offspring that are better adapted to their environment, GAs expose genetic material, frequently strings of 1s and Os, to the forces of artificial evolution: selection, mutation, recombination, etc. GAs start with a pool of randomly-generated candidate solutions which are then tested and scored with respect to their utility. Solutions are then bred by probabilistically selecting high quality parents and recombining their genetic representations to produce offspring solutions. Offspring are typically subjected to a small amount of random mutation. After a pool of offspring is produced, this process iterates until a satisfactory solution is found or an iteration limit is reached. Genetic algorithms have been applied to a wide variety of problems in many fields, including chemistry, biology, and many engineering disciplines. There are many styles of parallelism used in implementing parallel GAs. One such method is called the master-slave or processor farm approach. In this technique, slave nodes are used solely to compute fitness evaluations (the most time consuming part). The master processor collects fitness scores from the nodes and performs the genetic operators (selection, reproduction, variation, etc.). Because of dependency issues in the GA, it is possible to have idle processors. However, as long as the load at each processing node is similar, the processors are kept busy nearly all of the time. In applying GAs to circuit design, a suitable genetic representation 'is that of a circuit-construction program. We discuss one such circuit-construction programming language and show how evolution can generate useful analog circuit designs. This language has the desirable property that virtually all sets of combinations of primitives result in valid circuit graphs. Our system allows circuit size (number of devices), circuit topology, and device values to be evolved. Using a parallel genetic algorithm and circuit simulation software, we present experimental results as applied to three analog filter and two amplifier design tasks. For example, a figure shows an 85 dB amplifier design evolved by our system, and another figure shows the performance of that circuit (gain and frequency response). In all tasks, our system is able to generate circuits that achieve the target specifications.

Long, Jason D.↗
DOE OSTI2023

ML-ACCEPT: Machine-Learning-enhanced Automated Circuit Configuration and Evaluation of Power Converters

This project, ML-ACCEPT, took a significant step toward achieving the first objective of the DIFFERENTIATE program: to help engineers to more rapidly and cost-effectively consider a wider range of more novel concepts before selecting an engineering-optimal architecture for high-fidelity detailed design and evaluation. Compared to existing methods, the ML-ACCEPT project investigated innovative technologies to make the design of power converters more cost-effective and time-efficient by i) integrating recent breakthroughs in ML, power electronics, simulation software, and optimization to research, develop, and developed a suite of ML-enhanced hypothesis generation tools for power converter design; and ii) facilitating the integration of the proposed software tools into existing power-converter design work-flows. Some existing tools for power-converter design have a certain level of intelligence to aid the design process, but to our knowledge none of them has ML-enhanced capability of automating the electrical circuit design process by selecting, configuring, and tailoring the individual components that enable available resources (e.g., high-voltage DC power) to be converted to the desired output (e.g., lower-voltage DC power with a desired voltage ripple), subject to application-specific (e.g., plasma generation and automotive applications) thermal and packaging considerations. The state-of-the-art circuit design of power converters is still heavily reliant on human experts to select the optimal topology and search for design parameters with human’s experience and intuitions, which can be very time-consuming, inefficient, and labor intensive. The team is composed of University of Michigan-Dearborn (UM-Dearborn), Lawrence Livermore National Laboratory (LLNL), Oak Ridge National Laboratory (ORNL), Modelon Inc., and lighthouse customers.

42 ENGINEERING↗
NASA NTRSDate not supplied

Hard Fault Protection for a Silicon Carbide-Based Aerospace Motor Drive

Due to increasingly high DC link voltages and further advancements in the current density of silicon carbide (SiC) MOSFETs, it has become evident that conventional IGBT protection methods are not sufficient to protect these devices from overcurrent during low-inductance fault events. The use of an air core Rogowski coil topology was explored to see if it could mitigate these hard fault events. The design of this circuit resulted in safe shutdown of a low impedance phase-tophase fault, tested up to DC link voltages of 1 kV.

High Voltage↗
DOE OSTI2023

Optical N-plasmon: topological hydrodynamic excitations in graphene from repulsive Hall viscosity

Abstract Edge states occurring in Chern and quantum spin-Hall phases are signatures of the topological electronic band structure in two-dimensional (2D) materials. Recently, a new topological electromagnetic phase of graphene characterized by the optical N-invariant was proposed. Optical N-invariant arises from repulsive Hall viscosity in hydrodynamic many-body electron systems, distinct from the Chern and Z 2 invariants. In this paper, we introduce the topologically protected edge excitation—optical N-plasmon of interacting many-body electron systems in the topological optical N-phase. These optical N-plasmons are signatures of the topological plasmonic band structure in 2D materials. We demonstrate that optical N-plasmons exhibit unique dispersion relations, stability against various boundary conditions, and edge profiles when compared with the topologically trivial edge magneto plasmons. Based on the optical N-plasmon, we design an ultra sub-wavelength broadband topological hydrodynamic circulator, which is a chiral quantum radio-frequency circuit component crucial for information routing and interfacing quantum–classical computing systems. Furthermore, we reveal that optical N-plasmons can be effectively tuned by the neighboring dielectric environment without breaking the topological properties. Our work provides a smoking gun signature of topological electromagnetic phases occurring in 2D materials arising from repulsive Hall viscosity.

Physics↗