SEARCH · Search NASA

Results for “digital circuits designs”

Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

SourceResearch connectionFrom yearThrough year

Quote a phrase for an exact phrase match. Source license links do not imply unrestricted reuse.

At least 37 records · Page 2

All sources NASA NTRS DOE OSTI

DOE OSTI2021

Strategies for on-chip digital data compression for X-ray pixel detectors

Here, the continued desire for X-ray pixel detectors with higher frame rates will stress the ability of application-specific integrated circuit (ASIC) designers to provide sufficient off-chip bandwidth to reach continuous frame rates in the 1 MHz regime. To move from the current 10 kHz to the 1 MHz frame rate regime, ASIC designers will continue to pack as many power-hungry high-speed transceivers at the periphery of the ASIC as possible. In this paper, however, we present new strategies to make the most efficient use of the off-chip bandwidth by utilizing data compression schemes for X-ray photon-counting and charge-integrating pixel detectors. In particular, we describe a novel in-pixel compression scheme that converts from analog to digital converter units to encoded photon counts near the photon Poisson noise level and achieves a compression ratio of >1.5x independent of the dataset. In addition, we describe a simple yet efficient zero-suppression compression scheme called "zeromask" (ZM) located at the ASIC's edge before streaming data off the ASIC chip. ZM achieves average compression ratios of >4x, >7x, and >8x for high-energy X-ray diffraction, ptychography, and X-ray photon correlation spectroscopy datasets, respectively. We present the conceptual designs, register-transfer level block diagrams, and the physical ASIC implementation of these compression schemes in 65 nm CMOS. When combined, these two digital compression schemes could increase the effective off-chip bandwidth by a factor of 6-12x.

47 OTHER INSTRUMENTATION↗

DOE OSTI2025

A DATA EFFICIENT SPARSE MODELING FRAMEWORK FOR POWER ESTIMATION IN WATER TREATMENT SENSING OPERATIONS

With increasing freshwater scarcity, advanced process design mechanisms such as Closed-Circuit Reverse Osmosis (CCRO) and Digital/Physical Twin systems are gaining traction in water treatment and reuse operations. While digital and physical twin models enable improved system insight and control, their development is often expensive and computationally intensive, requiring large volumes of synthetic or experimental data to characterize underlying process dynamics. This work introduces a sparse surrogate modeling framework to estimate power consumption from measured flow and pressure variables, along with their nonlinear polynomial and interaction expansions. To ensure model reliability and reduce overfitting, a two-stage pipeline is proposed. First, a dynamic data filtering algorithm is employed to remove uninformative observations and transient operational states. Second, a sparse penalized regression technique is applied to select a minimal set of parsimonious features. The proposed model achieves high sparsity, retaining only 7 out of 34 candidate features (≈79.41% sparsity) while delivering a root mean square error (RMSE) of 0.072 on the test dataset.

Mukherjee, Subrata [ORNL] (ORCID:0000000309930338)↗

DOE OSTI2026

Diagonal state designs with reconfigurable real-time circuits

Unitary designs are widely used in quantum computation, but in many practical settings it suffices to construct a diagonal state design generated with unitary gates diagonal in the computational basis. In this work, we introduce a simple and efficient diagonal state 3-design based on real-time evolutions under 2-local Hamiltonians. Our construction is inspired by the classical Girard-Hutchinson trace estimator in that it involves the stochastic preparation of many random-phase states. Though the exact Girard-Hutchinson states are not tractably implementable on a quantum computer, we can construct states that match the statistical moments of the Girard-Hutchinson states with real-time evolution. Importantly, our random states are all generated using the same Hamiltonians for real-time evolution, with the randomness arising solely from stochastic variations in the durations of the evolutions. In this sense, the circuit is fully reconfigurable and thus suited for near-term realizations on both digital and analog platforms. Moreover, we show how to extend our construction to achieve diagonal state designs of arbitrarily high order.

Shen, Yizhi [LBL, Berkeley] (ORCID:000000024160548↗

DOE OSTI2026

Design of digital acquisition for beam current monitor

As a part of the Proton Improvement Plan – II (PIP-II) at Fermilab, instrumentation systems are being modernized to take advantage of the higher speeds and ease of use offered by standardized embedded systems like MicroTCA. A rear-transition module (RTM) is being designed to interface with said embedded systems. In each of the four identical channels on the RTM, the differential signal from an alternating-current current transformer (ACCT) transimpedance amplifier will again be amplified by a differential operation-amplifier, then filtered by a low-pass topology. The conditioned signal is then digitized at a maximum of 10MS/s by an analog to digital converter (ADC) integrated circuit. After digitization, the ADC passes the data to an off the shelf AdvancedMC (AMC) Xilinx FPGA module using low voltage differential signals. This paper will describe the simulation of analog circuitry for signal conditioning, simulation of digital signal integrity based on physical design as well as verification of design characteristics critical to signal integrity. This work aims to create a methodology that can be applied to future RTMs requiring application of high-speed digital design principles.

White, R.Turner [Fermilab]↗

DOE OSTI2025

Design of Digital Acquisition for Beam Current Monitor

As a part of the Proton Improvement Plan II (PIP-II) at Fermilab, instrumentation systems are being modernized to take advantage of the higher speeds and ease of use offered by standardized embedded systems like MicroTCA. A rear-transition module (RTM) is being designed to interface with said embedded systems. In each of the four identical channels on the RTM, the differential signal from an alternating-current current transformer (ACCT) transimpedance amplifier will again be amplified by a differential operation-amplifier, then filtered by a low-pass topology. The conditioned signal is then digitized at a maximum of 10MS/s by an analog to digital converter (ADC) integrated circuit. After digitization, the ADC passes the data to an off the shelf AdvancedMC (AMC) Xilinx FPGA module using low voltage differential signals. This paper will describe the simulation of analog circuitry for signal conditioning, simulation of digital signal integrity based on physical design as well as verification of design characteristics critical to signal integrity. This work aims to create a methodology that can be applied to future RTMs requiring application of high-speed digital design principles.

White, Turner [Fermilab] (ORCID:0009000348159256)↗

DOE OSTI2024

HunStat – a simple and low-cost potentiostat for analytical and educational purposes

We have developed a truly low-cost (15 USD), simple do-it-yourself (DIY) potentiostat with compact dimensions. The output potential range of this device is between ±1.65 V. The developed instrument takes advantage of a Seeeduino XIAO microcontroller equipped with 10 bit digital-to-analog (D/A) and 12 bit analog-to-digital (A/D) converters and supports various voltammetry techniques, including cyclic voltammetry (CV), differential pulse voltammetry (DPV), and chronoamperometry (CA). Interested users are provided with circuit diagrams, bill of materials, and design files. Additionally, software components are also provided free of charge, including an Arduino sketch and control software. The software enables easy manipulation of electrochemical parameters and visualization of results. The presented design introduces a simple and low-cost DIY potentiostat recommended for both analytical and educational purposes.

47 OTHER INSTRUMENTATION↗

DOE OSTI2024

Synthesis of Correct Digital Controller Models from Specifications by Model Transformation (21-0320)

The design of high consequence controllers (in weapons systems, autonomy, etc.) that do what they are supposed to do is a significant challenge. Testing simply does not come close to meeting the requirements for assurance. Today circuit designers at Sandia (and elsewhere) typically capture the core behavior of their components using state models in tools such as STATEFLOW. They then check that their models meet certain requirements (e.g. “The system bus must not deadlock” or “both traffic lights at an intersection must not be green at the same time”) using tools called model checkers. If the model checker returns “yes” then the property is guaranteed to be satisfied by the model. However, there are several drawbacks to this industry practice: (1) there is a lot of detail to get right, this is particularly challenging when there are multiple components requiring complex coordination (2) any errors returned by the model checker have to be traced back through the design and fixed, necessitating rework, (3) there are severe scalability problems with this approach, particularly when dealing with concurrency. All this places high demands on the designers who now face not only an accelerated schedule but also controllers of increasing complexity. This report describes a new and fundamentally different approach to the construction of safety-critical digital controllers. Instead of directly constructing a complete model and then trying to verify it, the designer can start with an initial abstract (think “sketch”) model plus the requirements, from which a correct concrete model is automatically synthesized. There is no need for post-hoc verification of required functional properties. Having tool to carry this out will significantly impact the nation’s ability to ensure the safety of high-consequence digital systems. The approach has been implemented in a prototype tool, along with a suite of examples, including ones that reflect actual problems faced by designers. Our approach operates on a variant of Statecharts developed at Sandia called Qspecs. Statecharts are a widely used formalism for developing concurrent reactive systems, supporting scalability through allowing state models containing composite states, which are the serial or parallel composition of substates which can themselves contain statecharts. Statecharts enable an incremental style of development, in which states are progressively refined to incorporate greater detail in an incremental model of software development. Our approach formulates a set of constraints from the structure of the models and the requirements and propagates these constraints to a fixpoint. The solution to the constraints is an inductive invariant along with guards on the transitions. We also show how our approach extends to implementation refinement, decomposition, composition, and elaboration. We currently handle safety requirements written in LTL (Linear Temporal Logic)

42 ENGINEERING↗

DOE OSTI2023

3-D Printed Electro-Magnetic Objects for THz Communications

Advanced materials and manufacturing techniques will pave the path towards high quality electro-magnetic circuits that operate up through THz and into optics regime. Digital additive manufacturing (AM) techniques offer game-changing potential for large scale manufacturing of Radio-frequency (RF) circuits and system in custom 2D/3D geometries. The technical collaboration will explore the design flexibility and product customization capabilities of additive manufacturing techniques to process magnetic materials in custom 3D geometries with tailored dielectric properties and frequency response characteristics. Transformation of an RF circuit design idea into a 3D printed system using additive manufacturing techniques will bring together the elements of advanced materials, additive integration, and low-cost manufacturing for future advanced wireless communication systems.

36 MATERIALS SCIENCE↗

DOE OSTI2021

Fast digital lossy compression for X-ray ptychographic data

Increases in X-ray brightness from synchrotron light sources lead to a requirement for higher frame rates from hybrid pixel array detectors (HPADs), while also favoring charge integration over photon counting. However, transfer of the full uncompressed data will begin to constrain detector design, as well as limit the achievable continuous frame rate. Here a data compression scheme that is easy to implement in a HPAD's application-specific integrated circuit (ASIC) is described, and how different degrees of compression affect image quality in ptychography, a commonly employed coherent imaging method, is examined. Using adaptive encoding quantization, it is shown in simulations that one can digitize signals up to 16383 photons per pixel (corresponding to 14 bits of information) using only 8 or 9 bits for data transfer, with negligible effect on the reconstructed image.

73 NUCLEAR PHYSICS AND RADIATION PHYSICS↗

DOE OSTI2025

SpacelyProject/spacely-docs

Quinn, Adam [Fermi National Accelerator Laboratory↗

DOE OSTI2025

An Open-Source Framework for Rapid Validation of Scientific ASICs

Spacely is an open-source framework for the post-silicon validation of analog, digital, and mixed-signal ASICs (Application-Specific Integrated Circuits) which maximizes the reuse of hardware and software, reducing the time taken to achieve meaningful test results. Spacely specifically addresses the needs of small, flexible ASIC design teams commonly found in academia or research institutions which benefit most from sharing the overhead of test stand creation between many unique ASIC designs. Spacely is a set of software, firmware, and design practices. It targets two primary hardware platforms (NI-PXI and Caribou) as well as offering extensible support for bench instruments. Spacely provides a high-level Python interface to all test hardware for accessibility, while also giving more sophisticated teams the opportunity to integrate custom test firmware. The design principles of Spacely are presented in brief. Current documentation is available at https://github.com/SpacelyProject/spacely-docs.

Quinn, Adam [Fermilab]↗

DOE OSTI2024

An Open-Source Framework for Rapid Validation of Scientific ASICs

Spacely is an open-source framework for the post-silicon validation of analog, digital, and mixed-signal ASICs (Application-Specific Integrated Circuits) which maximizes the reuse of hardware and software, reducing the time taken to achieve meaningful test results. Spacely specifically addresses the needs of small, flexible ASIC design teams commonly found in academia or research institutions which benefit most from sharing the overhead of test stand creation between many unique ASIC designs. Spacely is a set of software, firmware, and design practices. It targets two primary hardware platforms (NI-PXI and Caribou) as well as offering extensible support for bench instruments. Spacely provides a high-level Python interface to all test hardware for accessibility, while also giving more sophisticated teams the opportunity to integrate custom test firmware. The design principles of Spacely are presented, along with a demonstrative example of using Spacely to test a pixel detector readout ASIC.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗

DOE OSTI2026

Versatile High-Gain Low-Noise Readout ASIC for Silicon Microstrip Tracking Detectors

This work presents Turpial, a custom-designed low- power front-end readout ASIC for microstrip silicon sensors. Implemented in 130 nm CMOS technology, the chip integrates 64 identical readout channels, each including a configurable charge-sensitive amplifier, a bipolar pulse shaper, a 32-sample 50 Msps analog memory, and a 12-bit RC-hybrid SAR ADC operating at 1 Msps. To satisfy the target power budget of 5 mW per channel, the architecture employs a time-decoupled readout scheme in which fast transient signals are first captured in the analog memory and subsequently digitized at a lower rate. Turpial supports a wide dynamic range from 1 kℎ+ to 1 Mℎ+ while maintaining low noise performance, targeting an equivalent noise charge (ENC) below 200 𝑒−including the sensor, and providing a maximum gain of 1500 mV/fC. A digital block manages slow control, data acquisition, and data serialization through dual CML 300 Mb/s serializers. In addition, an on-chip reference circuit, based on a sub-1 V bandgap reference and an integrated LDO regulator, eliminates the need for external reference circuitry. Experimental results demonstrate that both the individual building blocks and the fully integrated ASIC meet the design specifications.

Hernandez, Hugo [Stanford University] (ORCID:00000↗

DOE OSTI2022

Hardware-Based Randomized Encoding for Sensor Authentication in Power Grid SCADA Systems

Supervisory Control and Data Acquisition (SCADA) systems are utilized extensively in critical power grid infrastructures. Modern SCADA systems have been proven to be susceptible to cyber-security attacks and require improved security primitives in order to prevent unwanted influence from an adversarial party. One section of weakness in the SCADA system is the integrity of field level sensors providing essential data for control decisions at a master station. In this paper we propose a lightweight hardware scheme providing inferred authentication for SCADA sensors by combining an analog to digital converter and a permutation generator as a single integrated circuit. Through this method we encode critical sensor data at the time of sensing, so that unencoded data is never stored in memory, increasing the difficulty of software attacks. We show through experimentation how our design stops both software and hardware false data injection attacks occurring at the field level of SCADA systems.

42 ENGINEERING↗

DOE OSTI2022

A Low-Power 1 Gb/s Line Driver with Configurable Pre-Emphasis for Lossy Transmission Lines

A line driver with configurable pre-emphasis is implemented in a 65 nm CMOS process. The driver utilizes a three-tap feed-forward equalization (FFE) architecture. The relative delays between the taps are selectable in increments of 1/16th of the unit interval (UI) via an 8-stage delay-locked loop (DLL) and digital interpolator. It is also possible to control the output amplitude and source impedance for each tap via a programmable array of eight source-series terminated (SST) drivers. The entire design consumes 9 mW from a 1.2 V supply at 1 Gb/s.

47 OTHER INSTRUMENTATION↗

DOE OSTI2025

Low-Jitter Clock Receivers for Fast Timing Applications

Precision timing is a key requirement for emerging 4D particle tracking, Positron Emission Tomography (PET), beam and fusion plasma diagnostics, and other systems. Time-to-Digital Converters (TDCs) are commonly used to provide digital estimates of the relative timing between events, but the jitter performance of a TDC can be no better than the performance of the circuits that acquire the pulses and deliver them to the TDC. Several clock receiver and distribution circuits were evaluated, and a differential amplifier with resistive loads driving a pseudo-differential clock distribution network, developed using design guidelines for radiation tolerance and cryogenic compatibility, was fabricated as part of three prototypes: an analog front-end testbed chip for high-precision timing pixel readout, a dedicated TDC evaluation chip, and a Low-Gain Avalanche Detector (LGAD) readout circuit. Based on TDC measurements of the prototypes, we infer that the jitter added by the clock receiver and distribution circuits is less than 2.25 ps-rms. This performance meets the requirements of many future precision timing systems. The clock receiver and on-chip pseudo-differential driver were fabricated in commercial 28-nm CMOS technology and occupy 2288 µm 2 .

47 OTHER INSTRUMENTATION↗

DOE OSTI2023

High-fidelity parallel entangling gates on a neutral-atom quantum computer

The ability to perform entangling quantum operations with low error rates in a scalable fashion is a central element of useful quantum information processing. Neutral-atom arrays have recently emerged as a promising quantum computing platform, featuring coherent control over hundreds of qubits and any-to-any gate connectivity in a flexible, dynamically reconfigurable architecture. The main outstanding challenge has been to reduce errors in entangling operations mediated through Rydberg interactions. Here we report the realization of two-qubit entangling gates with 99.5% fidelity on up to 60 atoms in parallel, surpassing the surface-code threshold for error correction. Our method uses fast, single-pulse gates based on optimal control, atomic dark states to reduce scattering and improvements to Rydberg excitation and atom cooling. We benchmark fidelity using several methods based on repeated gate applications, characterize the physical error sources and outline future improvements. Finally, we generalize our method to design entangling gates involving a higher number of qubits, which we demonstrate by realizing low-error three-qubit gates. By enabling high-fidelity operation in a scalable, highly connected system, these advances lay the groundwork for large-scale implementation of quantum algorithms, error-corrected circuits and digital simulations.

97 MATHEMATICS AND COMPUTING↗

DOE OSTI2025

Event-driven readout development: testing of the EDWARD65P1 chip with integrated event generators

Building on a prototype readout integrated circuit for segmented silicon sensors with the EDWARD event-driven readout architecture, the front-end in each pixel was replaced by a hardware generator to verify readout performance, ensuring no data loss, consistent priority handling, and speed verification. Here, this generator produces Poisson-distributed readout requests with individually tunable rates per pixel via a digitally controlled oscillator. The resulting EDWARD65P1 test ASIC is a 32×32 pixel matrix with a 100 μm pitch, equipped with digital event generators simulating radiation hits at user-defined rates. Test results for this new design are presented.

47 OTHER INSTRUMENTATION↗