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At least 37 records · Page 2

AIN-Based Packaging for SiC High-Temperature Electronics

Packaging made primarily of aluminum nitride has been developed to enclose silicon carbide-based integrated circuits (ICs), including circuits containing SiC-based power diodes, that are capable of operation under conditions more severe than can be withstood by silicon-based integrated circuits. A major objective of this development was to enable packaged SiC electronic circuits to operate continuously at temperatures up to 500 C. AlN-packaged SiC electronic circuits have commercial potential for incorporation into high-power electronic equipment and into sensors that must withstand high temperatures and/or high pressures in diverse applications that include exploration in outer space, well logging, and monitoring of nuclear power systems. This packaging embodies concepts drawn from flip-chip packaging of silicon-based integrated circuits. One or more SiC-based circuit chips are mounted on an aluminum nitride package substrate or sandwiched between two such substrates. Intimate electrical connections between metal conductors on the chip(s) and the metal conductors on external circuits are made by direct bonding to interconnections on the package substrate(s) and/or by use of holes through the package substrate(s). This approach eliminates the need for wire bonds, which have been the most vulnerable links in conventional electronic circuitry in hostile environments. Moreover, the elimination of wire bonds makes it possible to pack chips more densely than was previously possible.

Savrun, Ender↗

Low volume packaging for a microinstrumentation system

A folding, multi-platform assembly has been developed for the packaging of a multi-chip microinstrumentation system. The assembly includes three solid platforms connected by flexible micromachined ribbon cables and it can be populated by sensors and electronics from a variety of technologies including surface mount and integrated circuit (IC) processes. The entire structure is fabricated from a four-inch silicon wafer using a simple four mask process and a post-process EDP etch. The micromachined ribbon cables allow the platform assembly to be folded into a three level structure with control electronics on the bottom level, microsensors and interface electronics on the second level, and sensors that need environmental access on the top level. Using the silicon multi-platform assembly, a prototype microinstrumentation system has been developed that includes a microcontroller unit and sensors for measuring temperature, barometric pressure, humidity, altitude, and acceleration as well as a telemetry device for wireless communication. When folded in the three level structure, this microsystem occupies only 5 cc and can be placed in an outer case the size of a wristwatch.

Mason, A.↗

MEMS in Space Systems

Micro-electro-mechanical systems (MEMS) provide an emerging technology that has the potential for revolutionizing the way space systems are designed, assembled, and tested. The high launch costs of current space systems are a major determining factor in the amount of functionality that can be integrated in a typical space system. MEMS devices have the ability to increase the functionality of selected satellite subsystems while simultaneously decreasing spacecraft weight. The Air Force Phillips Laboratory (PL) is supporting the development of a variety of MEMS related technologies as one of several methods to reduce the weight of space systems and increase their performance. MEMS research is a natural extension of PL research objectives in micro-electronics and advanced packaging. Examples of applications that are under research include on-chip micro-coolers, micro-gyroscopes, vibration sensors, and three-dimensional packaging technologies to integrate electronics with MEMS devices. The first on-orbit space flight demonstration of these and other technologies is scheduled for next year.

Lyke, J. C.↗

High-Temperature, Wirebondless, Ultracompact Wide Bandgap Power Semiconductor Modules

Silicon carbide (SiC) and other wide bandgap semiconductors offer great promise of high power rating, high operating temperature, simple thermal management, and ultrahigh power density for both space and commercial power electronic systems. However, this great potential is seriously limited by the lack of reliable high-temperature device packaging technology. This Phase II project developed an ultracompact hybrid power module packaging technology based on the use of double lead frames and direct lead frame-to-chip transient liquid phase (TLP) bonding that allows device operation up to 450 degC. The new power module will have a very small form factor with 3-5X reduction in size and weight from the prior art, and it will be capable of operating from 450 degC to -125 degC. This technology will have a profound impact on power electronics and energy conversion technologies and help to conserve energy and the environment as well as reduce the nation's dependence on fossil fuels.

Elmes, John↗

Qualification and Reliability for MEMS and IC Packages

Advanced IC electronic packages are moving toward miniaturization from two key different approaches, front and back-end processes, each with their own challenges. Successful use of more of the back-end process front-end, e.g. microelectromechanical systems (MEMS) Wafer Level Package (WLP), enable reducing size and cost. Use of direct flip chip die is the most efficient approach if and when the issues of know good die and board/assembly are resolved. Wafer level package solve the issue of known good die by enabling package test, but it has its own limitation, e.g., the I/O limitation, additional cost, and reliability. From the back-end approach, system-in-a-package (SIAP/SIP) development is a response to an increasing demand for package and die integration of different functions into one unit to reduce size and cost and improve functionality. MEMS add another challenging dimension to electronic packaging since they include moving mechanical elements. Conventional qualification and reliability need to be modified and expanded in most cases in order to detect new unknown failures. This paper will review four standards that already released or being developed that specifically address the issues on qualification and reliability of assembled packages. Exposures to thermal cycles, monotonic bend test, mechanical shock and drop are covered in these specifications. Finally, mechanical and thermal cycle qualification data generated for MEMS accelerometer will be presented. The MEMS was an element of an inertial measurement unit (IMU) qualified for NASA Mars Exploration Rovers (MERs), Spirit and Opportunity that successfully is currently roaring the Martian surface

inertial measurement unit↗

Advanced large scale GaAs monolithic IF switch matrix subsystem

Attention is given to a novel chip design and packaging technique to overcome the limitations due to the high signal isolation requirements of advanced communications systems. A hermetically sealed 6 x 6 monolithic GaAs switch matrix subsystem with integral control electronics based on this technique is presented. An 0-dB insertion loss and 60-dB crosspoint isolation over a 3.5-to-6-GHz band were achieved. The internal controller portion of the switching subsystem provides crosspoint control via a standard RS-232 computer interface and can be synchronized with an external systems control computer. The measured performance of this advanced switching subsystem is fully compatible with relatively static 'switchboard' as well as dynamic TDMA modes of operation.

Ch'en, D. R.↗

System Miniaturization Via Heterogeneous Integration of Electronic Devices for Deep Space Missions

The scientific devices designed for each of the Outer Planets Program Focuses will likely be groundbreaking not only with respect to their scientific role but also regarding the electronics required to perform such investigations. In the past, the performance of packaged electronics was limited by the components themselves, with minimal influence of the packaging technology. The rapid development of integrated circuit technology, however, has drastically increased the importance of packaging technology in the ultimate performance of devices. If not carefully considered in the overall design, the packaging may become the limiting factor in the operation of the system. Although industry is responsible for several significant accomplishments in the field of electronics packaging, deep space/outer planet missions must take into account additional requirements such as extremely low temperatures, high radiation levels, hermetic sealing, and severe size and weight limitations. Therefore, the present investigation has been designed to meet the needs of NASA's sensor intensive outer planets program by combining (using flip chip technology) an array of devices (including analog, digital, power volt-age, passives, and MEMS) into a miniaturized heterogeneous system and utilizing optical buses to enable autonomy. Additional information is contained in the original extended abstract.

DelCastillo, L.↗

Electrical and Dielectric Characterizations of HTCC Electronic Packages for High Temperature Harsh Environment Applications

A prototype high temperature co-fired ceramic (HTCC) alumina packaging system composed of a 32-I/Os package and a compatible circuit board was previously developed and demonstrated for long term operation in 500 °C environments. The electrical / dielectric parasitic parameters of that chip level package were characterized and reported. This co-fired packaging system with platinum (Pt) conductor has successfully facilitated tests of silicon carbide (SiC) analog and digital integrated circuits (ICs) developed at NASA GRC at 500°C for up to 10,000 hours in ambient oven environment and 60 earth days in Venus surface environment with simulated temperature, pressure, and chemical constituents. Based on these previous results, this paper introduces new designs of Pt-HTCC packages with 16, 24, and 44 I/Os for packaging a new generation SiC ICs with 8, 24, 56, 62, and 72 I/Os to be tested in high temperature harsh environments. The package with 44 I/Os is specifically designed for the new SiC ICs with 56, 62, and 72-I/Os and electrical connection needs, the power pads of this package are consolidated, and an array of I/O pads distributed on separated vertical levels (inside the package) is used to control the overall package dimensions and mitigate the parasitic effects at high temperatures. This paper will present the detailed design of these chip-level packages and results of electrical and dielectric characterization of these newly fabricated chip-level Pt-HTCC packages.

High temperature↗

Electrical and Dielectric Characterizations of HTCC Electronic Packages for High Temperature Harsh Environment Applications

A prototype high temperature co-fired ceramic (HTCC) alumina packaging system composed of a 32-I/Os package and a compatible circuit board was previously developed and demonstrated for long term operation in 500 °C environments. The electrical / dielectric parasitic parameters of that chip level package were characterized and reported. This co-fired packaging system with platinum (Pt) conductor has successfully facilitated tests of silicon carbide (SiC) analog and digital integrated circuits (ICs) developed at NASA GRC at 500°C for up to 10,000 hours in ambient oven environment and 60 earth days in Venus surface environment with simulated temperature, pressure, and chemical constituents. Based on these previous results, this paper introduces new designs of Pt-HTCC packages with 16, 24, and 44 I/Os for packaging a new generation SiC ICs with 8, 24, 56, 62, and 72 I/Os to be tested in high temperature harsh environments. The package with 44 I/Os is specifically designed for the new SiC ICs with 56, 62, and 72-I/Os and electrical connection needs, the power pads of this package are consolidated, and an array of I/O pads distributed on separated vertical levels (inside the package) is used to control the overall package dimensions and mitigate the parasitic effects at high temperatures. This paper will present the detailed design of these chip-level packages and results of electrical and dielectric characterization of these newly fabricated chip-level Pt-HTCC packages.

High temperature↗

Advanced Interconnect Roadmap for Space Applications

This paper presents the NASA electronic parts and packaging program for space applications. The topics include: 1) Forecasts; 2) Technology Challenges; 3) Research Directions; 4) Research Directions for Chip on Board (COB); 5) Research Directions for HDPs: Multichip Modules (MCMs); 6) Research Directions for Microelectromechanical systems (MEMS); 7) Research Directions for Photonics; and 8) Research Directions for Materials. This paper is presented in viewgraph form.

Galbraith, Lissa↗

A 96% Alumina based Packaging System for 500°C Test of SiC Integrated Circuits

With the development of silicon carbide (SiC) sensors and electronic devices for operation at 500°C, compatible packaging technologies are needed for long term high temperature test and deployment of these sensors and electronic devices. 96% Al2O3ceramic is an excellent electrically insulating material with acceptable dielectric constant and low dielectric loss over wide temperature and frequency ranges. This paper presents a packaging system for low power integrated circuits including a prototype 8-I/O chip-level package and printed circuit board (PCB) based on 96% Al2O3ceramic substrates and Au thick-film metallization for 500°C applications. The details related to designs of packages and PCBs, packaging materials, and specific packaging step recipes including wire -bonding and die-attach, are presented. Some test results of this prototype packaging approach applied to SiC integrated circuits at 500°C are reviewed.

High Temperature, Packaging, Alumina, Thick Film↗

A 96% Alumina based Packaging System for 500°C Test of SiC Integrated Circuits

With the development of silicon carbide (SiC) sensors and electronic devices for operation at 500°C, compatible packaging technologies are needed for long term high temperature test and deployment of these sensors and electronic devices. 96% Al2O3 ceramic is an excellent electrically insulating material with acceptable dielectric constant and low dielectric loss over wide temperature and frequency ranges. This paper presents a packaging system for low power integrated circuits including a prototype 8-I/O chip-level package and printed circuit board (PCB) based on 96% Al2O3 ceramic substrates and Au thick-film metallization for 500°C applications. The details related to designs of packages and PCBs, packaging materials, and specific packaging step recipes including wire - bonding and die-attach, are presented. Some test results of this prototype packaging approach applied to SiC integrated circuits at 500oC are reviewed.

high temperature↗

Packaging Technologies for High Temperature Electronics and Sensors

This paper reviews ceramic substrates and thick-film metallization based packaging technologies in development for 500degC silicon carbide (SiC) electronics and sensors. Prototype high temperature ceramic chip-level packages and printed circuit boards (PCBs) based on ceramic substrates of aluminum oxide (Al2O3) and aluminum nitride (AlN) have been designed and fabricated. These ceramic substrate-based chiplevel packages with gold (Au) thick-film metallization have been electrically characterized at temperatures up to 550degC. A 96% alumina based edge connector for a PCB level subsystem interconnection has also been demonstrated recently. The 96% alumina packaging system composed of chip-level packages and PCBs has been tested with high temperature SiC devices at 500degC for over 10,000 hours. In addition to tests in a laboratory environment, a SiC JFET with a packaging system composed of a 96% alumina chip-level package and an alumina printed circuit board mounted on a data acquisition circuit board was launched as a part of the MISSE-7 suite to the International Space Station via a Shuttle mission. This packaged SiC transistor was successfully tested in orbit for eighteen months. A spark-plug type sensor package designed for high temperature SiC capacitive pressure sensors was developed. This sensor package combines the high temperature interconnection system with a commercial high temperature high pressure stainless steel seal gland (electrical feed-through). Test results of a packaged high temperature capacitive pressure sensor at 500degC are also discussed. In addition to the pressure sensor package, efforts for packaging high temperature SiC diode-based gas chemical sensors are in process.

Electronic packaging↗

Hydrogen Sensors Demonstrated on the Shuttle

Microelectromechanical-systems- (MEMS-) based hydrogen sensor technology developed by the NASA Glenn Research Center at Lewis Field and Case Western Reserve University was demonstrated on shuttle missions STS-95 (Senator Glenn s mission) and STS-96. These smart sensors, commercialized by Makel Engineering Inc., were part of an "Integrated Vehicle Health Monitoring HEDS Technology Demonstration" series conducted at the NASA Kennedy Space Center. The experiments were designed to demonstrate the effect of technological upgrades on shuttle performance. The hydrogen sensors were micro-fabricated for minimal size, weight, and power consumption. A temperature detector and heater were included on the sensor for temperature control. Two palladium chrome (PdCr) hydrogen detection devices were included in each sensor package: a Schottky diode for low concentrations and a resistor for high concentrations. These sensor designs allow operation in inert environments. "Smart" electronics developed by Makel Engineering were integrated with the sensors to control the sensor temperature and process the output of the various sensors. This complete hydrogen detection system (two sensors on a chip with smart electronics) flew on STS-95 (launched October 1998) and STS-96 (launched May 1999). It was installed in the aft compartment of the shuttle and used to monitor the hydrogen concentration in that region. Up to this time, a mass spectrometer had monitored the hydrogen concentration in the aft compartment before launch, and "grab" bottles had been used after launch. The inside of these bottles is at vacuum. During flight, the grab bottles are pyrotechnically opened for a brief period, and the gas in the aft compartment is captured in the bottle. Several of these bottles are opened at different times during takeoff, and their contents are used to determine the time profile of the gases in the aft chamber. However, this information is not available until after the flight. On the launch pad, results from the new sensor technology paralleled the responses of the mass spectrometer with, in some cases, a quicker response time. In flight, data from the new sensors agreed with those derived from analyzing the contents of the grab bottles. Moreover, this microsensor can monitor the aft compartment continuously and, in principle, could monitor the health of the vehicle in real time during flight.

Hunter, Gary W.↗

Aeroflex Technology as Class-Y Demonstrator

Modern space field programmable gate array (FPGA) devices with increased functional density and operational frequency, such as Xilinx Virtex 4 (V4) and S (V5), are packaged in non-hermetic ceramic flip chip forms. These next generation space parts were not qualified to the MIL-PRF-38535 Qualified Manufacturer Listing (QML) class-V when they were released because class-V was only intended for hermetic parts. In order to bring Xilinx V5 type packages into the QML system, it was suggested that class-Y be set up as a new category. From 2010 through 2014, a JEDEC G12 task group developed screening and qualification requirements for Class-Y products. The Document Standardization Division of the Defense Logistics Agency (DLA) has completed an engineering practice study. In parallel with the class-Y efforts, the NASA Electronic Parts and Packaging (NEPP) program has funded JPL to study potential reliability issues of the class-Y products. The major hurdle of this task was the absence of adequate research samples. Figure 1-1 shows schematic diagrams of typical structures of class-Y type products. Typically, class-Y products are either in ceramic flip chip column grid array (CGA) or land grid array (LGA) form. In class-Y packages, underfill and heat spread adhesive materials are directly exposed to the spacecraft environment due to their non-hermeticity. One of the concerns originally raised was that the underfill material could degrade due to the spacecraft environment and negatively impact the reliability of the package. In order to study such issues, it was necessary to use ceramic daisy chain flip chip package samples so that continuity of flip chip solder bumps could be monitored during the reliability tests. However, none of the commercially available class-Y daisy chain parts had electrical connections through flip chip solder bumps; only solder columns were daisy chained, which made it impossible to test continuity of flip chip solder bumps without using extremely costly functional parts. Among space parts manufacturers who were interested in producing class-Y products, Aeroflex Microelectronic Solutions-HiRel had been developing assembly processes using their internal R&D classy type samples. In early 2012, JPL and Aeroflex initiated a collaboration to study reliability of the Aeroflex technology as a class-Y demonstrator.

Suh, Jong-ook↗

Packaging Technology Designed, Fabricated, and Assembled for High-Temperature SiC Microsystems

A series of ceramic substrates and thick-film metalization-based prototype microsystem packages designed for silicon carbide (SiC) high-temperature microsystems have been developed for operation in 500 C harsh environments. These prototype packages were designed, fabricated, and assembled at the NASA Glenn Research Center. Both the electrical interconnection system and the die-attach scheme for this packaging system have been tested extensively at high temperatures. Printed circuit boards used to interconnect these chip-level packages and passive components also are being fabricated and tested. NASA space and aeronautical missions need harsh-environment, especially high-temperature, operable microsystems for probing the inner solar planets and for in situ monitoring and control of next-generation aeronautical engines. Various SiC high-temperature-operable microelectromechanical system (MEMS) sensors, actuators, and electronics have been demonstrated at temperatures as high as 600 C, but most of these devices were demonstrated only in the laboratory environment partially because systematic packaging technology for supporting these devices at temperatures of 500 C and beyond was not available. Thus, the development of a systematic high-temperature packaging technology is essential for both in situ testing and the commercialization of high-temperature SiC MEMS. Researchers at Glenn developed new prototype packages for high-temperature microsystems using ceramic substrates (aluminum nitride and 96- and 90-wt% aluminum oxides) and gold (Au) thick-film metalization. Packaging components, which include a thick-film metalization-based wirebond interconnection system and a low-electrical-resistance SiC die-attachment scheme, have been tested at temperatures up to 500 C. The interconnection system composed of Au thick-film printed wire and 1-mil Au wire bond was tested in 500 C oxidizing air with and without 50-mA direct current for over 5000 hr. The Au thick-film metalization-based wirebond electrical interconnection system was also tested in an extremely dynamic thermal environment to assess thermal reliability. The I-V curve1 of a SiC high-temperature diode was measured in oxidizing air at 500 C for 1000 hr to electrically test the Au thick-film material-based die-attach assembly.

Chen, Liang-Yu↗

Microelectromechanical Systems (MEMS) Broadband Light Source Developed

A miniature, low-power broadband light source has been developed for aerospace applications, including calibrating spectrometers and powering miniature optical sensors. The initial motivation for this research was based on flight tests of a Fabry-Perot fiberoptic temperature sensor system used to detect aircraft engine exhaust gas temperature. Although the feasibility of the sensor system was proven, the commercial light source optically powering the device was identified as a critical component requiring improvement. Problems with the light source included a long stabilization time (approximately 1 hr), a large amount of heat generation, and a large input electrical power (6.5 W). Thus, we developed a new light source to enable the use of broadband optical sensors in aerospace applications. Semiconductor chip-based light sources, such as lasers and light-emitting diodes, have a relatively narrow range of emission wavelengths in comparison to incandescent sources. Incandescent light sources emit broadband radiation from visible to infrared wavelengths; the intensity at each wavelength is determined by the filament temperature and the materials chosen for the filament and the lamp window. However, present commercial incandescent light sources are large in size and inefficient, requiring several watts of electrical power to obtain the desired optical power, and they emit a large percentage of the input power as heat that must be dissipated. The miniature light source, developed jointly by the NASA Glenn Research Center, the Jet Propulsion Laboratory, and the Lighting Innovations Institute, requires one-fifth the electrical input power of some commercial light sources, while providing similar output light power that is easily coupled to an optical fiber. Furthermore, it is small, rugged, and lightweight. Microfabrication technology was used to reduce the size, weight, power consumption, and potential cost-parameters critical to future aerospace applications. This chip-based light source has the potential for monolithic fabrication with on-chip drive electronics. Other uses for these light sources are in systems for vehicle navigation, remote sensing applications such as monitoring bridges for stress, calibration sources for spectrometers, light sources for space sensors, display lighting, addressable arrays, and industrial plant monitoring. Two methods for filament fabrication are being developed: wet-chemical etching and laser ablation. Both yield a 25-mm-thick tungsten spiral filament. The proof-of-concept filament shown was fabricated with the wet etch method. Then it was tested by heating it in a vacuum chamber using about 1.25 W of electrical power; it generated bright, blackbody radiation at approximately 2650 K. The filament was packaged in Glenn's clean-room facilities. This design uses three chips vacuum-sealed with glass tape. The bottom chip consists of a reflective film deposited on silicon, the middle chip contains a tungsten filament bonded to silicon, and the top layer is a transparent window. Lifetime testing on the package will begin shortly. The emitted optical power is expected to be approximately 1.0 W with the spectral peak at 1.1 mm.

Tuma, Margaret L.↗