Search NASA⌕ Search

SEARCH · Search NASA

Results for “integrated gate driver”

Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

Quote a phrase for an exact phrase match. Source license links do not imply unrestricted reuse.

34 records · Page 2
All sourcesNASA NTRSDOE OSTI
DOE OSTI2025

Integration Methods for High-Density Integrated Electric Drives (Final Technical Report)

The project goal was to research, design and fabricate high-power-density, high-performance SiC power electronic modules for motor drive inverters in electric vehicles (EVs) to enable the subsequent motor drive to achieve a power density of 100 kW/l. EVs use electric motors instead of internal combustion engines as the prime mover, and their core components are semiconductor-based power electronic modules. Efficient power electronic modules play a vital role in power conversion systems. The performance of power modules directly affects the energy efficiency and overall performance of electric vehicles. Therefore, it is particularly important to develop power modules with high power density and high electrical performance that will perform reliably under EV environmental conditions. To achieve these goals, advanced electronic packaging technologies are required. This report describes a 5-year effort to integrate key aspects surrounding the basic power devices into the module itself to increase power density. These include sensing and sensing readout circuits, gate driver circuits, and two-sided cooling solutions.

33 ADVANCED PROPULSION SYSTEMS↗
DOE OSTI2021

Highly Integrated Wide Bandgap Power Module for Next Generation Plug-In Vehicles (Final Report)

Wide bandgap devices are key enablers for high power density traction inverters. A highly integrated wide bandgap (WBG) power module enables higher temperature operation, higher inverter efficiency and overall smaller die area with the same power delivery. However, it requires careful design of the power module to take advantage of all the superior material properties that silicon carbide (SiC) provides over conventional silicon (Si) Insulated Gate Bipolar Transistor (IGBT) based design. This project developed an efficient and densely packed SiC power module for an automotive traction inverter application. Extensive study was performed to select the best performing SiC die considering a wide range of temperature variation, suitability to integrate into target packaging, robust body diode performance and overall high electrical efficiency. Multiple design ideas were explored to achieve lower stray inductance for both power loop and signal loop, uniform current distribution, compact form factor, and very high thermal performance. The final power module package includes all six inverter switches in the same module (six-pack) with die sintered at both bottom and top surfaces utilizing high performance substrate to achieve high electrical and thermal performance. Two power module variants were developed using 900 V and 1200 V devices for operating at two different high voltage levels (> 600 V HV battery). Both power modules were comprehensively characterized, and high efficiency operation of the inverter was confirmed through analysis. Finally, a complete functional inverter was built with the 1200V power modules using other essential components (HV capacitors, gate driver board, controller board, current sensor, connectors etc.) and tested using GM’s standard test procedure. There are several challenges associated with adopting WBG devices for high voltage operation. In order to assess and mitigate those challenges, GM and subrecipients of this project have conducted multiple detailed studies. This includes phase current reconstruction using integrated Rogowski coil, device junction temperature estimation using on-state gate resistance, modeling and testing the effect of high voltage and fast switching on motor insulation and bearings, partial discharge inception voltage measurement under different environmental conditions. Findings of all these studies are summarized in this report.

33 ADVANCED PROPULSION SYSTEMS↗
DOE OSTI2024

Nuclear imaging to diagnose and correct target-driver registration at high-repetition-rate for improved reactor efficiency

Inertial Confinement Fusion produces energy from a burning plasma lasting a fraction of a nanosecond. Power plant designs based on Inertial Fusion Energy (IFE) will need to ignite targets 1-10 times a second, fired as projectiles into a chamber and delivering the driver to the target location. Driver asymmetry is known to impact ICF experiments at gain near unity and remains a candidate for primary yield degradation, and therefore fusion power plant energy output, for high-gain target designs. For a Fusion Power Plant (FPP), continuous and real-time monitoring of target performance provides an opportunity to stabilize or correct the target-driver registration. This requires x-ray and neutron imaging with a large field-of-view, sufficiently high resolution, fast analysis and to subtend a minimal solid angle. We introduce design criteria for such an imaging system that uses a coded aperture and time-gated, lens-coupled scintillators as a viable solution and outline the research steps required to field such a system. Integrating the imaging system into an IFE power plant as part of an active feedback loop could increase average power output by reducing the failure rate due to mis-aligned drivers with respect to the target.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗
DOE OSTI2022

High Temperature Optocoupler for 3D High Density Power Modules

The goal of this proposed research is to develop a reliable high-temperature optocouplers, which can operate at 250°C with at least ten-year lifetime, and replace isolation transforms as the galvanic isolation solution for the 3D integration of high density power modules. The electrification of future transportations (i.e., electric vehicles) will continuously drive the demand for high density power modules. Optocouplers (i.e., packaged light emitter and detector) as a promising candidate to replace bulky isolation transformers are highly desirable to facilitate the continuous scale-down of gate driver circuitry that will lead to 3D high density power modules and achieve disruptive performance in terms of thermal management, power density, power efficiency, reliability and operating environments. However, regular semiconductor optoelectronic materials and devices have significant difficulty functioning in the harsh environments designated for high density power module usage (such as operation at high temperatures). Ultimately, it is not the intrinsic properties of power devices that prevent their use at higher temperatures, but rather the low voltage electronics needed to drive them and the packaging that surrounds them. The typical operating temperature for optocouplers is only up to 100°C, due to the limitations of light emitting diode (LED) devices inside and packaging materials. A systematic characterization methodology will be developed to analyze the performance, lifetime and reliability of LED devices and distinguish multiple failure mechanisms at high temperatures. An original methodology of “design for reliability” will be developed to design the optoelectronic devices with high reliability and long lifetime at high temperatures. A new architecture of high temperature high reliable optocouplers will be developed, fabricated and demonstrated with continuous operating at 250°C. The development of efficient, reliable high density 3D power modules is the foundation for energy efficiency and energy reliability. Enabled with advanced 3D integration and packaging technologies, high density power module solutions can achieve much more superior performance over the conventional discrete solutions in terms of efficiency, thermal management and power density. The proposed concept of high temperature optocouplers as the galvanic isolation solution for high density power modules will bring together interdisciplinary research involving the wide bandgap materials, optoelectronics, high reliable device design, electronics packaging and power modules. A streamline of skilled personnel would be trained including graduate and undergraduate students, local engineers and scientists which are in great demand to both academia and optoelectronics industry. The proposed research topics, such as, solid state lighting and high temperature device reliability, are currently of major interest at the Department of Energy, in particular, Sandia National Laboratories. This project can enhance collaborations between the University of Arkansas (UA) and Sandia National Laboratories. The findings of the proposed research are expected to be integrated into high density 3-D power modules at the Engineering Research Center for Power Optimization for Electro-Thermal Systems (POETS).

42 ENGINEERING↗
DOE OSTI2024

Tunnel junction-enabled monolithically integrated GaN micro-light emitting transistor

GaN/InGaN microLEDs are a very promising technology for next-generation displays. Switching control transistors and their integration are key components in achieving high-performance, efficient displays. Monolithic integration of microLEDs with GaN switching devices provides an opportunity to control microLED output power with capacitive (voltage)-controlled rather than current-controlled schemes. This approach can greatly reduce system complexity for the driver circuit arrays while maintaining device opto-electronic performance. In this work, we demonstrate a 3-terminal GaN micro-light emitting transistor that combines a GaN/InGaN blue tunneling-based microLED with a GaN n-channel FET. Further, the integrated device exhibits excellent gate control, drain current control, and optical emission control. This work provides a promising pathway for future monolithic integration of GaN FETs with microLED to enable fast switching, high-efficiency microLED display and communication systems.

42 ENGINEERING↗
DOE OSTI2024

Investigating resource-efficient neutron/gamma classification ML models targeting eFPGAs

There has been considerable interest and resulting progress in implementing machine learning (ML) models in hardware over the last several years from the particle and nuclear physics communities. A big driver has been the release of the Python package, hls4ml, which has enabled porting models specified and trained using Python ML libraries to register transfer level (RTL) code. So far, the primary end targets have been commercial field-programmable gate arrays (FPGAs) or synthesized custom blocks on application specific integrated circuits (ASICs). However, recent developments in open-source embedded FPGA (eFPGA) frameworks now provide an alternate, more flexible pathway for implementing ML models in hardware. These customized eFPGA fabrics can be integrated as part of an overall chip design. In general, the decision between a fully custom, eFPGA, or commercial FPGA ML implementation will depend on the details of the end-use application. In this work, we explored the parameter space for eFPGA implementations of fully-connected neural network (fcNN) and boosted decision tree (BDT) models using the task of neutron/gamma classification with a specific focus on resource efficiency. We used data collected using an AmBe sealed source incident on Stilbene, which was optically coupled to an OnSemi J-series silicon photomultiplier (SiPM) to generate training and test data for this study. We investigated relevant input features and the effects of bit-resolution and sampling rate as well as trade-offs in hyperparameters for both ML architectures while tracking total resource usage. The performance metric used to track model performance was the calculated neutron efficiency at a gamma leakage of 10 -3 . The results of the study will be used to aid the specification of an eFPGA fabric, which will be integrated as part of a test chip.

47 OTHER INSTRUMENTATION↗
DOE OSTI2026

Bistable Optical Semiconductor Switching Based on C-Doped GaN

Highly resistive gallium nitride (GaN) is an essential material for power optoelectronic applications. While carbon doping is widely used to achieve semi-insulating properties in GaN, the persistent photoconductivity (PPC) arising from deep-level defect traps remains a major obstacle for high-speed power switching. This study demonstrates a novel approach: leveraging the ultrahigh photoresponsivity of GaN:C (up to 2.1 A ⋅ cm/W ⋅ kV, surpassing alternatives such as GaN:Fe) and employing defect-selective optical control to effectively quench the PPC. By synchronizing a short infrared (1064 nm) quenching pulse with UV (385 nm) excitation in an epitaxially grown GaN:C layer on a heavily doped n-type GaN substrate, we achieve a dramatic reduction in photocurrent fall time by approximately 293× (from 470 to 1.6 μ s), increasing modulation bandwidth from 745 Hz to nearly 218 kHz. Here, this advancement not only establishes a new pathway for controlling PPC in GaN:C but also enables the practical integration of GaN:C in fast power switching devices. Enhanced modulation bandwidth, along with GaN:C excellent photoresponsivity, makes it a promising candidate for optically controlled high-voltage, high-power electronic systems, such as photoconductive semiconductor switches (PCSSs) used in pulsed-power drivers, high-power microwave (HPM) sources, and high-voltage gate drivers for wide bandgap (WBG) power electronics.

Carbon-dopped Gallium nitride (GaN:C)↗
NASA NTRS1999

Design of the Wind Tunnel Model Communication Controller Board

The NASA Langley Research Center's Wind Tunnel Reinvestment project plans to shrink the existing data acquisition electronics to fit inside a wind tunnel model. Space limitations within a model necessitate a distributed system of Application Specific Integrated Circuits (ASICs) rather than a centralized system based on PC boards. This thesis will focus on the design of the prototype of the communication Controller board. A portion of the communication Controller board is to be used as the basis of an ASIC design. The communication Controller board will communicate between the internal model modules and the external data acquisition computer. This board is based around an Field Programmable Gate Array (FPGA), to allow for reconfigurability. In addition to the FPGA, this board contains buffer Random Access Memory (RAM), configuration memory (EEPROM), drivers for the communications ports, and passive components.

Wilson, William C.↗
NASA NTRS1975

The 1.06 micrometer wideband laser modulator: Fabrication and life testing

The design, fabrication, testing and delivery of an optical modulator which will operate with a mode-locked Nd:YAG laser at 1.06 micrometers were performed. The system transfers data at a nominal rate of 400 Mbps. This wideband laser modulator can transmit either Pulse Gated Binary Modulation (PGBM) or Pulse Polarization Binary Modulation (PPBM) formats. The laser beam enters the modulator and passes through both crystals; approximately 1% of the transmitted beam is split from the main beam and analyzed for the AEC signal; the remaining part of the beam exits the modulator. The delivered modulator when initially aligned and integrated with laser and electronics performed very well. The optical transmission was 69.5%. The static extinction ratio was 69:1. A 1000 hour life test was conducted with the delivered modulator. A 63 bit pseudorandom code signal was used as a driver input. At the conclusion of the life test the modulator optical transmission was 71.5% and the static extinction ratio 65:1.

Teague, J. R.↗
NASA NTRS2004

A Re-programmable Platform for Dynamic Burn-in Test of Xilinx Virtexll 3000 FPGA for Military and Aerospace Applications

Field Programmable Gate Arrays (FPGA) have played increasingly important roles in military and aerospace applications. Xilinx SRAM-based FPGAs have been extensively used in commercial applications. They have been used less frequently in space flight applications due to their susceptibility to single-event upsets. Reliability of these devices in space applications is a concern that has not been addressed. The objective of this project is to design a fully programmable hardware/software platform that allows (but is not limited to) comprehensive static/dynamic burn-in test of Virtex-II 3000 FPGAs, at speed test and SEU test. Conventional methods test very few discrete AC parameters (primarily switching) of a given integrated circuit. This approach will test any possible configuration of the FPGA and any associated performance parameters. It allows complete or partial re-programming of the FPGA and verification of the program by using read back followed by dynamic test. Designers have full control over which functional elements of the FPGA to stress. They can completely simulate all possible types of configurations/functions. Another benefit of this platform is that it allows collecting information on elevation of the junction temperature as a function of gate utilization, operating frequency and functionality. A software tool has been implemented to demonstrate the various features of the system. The software consists of three major parts: the parallel interface driver, main system procedure and a graphical user interface (GUI).

Field Programmable Gate Arrays (FPGA)↗
DOE OSTI2020

A 150-kW 99% Efficient All-Silicon-Carbide Triple-Active-Bridge Converter for Solar-Plus-Storage Systems

Solar-plus-storage systems could effectively mitigate the uncertainties of the photovoltaic (PV) generation and improve system reliability by adding an integrated battery energy storage system. As a three-port bidirectional isolated dc–dc converter with soft-switching capability, the triple-active-bridge (TAB) converter inherently matches the requirements of the solar-plus-storage system. However, challenges still remain in the TAB converter design to further improve system efficiency. In this article, the detailed design, implementation, and demonstration for a silicon carbide (SiC) 150-kW TAB converter are presented. Starting from a brief review of the TAB converter, the modulation scheme, power characteristics, and soft-switching region are analyzed. Then, the detailed design of the H-bridge converter building block is given. Here, to improve the system efficiency, a comprehensive characterization of the SiC gate driver with various external gate resistances is performed to address tradeoffs between switching loss and voltage overshoot during transients, as well as the thermal performance of the H-bridge building block. In addition, the design and characterization of the 20-kHz three-port transformer are also given. Comprehensive experimental studies are conducted on a full-power prototype to verify the proposed design. With a measured 99.1% peak efficiency, the proposed TAB converter can fulfill the requirements for solar-plus-storage applications.

14 SOLAR ENERGY↗
DOE OSTI2024

SMART SiC Power ICs: Scalable, Manufacturable, and Robust Technology for SiC Power Integrated Circuits (Final Technical Report)

This collaborative project was initiated with the goal of developing Scalable, Manufacturable, and Robust Technology for SiC Power Integrated Circuits (SMART SiC Power ICs). In pursuit of this objective, innovative designs and fabrication processes were implemented, enabling the development of large-scale (>1 cm²) SiC Complementary Metal-Oxide-Semiconductor (CMOS) integrated circuits and high-voltage (400–600 V) lateral power MOSFETs (HV-LDMOS) on 150 mm 4H-SiC substrates. The resulting SMART SiC Power ICs are tailored to support a wide range of applications requiring diverse voltage and power levels, including automotive systems, industrial equipment, electronic data processing, energy harvesting, and power conditioning. To achieve the proposed ‘SMART’ technology for SiC ICs, the team focused on 1) the Development of highly scalable CMOS (with high channel mobilities for n-type and p-type MOSFETs), LDMOS (~600V, 10A rated), and IC technologies, 2) Establishment of a manufacturable process baseline in a production-grade-, 150mm, SiC fabrication facility, and 3) Demonstration of SMART SiC ICs. The project initially comprised of fabricating 5 lots. In lot 1 monolithic integration using a single process was achieved. Here, we were able to successfully accomplish Integrated HV NMOSFET with LV CMOS on N-epi/N+ Substrate. The HV NMOS demonstrated a Breakdown Voltage (BV) more than 600V. Circuit demonstration of CMOS was also another achievement from this lot. In lot 2, priority was in place for isolation and integration. Here we addressed the isolation concerns and integrated the HV NMOS and LV CMOS using the N-epi/P-epi/N+ substrate. Similar to the lot 1, we were able to achieve a BV of 600 V for HV NMOS. Optimized gate oxide process with high channel mobilities, better gate oxide reliability, development of SPICE models, successful ohmic process development, novel wafer area saving design layouts, P+ isolation schemes with channeling implantations and high temperature operational circuits demonstrations are some of the key highlights from lot 1 and lot2. In lot 3, discrete device performances of HV NMOS with a BV ~700V and reliable LV CMOS performances were achieved. Also, novel architectural solutions were successfully implemented to suppress the electric field crowding at the gate oxide for reliable operations. In lot 4, half bridge power driver ICs with a conversion efficiency of (target 90% to 95%) in the 1-5MHz switching frequency range for output power between 25 W to 3 kW have been included in. However, due to the unfortunate events of sudden foundry shutdown (SiCamore Semi) the processing of lot 4 wafers came to a complete stop (January 2024). Arrangements have recently been made to shift the fabrication to another foundry, General Electric Aerospace. The fabrication process now on course (as of December 2024). Characterizations are delayed due to this unfortunate circumstance. The proposed trench architectural-based devices and ICs (lot 5) underwent modifications from the original project proposal. This change was necessitated by limitations in the availability of trench-based processes at commercial production-grade fabrication facilities in the US. Apart from above achievements, a Process Development Kit (PDK) was successfully developed for planar type SiC CMOS/LDMOS.

42 ENGINEERING↗
NASA NTRS2015

Relativistic Electron Response to the Combined Magnetospheric Impact of a Coronal Mass Ejection Overlapping with a High-Speed Stream: Van Allen Probes Observations

During early November 2013, the magnetosphere experienced concurrent driving by a coronal mass ejection (CME) during an ongoing high-speed stream (HSS) event. The relativistic electron response to these two kinds of drivers, i.e., HSS and CME, is typically different, with the former often leading to a slower buildup of electrons at larger radial distances, while the latter energizing electrons rapidly with flux enhancements occurring closer to the Earth. We present a detailed analysis of the relativistic electron response including radial profiles of phase space density as observed by both Magnetic Electron and Ion Sensor (MagEIS) and Relativistic Electron Proton Telescope instruments on the Van Allen Probes mission. Data from the MagEIS instrument establish the behavior of lower energy (<1 MeV) electrons which span both intermediary and seed populations during electron energization. Measurements characterizing the plasma waves and magnetospheric electric and magnetic fields during this period are obtained by the Electric and Magnetic Field Instrument Suite and Integrated Science instrument on board Van Allen Probes, Search Coil Magnetometer and Flux Gate Magnetometer instruments on board Time History of Events and Macroscale Interactions during Substorms, and the low-altitude Polar-orbiting Operational Environmental Satellites. These observations suggest that during this time period, both radial transport and local in situ processes are involved in the energization of electrons. The energization attributable to radial diffusion is most clearly evident for the lower energy (<1 MeV) electrons, while the effects of in situ energization by interaction of chorus waves are prominent in the higher-energy electrons.

Magnetosphere↗
NASA NTRS2011

Operation of a New Half-Bridge Gate Driver for Enhancement - Mode GaN FETs, Type LM5113, Over a Wide Temperature Range

A new commercial-off-the-shelf (COTS) gate driver designed to drive both the high-side and the low-side enhancement-mode GaN FETs, National Semiconductor's type LM5113, was evaluated for operation at temperatures beyond its recommended specified limits of -40 C to +125 C. The effects of limited thermal cycling under the extended test temperature, which ranged from -194 C to +150 C, on the operation of this chip as well as restart capability at the extreme cryogenic and hot temperatures were also investigated. The driver circuit was able to maintain good operation throughout the entire test regime between -194 C and +150 C without undergoing any major changes in its outputs signals and characteristics. The limited thermal cycling performed on the device also had no effect on its performance, and the driver chip was able to successfully restart at each of the extreme temperatures of -194 C and +150 C. The plastic packaging of this device was also not affected by either the short extreme temperature exposure or the limited thermal cycling. These preliminary results indicate that this new commercial-off-the-shelf (COTS) halfbridge eGaN FET driver integrated circuit has the potential for use in space exploration missions under extreme temperature environments. Further testing is planned under long-term cycling to assess the reliability of these parts and to determine their suitability for extended use in the harsh environments of space.

Patterson, Richard↗
DOE OSTI2024

Advanced Power Electronics and Electric Machines

The advanced power electronics and electric machines (APEEM) research group at the National Renewable Energy Laboratory (NREL) has developed world-class experimental and modeling capabilities for designing and evaluating efficient and reliable power electronics and electric machines thermal management systems. They also design, fabricate and characterize advanced power electronics packaging, and are developing state-of-health monitoring techniques. These researchers deliver safe, reliable, high performing, power-dense components that allow seamless integration between renewable energy sources, electric transportation, and the grid, helping to make widespread electric vehicle (EV) adoption and greenhouse gas emissions reduction more feasible. This document outlines the group's major capabilities in the areas of power electronics; module development and characterization; thermal modeling and management; thermomechanical reliability analysis of devices, modules, inverters/converters, and electric machines; physics-of-failure-based reliability analysis; and microelectronics. It also overviews the group's state-of-the-art equipment for fluid-based thermal management; thermal measurement & characterization; thermomechanical reliability analysis; micro- and power electronics measurement & characterization; and prototype fabrication, as well as the group's world-class modeling and simulation capabilities.

advanced gate drivers↗
NASA NTRS2011

Digital Interface Board to Control Phase and Amplitude of Four Channels

An increasing number of parts are designed with digital control interfaces, including phase shifters and variable attenuators. When designing an antenna array in which each antenna has independent amplitude and phase control, the number of digital control lines that must be set simultaneously can grow very large. Use of a parallel interface would require separate line drivers, more parts, and thus additional failure points. A convenient form of control where single-phase shifters or attenuators could be set or the whole set could be programmed with an update rate of 100 Hz is needed to solve this problem. A digital interface board with a field-programmable gate array (FPGA) can simultaneously control an essentially arbitrary number of digital control lines with a serial command interface requiring only three wires. A small set of short, high-level commands provides a simple programming interface for an external controller. Parity bits are used to validate the control commands. Output timing is controlled within the FPGA to allow for rapid update rates of the phase shifters and attenuators. This technology has been used to set and monitor eight 5-bit control signals via a serial UART (universal asynchronous receiver/transmitter) interface. The digital interface board controls the phase and amplitude of the signals for each element in the array. A host computer running Agilent VEE sends commands via serial UART connection to a Xilinx VirtexII FPGA. The commands are decoded, and either outputs are set or telemetry data is sent back to the host computer describing the status and the current phase and amplitude settings. This technology is an integral part of a closed-loop system in which the angle of arrival of an X-band uplink signal is detected and the appropriate phase shifts are applied to the Ka-band downlink signal to electronically steer the array back in the direction of the uplink signal. It will also be used in the non-beam-steering case to compensate for phase shift variations through power amplifiers. The digital interface board can be used to set four 5-bit phase shifters and four 5-bit attenuators and monitor their current settings. Additionally, it is useful outside of the closed-loop system for beamsteering alone. When the VEE program is started, it prompts the user to initialize variables (to zero) or skip initialization. After that, the program enters into a continuous loop waiting for the telemetry period to elapse or a button to be pushed. A telemetry request is sent when the telemetry period is elapsed (every five seconds). Pushing one of the set or reset buttons will send the appropriate command. When a command is sent, the interface status is returned, and the user will be notified by a pop-up window if any error has occurred. The program runs until the End Program button is depressed.

Smith, Amy E.↗