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Proton testing of linear circuits has identified devices where significantly more damage occurs at equivalent total dose levels with protons than tests with gamma rays.
Commercially available integrated circuit that is marketed as a digital computer input gate circuit was converted to a linear amplifier in a microphone circuit that has high input impedance, low output impedance, low cost, and is small enough to fit on a standard printed circuit card.
Single Event Transients (SETs) originating in linear bipolar integrated circuits are known to undermine the reliability of electronic systems operating in the radiation environment of space. Ionizing particle radiation produces a variety of SETs in linear bipolar circuits. The extent to which these SETs threaten system reliability depends on both their shapes (amplitude and width) and their threshold energies. In general, SETs with large amplitudes and widths are the most likely to propagate from a bipolar circuit's output through a subsystem. The danger these SET pose is that, if they become latched in a follow-on circuit, they could cause an erroneous system response. Long-term exposure of linear bipolar circuits to particle radiation produces total ionizing dose (TID) and/or displacement damage dose (DDD) effects that are characterized by a gradual degradation in some of the circuit's electrical parameters. For example, an operational amplifier's gain-bandwidth product is reduced by exposure to ionizing radiation, and it is this reduction that contributes to the distortion of the SET shapes. In this paper, we compare SETs produced in a pristine LM124 operational amplifier with those produced in one exposed to ionizing radiation for three different operating configurations - voltage follower (VF), inverter with gain (IWG), and non-inverter with gain (NIWG). Each configuration produces a unique set of transient shapes that change following exposure to ionizing radiation. An important finding is that the changes depend on operating configuration; some SETs decrease in amplitude, some remain relatively unchanged, some become narrower and some become broader.
An extensive investigation of irradiate-anneal (IRAN) screening against total dose radiation effects was carried out as part of a program to harden the Mariner Jupiter/Saturn 1977 (MJS'77) spacecraft to survive the Jupiter radiation belts. The method consists of irradiating semiconductor devices with Cobalt-60 to a suitable total dose under representative bias conditions and of separating the parts in the undesired tail of the distribution from the bulk of the parts by means of a predetermined acceptance limit. The acceptable devices are then restored close to their preirradiation condition by annealing them at an elevated temperature. IRAN was used when lot screen methods were impracticable due to lack of time, and when members of a lot showed a diversity of radiation response. The feasibility of the technique was determined by testing of a number of types of linear bipolar integrated circuits, analog switches, n-channel JFETS and bipolar transistors. Based on the results of these experiments a number of device types were selected for IRAN of flight parts in the MJS'77 spacecraft systems. The part types, screening doses, acceptance criteria, number of parts tested and rejected as well as the program steps are detailed.
Dose rate effects are examined in linear bipolar transistors at high and low dose rates. At high dose rates, approximately 50% of the damage anneals at room temperature, even though these devices exhibit enhanced damage at low dose rate. The unexpected recovery of a significant fraction of the damage after tests at high dose rate requires changes in existing test standards. Tests at low temperature with a one-second radiation pulse width show that damage continues to increase for more than 3000 seconds afterward, consistent with predictions of the CTRW model for oxides with a thickness of 700 nm.
The design concepts, analyses, and development of GaAs monolithic microwave integrated circuit (MMIC) linear-phase and digital modulators for the next generation of space-borne communications systems are summarized. The design approach uses a compact lumped element quadrature hybrid and Metal Semiconductor Field Effect Transistors (MESFET)-varactors to provide low loss and well-controlled phase performance for deep space transponder (DST) applications. The measured results of the MESFET-diode show a capacitance range of 2:1 under reverse bias, and a Q of 38 at 10 GHz. Three cascaded sections of hybrid-coupled reflection phase shifters were modeled and simulations performed to provide an X-band (8415 +/- 50 MHz) DST phase modulator with +/- 2.5 radians of peak phase deviation. The modulator will accommodate downlink signal modulation with composite telemetry and ranging data, with a deviation linearity tolerance of +/- 8 percent and insertion loss of less than 8 +/- 0.5 dB. The MMIC digital modulator is designed to provide greater than 10 Mb/s of bi-phase modulation at X-band.
The design concepts, analyses, and the development of GaAs monolithic microwave integrated circuit (MMIC) linear-phase and digital modulators for the next generation of spaceborne communications systems are summarized. The design approach uses a very compact lumped-element, quadrature hybrid, and MESFET-varactors to provide low-loss and well-controlled phase performance for deep-space transponder (DST) applications. The measured results of the MESFET-diode show a capacitance range of 2:1 under reverse bias, and a Q of 38 at 10 GHz. Three cascaded sections of hybrid-coupled reflection phase shifters have been modeled and simulations performed to provide an X-band (8415 +/- 50 MHz) DST phase modulator with +/-2.5 radians of peak phase deviation.
Simple circuit monitors the frequency of PFM /Pulse Frequency Modulated/ telemetry signals. This discriminator can be used as a constant current integrator in such circuits as linear sweep and time delay.
Dc-to-dc power converter multiplies input supply potential by factor of nearly 40. Design does not make use of transformers or inductors but effects voltage boost-up by capacitive energy transfer. Circuit primarily made up of banks of capacitors, connected by network of integrated-circuit relays. Converter functionally linear voltage amplifier with fixed gain figure. Bipolar in operation. Output fully floating, and excellent dc isolation between input and output terminals.
Generator, comprised largely of integrated circuits, has operational amplifier connected as integrator to provide linear voltage ramp, pair of logic gates and one-shot multivibrator function as sweep reverse circuit feeding the integrator. Solid state switch effects generator hold capability.
This paper investigates trellis structures of linear block codes for the integrated circuit (IC) implementation of Viterbi decoders capable of achieving high decoding speed while satisfying a constraint on the structural complexity of the trellis in terms of the maximum number of states at any particular depth. Only uniform sectionalizations of the code trellis diagram are considered. An upper-bound on the number of parallel and structurally identical (or isomorphic) subtrellises in a proper trellis for a code without exceeding the maximum state complexity of the minimal trellis of the code is first derived. Parallel structures of trellises with various section lengths for binary BCH and Reed-Muller (RM) codes of lengths 32 and 64 are analyzed. Next, the complexity of IC implementation of a Viterbi decoder based on an L-section trellis diagram for a code is investigated. A structural property of a Viterbi decoder called add-compare-select (ACS)-connectivity which is related to state connectivity is introduced. This parameter affects the complexity of wire-routing (interconnections within the IC). The effect of five parameters namely: (1) effective computational complexity; (2) complexity of the ACS-circuit; (3) traceback complexity; (4) ACS-connectivity; and (5) branch complexity of a trellis diagram on the very large scale integration (VISI) complexity of a Viterbi decoder is investigated. It is shown that an IC implementation of a Viterbi decoder based on a nonminimal trellis requires less area and is capable of operation at higher speed than one based on the minimal trellis when the commonly used ACS-array architecture is considered.
Theoretical analysis and some experiments have shown that the silicon-on-insulator (SOI) 4-gate transistors known as G4-FETs can be used as building blocks of four-quadrant analog voltage multiplier circuits. Whereas a typical prior analog voltage multiplier contains between six and 10 transistors, it is possible to construct a superior voltage multiplier using only four G4-FETs. A G4-FET is a combination of a junction field-effect transistor (JFET) and a metal oxide/semiconductor field-effect transistor (MOSFET). It can be regarded as a single transistor having four gates, which are parts of a structure that affords high functionality by enabling the utilization of independently biased multiple inputs. The structure of a G4-FET of the type of interest here (see Figure 1) is that of a partially-depleted SOI MOSFET with two independent body contacts, one on each side of the channel. The drain current comprises of majority charge carriers flowing from one body contact to the other that is, what would otherwise be the side body contacts of the SOI MOSFET are used here as the end contacts [the drain (D) and the source (S)] of the G4-FET. What would otherwise be the source and drain of the SOI MOSFET serve, in the G4-FET, as two junction-based extra gates (JG1 and JG2), which are used to squeeze the channel via reverse-biased junctions as in a JFET. The G4-FET also includes a polysilicon top gate (G1), which plays the same role as does the gate in an accumulation-mode MOSFET. The substrate emulates a fourth MOS gate (G2). By making proper choices of G4-FET device parameters in conjunction with bias voltages and currents, one can design a circuit in which two input gate voltages (Vin1,Vin2) control the conduction characteristics of G4-FETs such that the output voltage (Vout) closely approximates a value proportional to the product of the input voltages. Figure 2 depicts two such analog multiplier circuits. In each circuit, there is the following: The input and output voltages are differential, The multiplier core consists of four G4- FETs (M1 through M4) biased by a constant current sink (Ibias), and The G4-FETs in two pairs are loaded by two identical resistors (RL), which convert a differential output current to a differential output voltage. The difference between the two circuits stems from their input and bias configurations. In each case, provided that the input voltages remain within their design ranges as determined by considerations of bias, saturation, and cutoff, then the output voltage is nominally given by Vout = kVin1Vin2, where k is a constant gain factor that depends on the design parameters and is different for the two circuits. In experimental versions of these circuits constructed using discrete G4- FETs and resistors, multiplication of voltages in all four quadrants (that is, in all four combinations of input polarities) was demonstrated, and deviations of the output voltages from linear dependence on the input voltages were found to amount to no more than a few percent. It is anticipated that in fully integrated versions of these circuits, the deviations from linearity will be made considerably smaller through better matching of devices.
How rapidly can a many-body quantum system generate randomness? Using path integral methods, we demonstrate that Brownian quantum systems have circuit complexity that grows linearly with time. In particular, we study Brownian clusters of N spins or fermions with time-dependent all-to-all interactions, and calculate the Frame Potential to characterize complexity growth in these models. In both cases the problem can be mapped to an effective statistical mechanics problem which we study using path integral methods. Within this framework it is straightforward to show that the kth Frame Potential comes within ϵ of the Haar value after a time of order t ~ kN + k log k + log ϵ –1 . Using a bound on the diamond norm, this implies that such circuits are capable of coming very close to a unitary k-design after a time of order t ~ kN. We also consider the same question for systems with a time-independent Hamiltonian and argue that a small amount of time-dependent randomness is sufficient to generate a k-design in linear time provided the underlying Hamiltonian is quantum chaotic. These models provide explicit examples of linear complexity growth that are analytically tractable and are directly applicable to practical applications calling for unitary k-designs.
An integrating IR detector array for imaging is provided in a hybrid circuit with InSb mesa diodes in a linear array, a single J-FET preamplifier for readout, and a silicon integrated circuit multiplexer. Thin film conductors in a fan out pattern deposited on an Al2O3 substrate connect the diodes to the multiplexer, and thick film conductors also connect the reset switch and preamplifier to the multiplexer. Two phase clock pulses are applied with a logic return signal to the multiplexer through triax comprised of three thin film conductors deposited between layers. A lens focuses a scanned image onto the diode array for horizontal read out while a scanning mirror provides vertical scan.
A 32-GHz six-element linear transmitter array utilizing monolithic microwave integrated circuit (MMIC) phase shifters and power amplifiers was designed and tested as part of the development of a spacecraft array feed for NASA deep-space communications applications. Measurements of the performance of individual phase shifters, power amplifiers, and microstrip radiators were carried out, and electronic beam steering of the linear array was demonstrated. The switched-line phase shifters were accurate to within 7 percent on average and the power amplifier 1-dB compressed output power varied over 0.3 dB. The array had a beamwidth of 7.5 deg and demonstrated acceptable beam steering over + or - 8 deg. From the results, it can be concluded that this MMIC phased array has adequate beam-scanning capability for use in the two-dimensional array. The areas that need to be improved are the efficiency of the MMIC power amplifier and the insertion loss of the MMIC phase shifter.
This paper investigates trellis structures of linear block codes for the IC (integrated circuit) implementation of Viterbi decoders capable of achieving high decoding speed while satisfying a constraint on the structural complexity of the trellis in terms of the maximum number of states at any particular depth. Only uniform sectionalizations of the code trellis diagram are considered. An upper bound on the number of parallel and structurally identical (or isomorphic) subtrellises in a proper trellis for a code without exceeding the maximum state complexity of the minimal trellis of the code is first derived. Parallel structures of trellises with various section lengths for binary BCH and Reed-Muller (RM) codes of lengths 32 and 64 are analyzed. Next, the complexity of IC implementation of a Viterbi decoder based on an L-section trellis diagram for a code is investigated. A structural property of a Viterbi decoder called ACS-connectivity which is related to state connectivity is introduced. This parameter affects the complexity of wire-routing (interconnections within the IC). The effect of five parameters namely: (1) effective computational complexity; (2) complexity of the ACS-circuit; (3) traceback complexity; (4) ACS-connectivity; and (5) branch complexity of a trellis diagram on the VLSI complexity of a Viterbi decoder is investigated. It is shown that an IC implementation of a Viterbi decoder based on a non-minimal trellis requires less area and is capable of operation at higher speed than one based on the minimal trellis when the commonly used ACS-array architecture is considered.
This paper investigates trellis structures of linear block codes for the IC (integrated circuit) implementation of Viterbi decoders capable of achieving high decoding speed while satisfying a constraint on the structural complexity of the trellis in terms of the maximum number of states at any particular depth. Only uniform sectionalizations of the code trellis diagram are considered. An upper bound on the number of parallel and structurally identical (or isomorphic) subtrellises in a proper trellis for a code without exceeding the maximum state complexity of the minimal trellis of the code is first derived. Parallel structures of trellises with various section lengths for binary BCH and Reed-Muller (RM) codes of lengths 32 and 64 are analyzed. Next, the complexity of IC implementation of a Viterbi decoder based on an L-section trellis diagram for a code is investigated. A structural property of a Viterbi decoder called ACS-connectivity which is related to state connectivity is introduced. This parameter affects the complexity of wire-routing (interconnections within the IC). The effect of five parameters namely: (1) effective computational complexity; (2) complexity of the ACS-circuit; (3) traceback complexity; (4) ACS-connectivity; and (5) branch complexity of a trellis diagram on the VLSI complexity of a Viterbi decoder is investigated. It is shown that an IC implementation of a Viterbi decoder based on a non-minimal trellis requires less area and is capable of operation at higher speed than one based on the minimal trellis when the commonly used ACS-array architecture is considered.
This paper updates the long-term 500 C electrical testing results from 6H-SiC junction field effect transistors (JFETs) and small integrated circuits that were introduced at ICSCRM-2007. Two packaged JFETs have now been operated in excess of 7000 hours at 500 degC with less than 10% degradation in linear I-V characteristics. Several simple digital and analog demonstration integrated circuits successfully operated for 2000-6500 hours at 500 C before failure.