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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 37 records · Page 2
All sourcesNASA NTRSDOE OSTI
NASA NTRS1977

Technology of GaAs metal-oxide-semiconductor solar cells

The growth of an oxide interfacial layer was recently found to increase the open-circuit voltage (OCV) and efficiency by up to 60 per cent in GaAs metal-semiconductor solar cells. Details of oxidation techniques to provide the necessary oxide thickness and chemical structure and using ozone, water-vapor-saturated oxygen, or oxygen gas discharges are described, as well as apparent crystallographic orientation effects. Preliminary results of the oxide chemistry obtained from X-ray, photoelectron spectroscopy are given. Ratios of arsenic oxide to gallium oxide of unity or less seem to be preferable. Samples with the highest OVC predominantly have As(+3) in the arsenic oxide rather than As(+5). A major difficulty at this time is a reduction in OCV by 100-200 mV when the antireflection coating is vacuum deposited.

Stirn, R. J.↗
NASA NTRS1994

Epitaxial heterojunctions of oxide semiconductors and metals on high temperature superconductors

Epitaxial heterojunctions formed between high temperature superconductors and metallic or semiconducting oxide barrier layers are provided. Metallic perovskites such as LaTiO3, CaVO3, and SrVO3 are grown on electron-type high temperature superconductors such as Nd(1.85)Ce(0.15)CuO(4-x). Alternatively, transition metal bronzes of the form A(x)MO(3) are epitaxially grown on electron-type high temperature superconductors. Also, semiconducting oxides of perovskite-related crystal structures such as WO3 are grown on either hole-type or electron-type high temperature superconductors.

Vasquez, Richard P.↗
NASA NTRS1974

Experimental investigation of a shielded complementary Metal-Oxide Semiconductor (MOS) structure

A shielded integrated complimentary MOS transistor structure is described which is used to prevent field inversion in the region not occupied by the gates and which permits the use of a thinner field oxide, reduces the chip area, and has provision for simplified multilayer connections. The structure is used in the design of a static shift register and results in a 20% reduction in area.

Lin, H. C.↗
NASA NTRS2009

Synthesis Methods, Microscopy Characterization and Device Integration of Nanoscale Metal Oxide Semiconductors for Gas Sensing in Aerospace Applications

A comparison is made between SnO2, ZnO, and TiO2 single-crystal nanowires and SnO2 polycrystalline nanofibers for gas sensing. Both nanostructures possess a one-dimensional morphology. Different synthesis methods are used to produce these materials: thermal evaporation-condensation (TEC), controlled oxidation, and electrospinning. Advantages and limitations of each technique are listed. Practical issues associated with harvesting, purification, and integration of these materials into sensing devices are detailed. For comparison to the nascent form, these sensing materials are surface coated with Pd and Pt nanoparticles. Gas sensing tests, with respect to H2, are conducted at ambient and elevated temperatures. Comparative normalized responses and time constants for the catalyst and noncatalyst systems provide a basis for identification of the superior metal-oxide nanostructure and catalyst combination. With temperature-dependent data, Arrhenius analyses are made to determine an activation energy for the catalyst-assisted systems.

VanderWal, Randy L.↗
NASA NTRS1993

Demonstration of Y1Ba2Cu3O(7-delta) and complementary metal-oxide-semiconductor device fabrication on the same sapphire substrate

We report the first fabrication of active semiconductor and high-temperature superconducting devices on the same substrate. Test structures of complementary MOS transistors were fabricated on the same sapphire substrate as test structures of Y1Ba2Cu3O(7-delta) flux-flow transistors, and separately, Y1Ba2Cu3O(7-delta) superconducting quantum interference devices utilizing both biepitaxial and step-edge Josephson junctions. Both semiconductor and superconductor devices were operated at 77 K. The cofabrication of devices using these disparate yet complementary electronic technologies on the same substrate opens the door for the fabrication of true semiconductive/superconductive hybrid integrated circuits capable of exploiting the best features of each of these technologies.

Burns, M. J.↗
NASA NTRS1979

A study to investigate the chemical stability of gallium phosphate oxide/gallium arsenide phosphide

The elemental composition with depth into the oxide films was examined using secondary ion mass spectrometry. Results indicate that the layers are arsenic-deficient through the bulk of the oxide and arsenic-rich near both the oxide surface and the oxide-semiconductor interface region. Phosphorus is incorporated into the oxide in an approximately uniform manner. The MIS capacitor structures exhibited deep-depletion characteristics and hysteresis indicative of electron trapping at the oxide-semiconductor interface. Post-oxidation annealing of the films in argon or nitrogen generally results in slightly increased dielectric leakage currents and decreased C-V hysteresis effects, and is associated with arsenic loss at the oxide surface. The results of bias-temperature stress experiments indicate that the major instability effects are due to changes in the electron trapping behavior. No changes were observed in the elemental profiles following electrical stressing, indicating that the grown films are chemically stable under device operating conditions.

Kuhlman, G. J.↗
NASA NTRS1991

Heavy-ion induced single-event upset in integrated circuits

The cosmic ray environment in space can affect the operation of Integrated Circuit (IC) devices via the phenomenon of Single Event Upset (SEU). In particular, heavy ions passing through an IC can induce sufficient integrated current (charge) to alter the state of a bistable circuit, for example a memory cell. The SEU effect is studied in great detail in both static and dynamic memory devices, as well as microprocessors fabricated from bipolar, Complementary Metal Oxide Semiconductor (CMOS) and N channel Metal Oxide Semiconductor (NMOS) technologies. Each device/process reflects its individual characteristics (minimum scale geometry/process parameters) via a unique response to the direct ionization of electron hole pairs by heavy ion tracks. A summary of these analytical and experimental SEU investigations is presented.

Zoutendyk, J. A.↗
NASA NTRS1974

Four phase logic systems

A four-phase logic system is provided which includes at least four logic networks connected in parallel between a single power line and a reference potential. A four-phase clock generator generates four distinct clock signals from a single-phase clock input at data rate. Each logic network comprises a pair of complementary metal-oxide-semiconductor integrated transistors (CMOST). Each metal-oxide-Semiconductor transistor (MOST) in the pair is responsive to a clock signal which turns the transistor on or off. In each network, there is also at least one MOST which is responsive to a logic signal. The logic transistor is connected in cascade with the pair of CMOSTs.

Petersen, H. L.↗
NASA NTRS1982

Automated semiconductor diffusion and oxidation facility

A semiconductor diffusion and oxidation facility (totally automated) was developed. Wafers arrived on an air track, automatically loaded into a furnace tube, processed, returned to track, and sent on to the next process. The entire process was controlled by a computer.

Source record↗
NASA NTRS2000

Active pixel sensor having intra-pixel charge transfer with analog-to-digital converter

An imaging device formed as a monolithic complementary metal oxide semiconductor Integrated circuit in an industry standard complementary metal oxide semiconductor process, the integrated circuit including a focal plane array of pixel cells, each one of the cells including a photogate overlying the substrate for accumulating photo-generated charge in an underlying portion of the substrate, a readout circuit including at least an output field effect transistor formed in the substrate, and a charge coupled device section formed on the substrate adjacent the photogate having a sensing node connected to the output transistor and at least one charge coupled device stage for transferring charge from the underlying portion of the substrate to the sensing node and an analog-to-digital converter formed in the substrate connected to the output of the readout circuit.

Fossum, Eric R.↗
NASA NTRS1999

Active pixel sensor array with multiresolution readout

An imaging device formed as a monolithic complementary metal oxide semiconductor integrated circuit in an industry standard complementary metal oxide semiconductor process, the integrated circuit including a focal plane array of pixel cells, each one of the cells including a photogate overlying the substrate for accumulating photo-generated charge in an underlying portion of the substrate and a charge coupled device section formed on the substrate adjacent the photogate having a sensing node and at least one charge coupled device stage for transferring charge from the underlying portion of the substrate to the sensing node. There is also a readout circuit, part of which can be disposed at the bottom of each column of cells and be common to all the cells in the column. The imaging device can also include an electronic shutter formed on the substrate adjacent the photogate, and/or a storage section to allow for simultaneous integration. In addition, the imaging device can include a multiresolution imaging circuit to provide images of varying resolution. The multiresolution circuit could also be employed in an array where the photosensitive portion of each pixel cell is a photodiode. This latter embodiment could further be modified to facilitate low light imaging.

Fossum, Eric R.↗
NASA NTRS1995

Active pixel sensor with intra-pixel charge transfer

An imaging device formed as a monolithic complementary metal oxide semiconductor integrated circuit in an industry standard complementary metal oxide semiconductor process, the integrated circuit including a focal plane array of pixel cells, each one of the cells including a photogate overlying the substrate for accumulating photo-generated charge in an underlying portion of the substrate, a readout circuit including at least an output field effect transistor formed in the substrate, and a charge coupled device section formed on the substrate adjacent the photogate having a sensing node connected to the output transistor and at least one charge coupled device stage for transferring charge from the underlying portion of the substrate to the sensing node.

Fossum, Eric R.↗