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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 37 records · Page 2
All sourcesNASA NTRSDOE OSTI
DOE OSTI2025

Testing the limits of ITkPixV2: the ATLAS inner tracker pixel detector readout chip

The ITkPixV2 chip is the final production readout chip for the ATLAS Phase 2 Inner Tracker (ITk) upgrade at the upcoming High-Luminosity LHC (HL-LHC). Due to the extraordinarily high peak luminosity at the HL-LHC of 5 × 1034 cm-1 s-1, ITkPixV2 must meet significant increases in nearly all design requirements compared to the current ATLAS Inner Detector (ID), including a 10× increase in trigger rate, a 7.5× increase in hit rate, a 3× increase in radiation tolerance, and a 12.5× decrease in pixel current draw per unit area, all while maintaining a similar power per unit area as present pixel detectors. Here we present the first measurements of the ITkPixV2 chip operated at the limits of the full chip design requirements, including in particular a measurement of the activity-induced current of the chip as a function of increasing hit rate.

Le Pottier, L↗
DOE OSTI2021

Design, construction, and test of the Gas Pixel Detectors for the IXPE mission

Due to be launched in late 2021, the Imaging X-ray Polarimetry Explorer (IXPE) is a NASA Small Explorer mission designed to perform polarization measurements in the 2–8 keV band, complemented with imaging, spectroscopy and timing capabilities. At the heart of the focal plane is a set of three polarization-sensitive Gas Pixel Detectors (GPD), each based on a custom ASIC acting as a charge-collecting anode. In this paper we shall review the design, manufacturing, and test of the IXPE focal-plane detectors, with particular emphasis on the connection between the science drivers, the performance metrics and the operational aspects. We shall present a thorough characterization of the GPDs in terms of effective noise, trigger efficiency, dead time, uniformity of response, and spectral and polarimetric performance. In addition, we shall discuss in detail a number of instrumental effects that are relevant for high-level science analysis—particularly as far as the response to unpolarized radiation and the stability in time are concerned.

79 ASTRONOMY AND ASTROPHYSICS↗
DOE OSTI2021

Compact, low power, high resolution ADC per pixel for large area pixel detectors

A compact ADC circuit can include one or more comparators, and a serial DAC (Digital-to-Analog) circuit that provides a signal to the comparator (or comparators). In addition, the ADC circuit can include a serial DAC redistribution sequencer that can provide a plurality of signals as input to the serial DAC circuit and is subject to a redistribution cycle and which receives as input a signal from a data multiplexer whose input connects electronically to an output of the comparator. The circuit can further include an ADC code register that provides an ADC output that connects electronically to the output of the comparator and the input to the data multiplexer. Shared logic circuitry for sharing common logic between pixels can be included, wherein the shared logic circuitry connects electronically to the data multiplexer and the ADC code register, wherein the shared logic circuitry promotes area and power savings for the pixel detector circuit.

Zimmerman, Tom↗
DOE OSTI2023

Compact, low power, high resolution ADC per pixel for large area pixel detectors

A compact ADC circuit can include one or more comparators, and a serial DAC (Digital-to-Analog) circuit that provides a signal to the comparator (or comparators). In addition, the ADC circuit can include a serial DAC redistribution sequencer that can provide a plurality of signals as input to the serial DAC circuit and is subject to a redistribution cycle and which receives as input a signal from a data multiplexer whose input connects electronically to an output of the comparator. The circuit can further include an ADC code register that provides an ADC output that connects electronically to the output of the comparator and the input to the data multiplexer. Shared logic circuitry for sharing common logic between pixels can be included, wherein the shared logic circuitry connects electronically to the data multiplexer and the ADC code register, wherein the shared logic circuitry promotes area and power savings for the pixel detector circuit.

Fahim, Farah↗
DOE OSTI2020

A pixel detector ROIC with a 3-bit, 40 Msps synchronous ADC per pixel for HL LHC

The prototype Fermi Compact Muon Solenoid (CMS) Pixel (FCP130), manufactured in a 130 nm process, is a readout integrated circuit (ROIC) designed for the High Luminosity upgrade of the Large Hadron Collider. It employs a synchronous analog to digital converter (ADC) for the front-end design, with signal processing and data conversion within a single bunch crossing of 25 ns. It is therefore capable of accurately detecting hits occurring in consecutive bunch crossings, without off-time registration of events, making it particularly suitable for the inner most layers of the vertex detector. The ROIC consists of a matrix of 48 × 160 pixels, each 100 × 30 μm2 in size. Each pixel contains a charge sensitive preamplifier with self-biasing leakage current compensation, eight auto-zero comparators and a Gray code encoder for a 3-bit flash-type ADC. The total power consumption is approximately 24 μW per pixel. The measured noise at the output of all the hit comparators across the ROIC is < 80 e- with threshold dispersion < 110 e-RMS, which allows an in-time threshold setting of ~ 1000 e-.

43 PARTICLE ACCELERATORS↗
DOE OSTI2023

In-Pixel Readout IC with compact in-pixel ADC for Pixel detectors at HL LHC

The prototype Smart Pixel concept test chip (SP28), designed in a CMOS 28 nm bulk process, is a proof of concept readout integrated circuit (ROIC) designed for a future Phase III High Luminosity upgrade of the Large Hadron Collider. It employs a synchronous analog to digital converter (ADC) for the front-end design, with signal processing and data conversion within a single bunch crossing of 25 ns. It is therefore capable of accurately detecting hits occurring in consecutive bunch crossings, without off-time registration of events and pileup insensitivity, making it particularly suitable for the inner most layers of the vertex detector. The ROIC consists of a matrix of 32 × 16 pixels, each 25 × 25 µm 2 in size. Each pixel contains a charge sensitive preamplifer with leakage current compensation, three auto-zero comparators for a 2-bit fash-type ADC. The total power consumption is approximately 5 µW per pixel. The measured noise at the output of all the hit comparators across the ROIC is < 90 e- with threshold dispersion < 45 e-RMS, which allows an in-time threshold setting of ≈ 475 e-.

Parpillon, Benjamin↗
DOE OSTI2025

Development of a test system for data links of the ATLAS Inner Tracker (ITk) upgrade silicon pixel detector

This contribution introduces a novel test system developed to evaluate the signal transmission quality in high-speed data links for the 2026 Inner Tracker (ITk) upgrade of the ATLAS experiment. Using an FPGA-based data acquisition (DAQ) framework, the setup can run simultaneous Bit Error Rate (BER) tests for up to 64 channels and generate virtual eye diagrams, for qualifying the ∼26k electrical links at the ATLAS ITk data rate of 1.28 Gb/s. The paper includes results from system calibration, yielding its contribution to the measured losses, and preliminary results from tests of prototype and pre-production assemblies of on-detector links of the three ATLAS ITk Pixel subsystems.

47 OTHER INSTRUMENTATION↗
DOE OSTI2025

High-energy X-ray imaging with a Germanium MM-PAD hybrid pixel detector

Germanium is a high-Z sensor material with excellent energy resolution and attractive properties for high-energy photon detection. Despite its advantages, the need for cryogenic operation and challenges in the fabrication of pixelated high-purity germanium have hindered the development of segmented detectors. We report on the fabrication and performance of a germanium imaging detector with 150 μm pixel pitch hybridized to the MM-PAD ASIC. The detector was capable of high-resolution radiographic imaging and has a fast temporal response. Additionally, we describe the detector's upper operating temperature limits using both the MM-PAD and MARS ASICs, achieving stable operation up to 130 K and 190 K, respectively.

36 MATERIALS SCIENCE↗
DOE OSTI2025

A 28 nm multiply-accumulate ASIC architecture for on-chip data compression in MHz frame rate X-ray and electron pixel detectors

Modern X-ray detector systems urgently require compact, efficient, and fast data compression schemes to handle the transmission of big data from pixel arrays, enabling frame rates in the MHz regime. Here, in this work, a data compression ASIC that implements a streaming fixed-length lossy compression scheme is introduced and analyzed, proving the feasibility and benefits of on-chip compression. The compression scheme utilizes a vector matrix product logic, which performs a number of floating-point multiplications, additions, and accumulations. The logic is verified, synthesized, and shown to fit in the area resource available for the X-ray detector under study, which comprises 192 × 168 pixels each of 12-bit width, and having a total area of 20 mm× 20 mm, about 2 mm× 20 mm of which are available for the digital logic. Several system architectures, precisions, and compression ratios ranging from 100 to 250 were analyzed to pave the way for on-chip fixed-length compression (e.g., principal component analysis, singular value decomposition) and data reduction (e.g., azimuthal integration) for X-ray and electron detectors.

Data compression↗
DOE OSTI2023

Digital encoding algorithm for pixelated detectors

A detector for imaging and efficiently digitizing a spatial distribution of photon flux includes pixel circuits that compressively encode pixel values generated by integrated analog to digital converters (ADCs). On-pixel digital compression circuits (DCCs) implement compression to increase continuous frame rate by reducing the number of bits per pixel while keeping quantization error below Poisson noise. Several mapping algorithms for photon-counting and charge-integrating detectors and compact digital logic implementations are presented.

Hammer, Michael P.↗
DOE OSTI2020

Dynamically Reconfigurable Data Readout of Pixel Detectors for Automatic Synchronization with Data Acquisition Systems

Reconfigurable detectors with dynamically selectable sensing and readout modes are highly desirable for implementing edge computing as well as enabling advanced imaging techniques such as foveation. The concept of a camera system capable of simultaneous passive imaging and dynamic ranging in different regions of the detector is presented. Such an adaptive-autonomous detector with both spatial and temporal control requires programmable window of exposure (time frames), ability to switch between readout modes such as full-frame imaging and zero-suppressed data, modification of the number of pixel data bits and independent programmability for distinct detector regions. In this work, a method is presented for seamlessly changing time frames and readout modes without data corruption while still ensuring that the data acquisition system (DAQ) does not need to stop and resynchronize at each change of setting, thus avoiding significant dead time. Data throughput is maximized by using a minimum unique data format, rather than lengthy frame headers, to differentiate between consecutive frames. A data control and transmitter (DCT) synchronizes data transfer from the pixel to the periphery, reconfigures the data to transmit it serially off-chip, while providing optimized decision support based on a DAQ definable mode. Measurements on a test structure demonstrate that the DCT can operate at 1 GHz in a 65 nm LP CMOS process.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗
DOE OSTI2023

Forward Pixel Detector for the Phase 2 Upgrade of CMS And Module Testing at UIC

High-Luminosity Large Hadron Collider (HL-LHC) upgrade aims to increase performance. In order to efficiently handle the larger particle flux and increased radiation, an upgrade is planned for the inner Tracker of the Compact Muon Solenoid (CMS) detector, which is located at the innermost part of the CMS. To efficiently reconstruct and track particles, the existing pixel tracker will be upgraded with novel sensors, readout chips, and front-end electronics designed to handle increased data rates. These improvements will allow the detector to track particles more precisely. In the United States, we are working on assembling new sensor modules to be inserted into disks, referred to as TFPX, for installation in the CMS detector for the HL-LHC era. We are currently testing the prototype of TFPX modules to ensure the upgrade is carried out in the best way possible. The University of Ilinois Chicago has been tasked with testing the final versions of the TFPX sensor modules before they are sent to CERN to be installed into the CMS detector. This work is supported by NSF.

72 PHYSICS OF ELEMENTARY PARTICLES AND FIELDS↗
DOE OSTI2024

Skipper-in-CMOS: Nondestructive Readout With Subelectron Noise Performance for Pixel Detectors

The Skipper-in-CMOS image sensor integrates the nondestructive readout capability of skipper charge coupled devices (Skipper-CCDs) with the high conversion gain of a pinned photodiode (PPD) in a CMOS imaging process while taking advantage of in-pixel signal processing. This allows both single photon counting as well as high frame rate readout through highly parallel processing. The first results obtained from a ${15} \times {15}~\mu $ m2 pixel cell of a Skipper-in-CMOS sensor fabricated in Tower Semiconductor’s commercial 180-nm CMOS image sensor process are presented. Measurements confirm the expected reduction of the readout noise with the number of samples down to deep subelectron noise of $0.15\text {e}^ - $ , demonstrating the charge transfer operation from the PPD and the single photon counting operation when the sensor is exposed to light. This article also discusses new testing strategies employed for its operation and characterization.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗
DOE OSTI2023

Search for Dark Matter using mono-Higgs and the ATLAS Pixel Detector (Final Report)

A large component of the mass-energy of the universe is composed of dark matter (DM), whose properties and interactions with known particles are not yet understood. Searches for DM at the Large Hadron Collider (LHC) provide important information, complementary to direct and indirect detection experiments, that is necessary to determine whether an observed signal indeed stems from DM. Furthermore, the discovery of the Higgs boson provides a unique avenue to search for DM because the potential interaction of the Higgs with DM would lead to the unique signature of a Higgs boson recoiling against DM. This process is typically referred to as mono-Higgs because DM does not interact strongly with most known particles and will therefore pass unseen through the detector, leading to a single detected Higgs boson and a large imbalance of momentum. Due to the strength of the interactions of the Higgs with Standard Model particles, it is unlikely for a Higgs boson to be radiated from initial state quarks. Therefore, the observation of this process would provide direct insight into the mechanism by which DM couples to known particles. The objective of this research program is to search for the dark matter particles produced in association with a Higgs boson at the LHC using the ATLAS (A Toroidal LHC Apparatus) detector, specifically when the Higgs boson decays to two bottom quarks. This research will benefit greatly from the development of innovative identification techniques of boosted Higgs bosons. The program includes the upgrade of the ATLAS Pixel readout system, which is critical to maintain high performance of tracking, vertexing, and boosted Higgs tagging in the planned higher luminosity run of the LHC.

72 PHYSICS OF ELEMENTARY PARTICLES AND FIELDS↗