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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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All sourcesNASA NTRSDOE OSTI
NASA NTRS2008

Silicon-On-Insulator (SOI) Devices and Mixed-Signal Circuits for Extreme Temperature Applications

Electronic systems in planetary exploration missions and in aerospace applications are expected to encounter extreme temperatures and wide thermal swings in their operational environments. Electronics designed for such applications must, therefore, be able to withstand exposure to extreme temperatures and to perform properly for the duration of the missions. Electronic parts based on silicon-on-insulator (SOI) technology are known, based on device structure, to provide faster switching, consume less power, and offer better radiation-tolerance compared to their silicon counterparts. They also exhibit reduced current leakage and are often tailored for high temperature operation. However, little is known about their performance at low temperature. The performance of several SOI devices and mixed-signal circuits was determined under extreme temperatures, cold-restart, and thermal cycling. The investigations were carried out to establish a baseline on the functionality and to determine suitability of these devices for use in space exploration missions under extreme temperatures. The experimental results obtained on selected SOI devices are presented and discussed in this paper.

Patterson, Richard↗
NASA NTRS1989

Growth and characterization of single crystal insulators on silicon

An overview of the growth and characterization of epitaxial insulators on semiconductors is presented. The potential applications include semiconductor-on-insulator structures, three-dimensional and/or high-density integrated circuits, optoelectronic applications such as integrated waveguides and improved gate insulators. The growth and physical characterization of epitaxial fluorides on semiconductors are discussed. Consideration is also given to the epitaxial overgrowth of epitaxial metal layers with CaF2 as well as to the formation of a novel superlattice of Ca particles in epitaxial CaF2.

Schowalter, Leo J.↗
NASA NTRS1969

Radiation tolerant silicon nitride insulated gate field effect transistors

Metal-Insulated-Semiconductor Field Effect Transistor /MISFET/ device uses a silicon nitride passivation layer over a thin silicon oxide layer to enhance the radiation tolerance. It is useful in electronic systems exposed to space radiation environment or the effects of nuclear weapons.

Newman, P. A.↗
NASA NTRS2004

Fabrication of Microshutter Arrays for James Webb Space Telescope

Two-dimensional MEMS microshutter arrays are being developed at NASA Goddard Space Flight Center for use in the near-infrared region on the Next Generation Space Telescope (NGST). The microshutter arrays are designed for the selective transmission of light with high efficiency and high contrast. The NGST environment requires cryogenic operation at 45K. Microshutter arrays are fabricated out of silicon-oxide-insulated (SOI) silicon wafers. Arrays are close-packed silicon nitride membranes with a pixel size of 100x100 microns. Individual shutters are patterned with a torsion flexure permitting shutters to open 90 degrees with a minimized mechanical stress concentration. The mechanical shutter arrays are fabricated using MEMS technologies. The processing includes a multi-layer metal deposition and patterning of shutter electrodes and magnetic pads, reactive ion etching (RE) of the front side to form shutters out of the nitride membrane, an anisotropic back-etch for wafer thinning, followed by a deep RIE (DRIE) back-etch down to the nitride shutter membrane to form frames and relieve shutters from the silicon substrate. An additional metal deposition and patterning is used to form back electrodes. Shutters are actuated using a magnetic force and latched using an electrostatic force.

Li, Mary J.↗
NASA NTRS2004

Microshutter Arrays for James Webb Space Telescope

Two-dimensional MEMS microshutter arrays are being developed at NASA Goddard Space Flight Center for use in the near-infrared region on the James Webb Space Telescope (JWST). The microshutter arrays are designed for the selective transmission of light with high efficiency and high contrast. The JWST environment requires cryogenic operation at 35K. Microshutter arrays are fabricated out of silicon-oxide-insulated (SOI) silicon wafers. Arrays are close-packed silicon nitride membranes with a pixel size of 100x200 p. Individual shutters are patterned with a torsion flexure permitting shutters to open 90 degrees with a minimized mechanical stress concentration. The mechanical shutter arrays are fabricated using MEMS technologies. The processing includes a multi- layer metal deposition and patterning of shutter electrodes and magnetic pads, reactive ion etching (NE) of the front side to form shutters out of the nitride membrane, an anisotropic back-etch for wafer thinning, followed by a deep RIE (DRIE) back-etch down to the nitride shutter membrane to form W e s and relieve shutters from the silicon substrate. An additional metal deposition and patterning is used to form back electrodes. Shutters are actuated using a magnetic force and latched using an electrostatic force. . . . KEYWORDS: microshutter, MEMS, RIE, DRIE, micro-optics, near inbred, space telescope

Li, Mary J.↗
NASA NTRS1991

Silicon dioxide with a silicon interfacial layer as an insulating gate for highly stable indium phosphide metal-insulator-semiconductor field effect transistors

A novel gate insulator consisting of silicon dioxide (SiO2) with a thin silicon (Si) interfacial layer has been investigated for high-power microwave indium phosphide (InP) metal-insulator-semiconductor field effect transistors (MISFETs). The role of the silicon interfacial layer on the chemical nature of the SiO2/Si/InP interface was studied by high-resolution X-ray photoelectron spectroscopy. The results indicated that the silicon interfacial layer reacted with the native oxide at the InP surface, thus producing silicon dioxide, while reducing the native oxide which has been shown to be responsible for the instabilities in InP MISFETs. While a 1.2-V hysteresis was present in the capacitance-voltage (C-V) curve of the MIS capacitors with silicon dioxide, less than 0.1 V hysteresis was observed in the C-V curve of the capacitors with the silicon interfacial layer incorporated in the insulator. InP MISFETs fabricated with the silicon dioxide in combination with the silicon interfacial layer exhibited excellent stability with drain current drift of less than 3 percent in 10,000 sec, as compared to 15-18 percent drift in 10,000 sec for devices without the silicon interfacial layer. High-power microwave InP MISFETs with Si/SiO2 gate insulators resulted in an output power density of 1.75 W/mm gate width at 9.7 GHz, with an associated power gain of 2.5 dB and 24 percent power added efficiency.

Kapoor, V. J.↗
NASA NTRS1982

High temperature silicon carbide impregnated insulating fabrics

High temperature insulating articles having improved performance characteristics are described. The articles comprise fabrics of closely woven refractory or heat resistant fibers having particles of silicon carbide dispersed at least partially through the fabric and bonded to the fibers with an emulsifiable polyethylene wax. Such articles exhibit significantly increased high temperature emittance characteristics and an improved retention of integrity and flexibility after prolonged exposure to high temperature.

Schomburg, C.↗
NASA NTRS1984

Recent developments in semiconductor research

Recent findings drawn from various laboratories focused toward a new understanding of the nature of crystal growth and how impurities are incorporated or excluded from the lattice were considered. From these findings a heuristic approach is given for improving the uniformity and charge carrier concentration of thin semiconductor films. Such improvement is considered essential to achieve respectable yield on large scale integrated circuits. A tentative conclusion is drawn which indicates that if the host compound crystal reactants are provided to the growing crystal surface in a reasonably stoichiometric manner, it is virtually impossible to include impurities into a growing crystal surface held at a sufficiently low temperature; impurities are incorporated into the crystal by gettering action of crystal defects located one and two monlayers beneath the growing surface. Devices in 3-5 semiconductors based on heterojunctions and two dimensional electron gases are noted and reliability concerns are voiced. Alternatives and novel device structures such as truly single crystal high quality silicon on insulator and beta silicon carbide devices are presented.

Yoder, M. N.↗
NASA NTRS1999

Waterproof Silicone Coatings of Thermal Insulation and Vaporization Method

Thermal insulation composed of porous ceramic material can be waterproofed by producing a thin silicone film on the surface of the insulation by exposing it to volatile silicone precursors at ambient conditions. When the silicone precursor reactants are multi-functional siloxanes or silanes containing alkenes or alkynes carbon groups higher molecular weight films can be produced. Catalyst are usually required for the silicone precursors to react at room temperature to form the films. The catalyst are particularly useful in the single component system e.g. dimethylethoxysilane (DNMS) to accelerate the reaction and decrease the time to waterproof and protect the insulation. In comparison to other methods, the chemical vapor technique assures better control over the quantity and location of the film being deposited on the ceramic insulation to improve the waterproof coating.

Cagliostro, Domenick E.↗
NASA NTRS1972

Acoustic-wave detection via a piezoelectric field-effect transducer.

An oriented piezoelectric film has been incorporated in the insulator region of a silicon insulated-gate field-effect transistor to provide a sensitive high-frequency strain transducer. With this device, strains as low as 10 to the -8th power have been detected, and gauge factors of roughly 7000 have been attained for applied ac strains at 5.6 MHz.

Greeneich, E. W.↗
NASA NTRS1975

Theoretical transducer properties of piezoelectric insulator FET transducers

An oriented piezoelectric film incorporated in the insulator region of a silicon insulated-gate field-effect transistor (FET) results in a sensitive high-frequency strain transducer. Theory governing the transducer properties of the piezoelectric insulator FET transducer is presented. Equations are developed which relate the drain current of the device to induced polarizations of the piezoelectric layer. The highest frequency of surface strains to which the FET transducer can respond is determined by the FET frequency response - ultimately by the channel transit time. This frequency can extend to the GHz range. The low-frequency response to applied strain is determined by the dielectric relaxation frequency of the piezoelectric layer.

Greeneich, E. W.↗
NASA NTRS2005

Making Wide-IF SIS Mixers with Suspended Metal-Beam Leads

A process that employs silicon-on-insulator (SOI) substrates and silicon (Si) micromachining has been devised for fabricating wide-intermediate-frequency-band (wide-IF) superconductor/insulator/superconductor (SIS) mixer devices that result in suspended gold beam leads used for radio-frequency grounding. The mixers are formed on 25- m-thick silicon membranes. They are designed to operate in the 200 to 300 GHz frequency band, wherein wide-IF receivers for tropospheric- chemistry and astrophysical investigations are necessary. The fabrication process can be divided into three sections: 1. The front-side process, in which SIS devices with beam leads are formed on a SOI wafer; 2. The backside process, in which the SOI wafer is wax-mounted onto a carrier wafer, then thinned, then partitioned into individual devices; and 3. The release process, in which the individual devices are separated using a lithographic dicing technique. The total thickness of the starting 4-in. (10.16-cm)-diameter SOI wafer includes 25 m for the Si device layer, 0.5 m for the buried oxide (BOX) layer, and 350 m the for Si-handle layer. The front-side process begins with deposition of an etch-stop layer of SiO2 or AlN(x), followed by deposition of a Nb/Al- AlN(x) /Nb trilayer in a load-locked DC magnetron sputtering system. The lithography for four of a total of five layers is performed in a commercial wafer-stepping apparatus. Diagnostic test dies are patterned concurrently at certain locations on the wafer, alongside the mixer devices, using a different mask set. The conventional, self-aligned lift-off process is used to pattern the SIS devices up to the wire level.

Kaul, Anupama↗
NASA NTRS1972

Bonding of reusable surface insulation with low density silicone foams

The development and evaluation of a reduced density, high reliable foamed bond strain isolation system for attaching reusable surface insulation to the space shuttle structure are reported. Included are data on virgin materials as well as on materials that received 100 cycles of exposure to 650 F for approximately 20 minutes per cycle. Room temperature vulcanizing silicon elastomers meet all the requirments for an adhesive bonding system.

Hiltz, A. A.↗
NASA NTRS2012

Measurement of Two-Phase Flow and Heat Transfer Parameters using Infrared Thermometry

A novel technique to measure heat transfer and liquid film thickness distributions over relatively large areas for two-phase flow and heat transfer phenomena using infrared (IR)thermometry is described. IR thermometry is an established technology that can be used to measure temperatures when optical access to the surface is available in the wavelengths of interest. In this work, a midwave IR camera (3.6-5.1 microns) is used to determine the temperature distribution within a multilayer consisting of a silicon substrate coated with a thin insulator. Since silicon is largely transparent to IR radiation, the temperature of the inner and outer walls of the multilayer can be measured by coating selected areas with a thin, IR opaque film. If the fluid used is also partially transparent to IR, the flow can be visualized and the liquid film thickness can be measured. The theoretical basis for the technique is given along with a description of the test apparatus and data reduction procedure. The technique is demonstrated by determining the heat transfer coefficient distributions produced by droplet evaporation and flow boiling heat transfer.

Kim, Tae-Hoon↗
NASA NTRS2016

500 C Electronic Packaging and Dielectric Materials for High Temperature Applications

High-temperature environment operable sensors and electronics are required for exploring the inner solar planets and distributed control of next generation aeronautical engines. Various silicon carbide (SiC) high temperature sensors, actuators, and electronics have been demonstrated at and above 500C. A compatible packaging system is essential for long-term testing and application of high temperature electronics and sensors. High temperature passive components are also necessary for high temperature electronic systems. This talk will discuss ceramic packaging systems developed for high temperature electronics, and related testing results of SiC circuits at 500C and silicon-on-insulator (SOI) integrated circuits at temperatures beyond commercial limit facilitated by these high temperature packaging technologies. Dielectric materials for high temperature multilayers capacitors will also be discussed. High-temperature environment operable sensors and electronics are required for probing the inner solar planets and distributed control of next generation aeronautical engines. Various silicon carbide (SiC) high temperature sensors, actuators, and electronics have been demonstrated at and above 500C. A compatible packaging system is essential for long-term testing and eventual applications of high temperature electronics and sensors. High temperature passive components are also necessary for high temperature electronic systems. This talk will discuss ceramic packaging systems developed for high electronics and related testing results of SiC circuits at 500C and silicon-on-insulator (SOI) integrated circuits at temperatures beyond commercial limit facilitated by high temperature packaging technologies. Dielectric materials for high temperature multilayers capacitors will also be discussed.

dielectric performance↗