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35 records · Page 2

Silicon device performance measurements to support temperature range enhancement

The results of the NPN bipolar transistor (BJT) (2N6023) breakdown voltage measurements were analyzed. Switching measurements were made on the NPN BJT, the insulated gate bipolar transistor (IGBT) (TA9796) and the N-channel metal oxide semiconductor field effect transistor (MOSFET) (RFH75N05E). Efforts were also made to build a H-bridge inverter. Also discussed are the plans that have been made to do life testing on the devices, to build an inductive switching test circuit and to build a dc/dc switched mode converter.

Johnson, R. Wayne↗

Long-Term Reliability of a Hard-Switched Boost Power Processing Unit Utilizing SiC Power MOSFETs

Silicon carbide (SiC) power devices have demonstrated many performance advantages over their silicon (Si) counterparts. As the inherent material limitations of Si devices are being swiftly realized, wide-band-gap (WBG) materials such as SiC have become increasingly attractive for high power applications. In particular, SiC power metal oxide semiconductor field effect transistors' (MOSFETs) high breakdown field tolerance, superior thermal conductivity and low-resistivity drift regions make these devices an excellent candidate for power dense, low loss, high frequency switching applications in extreme environment conditions. In this paper, a novel power processing unit (PPU) architecture is proposed utilizing commercially available 4H-SiC power MOSFETs from CREE Inc. A multiphase straight boost converter topology is implemented to supply up to 10 kilowatts full-scale. High Temperature Gate Bias (HTGB) and High Temperature Reverse Bias (HTRB) characterization is performed to evaluate the long-term reliability of both the gate oxide and the body diode of the SiC components. Finally, susceptibility of the CREE SiC MOSFETs to damaging effects from heavy-ion radiation representative of the on-orbit galactic cosmic ray environment are explored. The results provide the baseline performance metrics of operation as well as demonstrate the feasibility of a hard-switched PPU in harsh environments.

Ikpe, Stanley A.↗

Atomic-scale defects generated in the early/intermediate stages of dielectric breakdown in Si/SiO 2 transistors

In this study, electrically detected magnetic resonance and near-zero-field magnetoresistance measurements were used to study atomic-scale traps generated during high-field gate stressing in Si/SiO 2 MOSFETs. The defects observed are almost certainly important to time-dependent dielectric breakdown. The measurements were made with spin-dependent recombination current involving defects at and near the Si/SiO 2 boundary. The interface traps observed are P b0 and P b1 centers, which are silicon dangling bond defects. The ratio of P b0 /P b1 is dependent on the gate stressing polarity. Electrically detected magnetic resonance measurements also reveal generation of E' oxide defects near the Si/SiO 2 interface. Near-zero-field magnetoresistance measurements made throughout stressing reveal that the local hyperfine environment of the interface traps changes with stressing time; these changes are almost certainly due to the redistribution of hydrogen near the interface.

42 ENGINEERING↗

Shielded silicon gate complementary MOS integrated circuit.

An electrostatic shield for complementary MOS integrated circuits was developed to minimize the adverse effects of stray electric fields created by the potentials in the metal interconnections. The process is compatible with silicon gate technology. N-doped polycrystalline silicon was used for all the gates and the shield. The effectiveness of the shield was demonstrated by constructing a special field plate over certain transistors. The threshold voltages obtained on an oriented silicon substrate ranged from 1.5 to 3 V for either channel. Integrated inverters performed satisfactorily from 3 to 15 V, limited at the low end by the threshold voltages and at the high end by the drain breakdown voltage of the n-channel transistors. The stability of the new structure with an n-doped silicon gate as measured by the shift in C-V curve under 200 C plus or minus 20 V temperature-bias conditions was better than conventional aluminum gate or p-doped silicon gate devices, presumably due to the doping of gate oxide with phosphorous.

Lin, H. C.↗

Aluminum Boron Nitride Ferroelectric Field-Effect Transistors With ZnO Semiconductor Channel

The discovery of ferroelectricity in hafnium zirconium oxide (HfxZr 1−x O2) and related fluorite materials has spurred interest in ferroelectric devices suitable for integration with silicon integrated circuits (ICs), especially those that can be embedded in the back-end-of-line (BEOL) process. More recently, ferroelectricity has been found in wurtzite aluminum nitride-based materials, such as scandium and boron-doped aluminum nitride (Al 1−x ScxN and Al 1−x BxN). Although these materials currently have undesirably large coercive electric fields, and small breakdown electric field-to-coercive electric field ratio, their low processing temperatures and large remanent polarization offer intriguing possibilities for device applications. Furthermore, we report ferroelectric field-effect transistors (FeFETs) with a 15 nm thick Al0.88B0.12N layer and an 11 nm ZnO semiconductor channel, achieving a memory window >1 V and switching voltages ( V switch ) <±10 V.

42 ENGINEERING↗

A study of the deposition of carbide coatings on graphite fibers

The chemical vapor deposition of boron carbide and silicon carbide on graphite fibers to increase their electrical resistance was studied. Silicon carbide coatings were applied without degradation of the mechanical properties of the filaments. These coatings typically added 1000 ohms to the resistance of a filament as measured between two mercury pools. When SiC-coated filaments were oxidized by refluxing in boiling phosphoric acid, average resistance increased by an additional 1000 ohms; in addition resistance increases as high as 150 K ohms and breakdown voltages as high as 17 volts were noted. Data on boron carbide coatings indicated that such coatings would not be effective in increasing resistance, and would degrade the mechanical properties.

Suplinskas, R. J.↗

An Overview of Experiments and Modeling of Polysiloxane-Coated Thermal Protection Systems for Missions to Mars, Titan, and Beyond.

Phenolic Impregnated Carbon Ablator (PICA) gained heritage during the historic Stardust mission, where it successfully returned samples from a comet’s tail and has since been instrumental in delivering payloads to the surface of Mars [1-3]. Most recently, PICA enabled the safe return of samples collected from asteroid Bennu as part of the OSIRIS-REx mission. This rich legacy underscores PICA’s critical role in allowing NASA’s most ambitious exploration missions. However, the friable nature of its phenolic phase presents challenges during handling and pre-launch activities. To mitigate this issue, PICA is coated with a polysiloxane resin system, which serves to suppress particulate dispersion and thereby safeguard spacecraft components. A comprehensive understanding of the polysiloxane resin’s behavior is imperative, as it profoundly shapes the material response of PICA during atmospheric entry by influencing its thermal and oxidative stability. This influence extends to thermocouple plugs embedded within thermal protection systems. These plugs have demonstrated their significance in missions such as Mars Science Laboratory (MSL) and Mars 2020, where the MEDLI and MEDLI2 instrumentation suites delivered in-valuable insights into the performance of thermal protection systems during entry into the Martian atmosphere [4]. Looking ahead, missions such as Dragonfly, set to descend into Titan’s dense atmosphere, aim to leverage advanced sensor technologies to further refine our understanding of thermal protection response [5]. Moreover, thermocouple plugs play an essential role in validating cutting-edge material response models, such as those pioneered under NASA’s Entry Systems Modeling Project (ESM), designed, in-part, to predict the operational integrity of thermal protection systems under the extreme stresses of atmospheric entry. To achieve these modeling goals, ground-based experiments are crucial to provide the foundational data necessary for developing and refining these predictive tools. To this end, an extensive test campaign was conducted at the Hypersonic Materials Environmental Test System (HyMETS) to investigate the high-temperature behavior of the polysiloxane resin in an air environment [6]. These experiments revealed critical phenomena, including the formation of a silicon oxycarbide layer that enhances oxidation resistance, moderates surface temperatures, and alters in-depth thermal response. Building on these findings, subsequent tests were designed to simulate atmospheric entry conditions in reactive gases, such as CO2 and N2, to mimic the environments of Mars and Titan, respectively, as well as non-reactive gases representing the atmospheres of the Ice Giants (Neptune and Uranus). A heating rate dependent decomposition mechanism has been identified for the polysiloxane resin under oxidizing conditions (Fig. 1). In the initial stage, the resin and the underlying thermal protection system undergo pyrolysis, rapidly generating a thin amorphous silicon oxycarbide interwoven with carbonaceous char and residual fibers from PICA. During the second stage, the nascent oxide layer establishes a robust, oxidation-resistant thermal barrier coating, which significantly impedes heat transfer to the underlying carbonaceous char, resulting in a stagnation of the surface temperature. A key factor contributing to this thermal resistance is the low recombination efficiency of atomic oxygen (γ), which further diminishes the heat load on the material’s interior layers [7]. Moreover, as the surface temperature stagnates, the silicon oxycarbide phase separates into distinct regions of silica and free graphite. Ultimately, when the heat flux reaches a critical threshold, a third stage is triggered, leading to the breakdown of the coating through carbothermal reduction, exposing the underlying char layer. This exposure leads to a dramatic surface temperature spike, driven by highly exothermic reactions between atomic oxygen and the char layer, further accelerating material degradation. A detailed mass and heat transfer model of PICA coated with polysiloxane resin was implemented in the Porous material Analysis Toolbox based on OpenFOAM, PATO [8]. The initial stage was considered negligible in this model because the resin decomposition occurs rapidly within a thin surface layer. Instead, the coating was directly considered as an oxygen-resistant thermal barrier coating. For the second stage, the thin amorphous silicon oxycarbide was treated as a pure silica surface to simplify the thermochemical behavior. The model ac-counts for surface equilibrium processes using representative elements of the coating-environment system. For the third stage, specific boundary conditions were developed to estimate the onset and progression of the coating removal. Two-dimensional material response simulations were conducted to compare uncoated and coated PICA using boundary conditions calibrated with HyMETS data. Fig. 2 illustrates that the simulations closely align with experimental data, successfully reproducing measured temperature profiles. This work will include the latest advancements in the coating model, including the calibration of recombination of atomic oxygen at the surface during the second phase. These simulated results will be further validated against additional CO2 data points from HyMETS, reinforcing the models’ predictive capabilities. These mechanisms and their effects on thermal protection systems, including thermochemical behavior and thermocouple probe performance in extreme environments, provide crucial insights for optimizing spacecraft designs that safeguard scientific payload and ensure mission success in future planetary exploration endeavors.

Active Oxidation↗

Development of non-volatile semiconductor memory

A 256 word by 8-bit random access memory chip was developed utilizing p channel, metal gate metal-nitride-oxide-silicon (MNOS) technology; with operational characteristics of a 2.5 microsecond read cycle, a 6.0 microsecond write cycle, 800 milliwatts of power dissipation; and retention characteristics of 10 to the 8th power read cycles before data refresh and 5000 hours of no power retention. Design changes were implemented to reduce switching currents that caused parasitic bipolar transistors inherent in the MNOS structure to turn on. Final wafer runs exhibited acceptable yields for a die 250 mils on a side. Evaluation testing was performed on the device in order to determine the maturity of the device. A fixed gate breakdown mechanism was found when operated continuously at high temperature.

Heikkila, W. W.↗

Product assurance technology for procuring reliable, radiation-hard, custom LSI/VLSI electronics

Advanced measurement methods using microelectronic test chips are described. These chips are intended to be used in acquiring the data needed to qualify Application Specific Integrated Circuits (ASIC's) for space use. Efforts were focused on developing the technology for obtaining custom IC's from CMOS/bulk silicon foundries. A series of test chips were developed: a parametric test strip, a fault chip, a set of reliability chips, and the CRRES (Combined Release and Radiation Effects Satellite) chip, a test circuit for monitoring space radiation effects. The technical accomplishments of the effort include: (1) development of a fault chip that contains a set of test structures used to evaluate the density of various process-induced defects; (2) development of new test structures and testing techniques for measuring gate-oxide capacitance, gate-overlap capacitance, and propagation delay; (3) development of a set of reliability chips that are used to evaluate failure mechanisms in CMOS/bulk: interconnect and contact electromigration and time-dependent dielectric breakdown; (4) development of MOSFET parameter extraction procedures for evaluating subthreshold characteristics; (5) evaluation of test chips and test strips on the second CRRES wafer run; (6) two dedicated fabrication runs for the CRRES chip flight parts; and (7) publication of two papers: one on the split-cross bridge resistor and another on asymmetrical SRAM (static random access memory) cells for single-event upset analysis.

Buehler, M. G.↗

New processes and materials for ultraviolet detection with solid state devices

The three major effects that degrade external responsivity of silicon from the 1/lambda theoretical curve for a quantum detector are: surface reflectance, surface recombination, and junction depth. Since the p-n junction must be very shallow, problems relating to surface are further enhanced. MOS type of processing is necessary. HCl oxides and numerous acid clean-ups are utilized in order to obtain a contamination free surface with low Qss levels. Stringent process controls such as CV shifts, spreading resistance measurements, thickness monitoring etc., are used to analyze the surface contaminations, surface mobile charges, surface concentrations, junction depth, oxide thickness etc. Low surface concentrations of 10 to the 18th atoms/cu cm are achieved by low temperature boron nitride depositions. Shallow junction depths of the order of a few tenths of a micron are achieved by low temperature controlled diffusions. In order to improve breakdown characteristics of these shallow junction devices, field plate and deep diffused p(+) ring geometries are used.

Chopra, D.↗

Probing the Atomic Scale Mechanisms of Time Dependent Dielectric Breakdown in Si/SiO 2 MOSFETs (June 2022)

Here we report on an atomic-scale study of trap generation in the initial/intermediate stages of time-dependent dielectric breakdown (TDDB) in high-field stressed (100) Si/SiO2 MOSFETs using two powerful analytical techniques: electrically detected magnetic resonance (EDMR) and near-zero-field magnetoresistance (NZFMR). We find the dominant EDMR-sensitive traps generated throughout the majority of the TDDB process to be silicon dangling bonds at the (100) Si/SiO2 interface (Pb0 and Pb1 centers) for both the spin-dependent recombination (SDR) and trap-assisted tunneling (SDTAT) processes. We find this generation to be linked to both changes in the calculated interface state densities as well as changes in the NZFMR spectra for recombination events at the interface, indicating a redistribution of mobile magnetic nuclei which we conclude could only be due to the redistribution of hydrogen at the interface. Additionally, we observe the generation of traps known as E’ centers in EDMR measurements at lower experimental temperatures via SDR measurements at the interface. Our work strongly suggests the involvement of a rate-limiting step in the tunneling process between the silicon dangling bonds generated at the interface and the ones generated throughout the oxide.

36 MATERIALS SCIENCE↗

A Comparison of Radiation-Induced and High-Field Electrically Stress-Induced Interface Defects in Si/SiO 2 MOSFETs via Electrically Detected Magnetic Resonance

Here, we utilize electrically detected magnetic resonance (EDMR) measurements to compare high-field stressed, and gamma irradiated Si/SiO 2 metal–oxide–silicon (MOS) structures. We utilize spin-dependent recombination (SDR) EDMR detected using the Fitzgerald and Grove dc I-V approach to compare the effects of high-field electrical stressing and gamma irradiation on defect formation at and near the Si/SiO 2 interface. As anticipated, both greatly increase the concentration of P b centers (silicon dangling bonds at the interface) densities. The irradiation also generated a significant increase in the dc I-V EDMR response of E' centers (oxygen vacancies in the SiO 2 films), whereas the generation of an E' EDMR response in high-field stressing is much weaker than in the gamma irradiation case. These results likely suggest a difference in their physical distribution resulting from radiation damage and high electric field stressing.

42 ENGINEERING↗

Process for High-Rate Fabrication of Alumina Nanotemplates

An anodizing process, at an early stage of development at the time of reporting the information for this article, has shown promise as a means of fabricating alumina nanotemplates integrated with silicon wafers. Alumina nanotemplates are basically layers of alumina, typically several microns thick, in which are formed approximately regular hexagonal arrays of holes having typical diameters of the order of 10 to 100 nm. Interest in alumina nanotemplates has grown in recent years because they have been found to be useful as templates in the fabrication of nanoscale magnetic, electronic, optoelectronic, and other devices. The present anodizing process is attractive for the fabrication of alumina nanotemplates integrated with silicon wafers in two respects: (1) the process involves self-ordering of the holes; that is, the holes as formed by the process are spontaneously arranged in approximately regular hexagonal arrays; and (2) the rates of growth (that is, elongation) of the holes are high enough to make the process compatible with other processes used in the mass production of integrated circuits. In preparation for fabrication of alumina nanotemplates in this process, one first uses electron-beam evaporation to deposit thin films of titanium, followed by thin films of aluminum, on silicon wafers. Then the alumina nanotemplates are formed by anodizing the aluminum layers, as described below. In experiments in which the process was partially developed, the titanium films were 200 A thick and the aluminum films were 5 m thick. The aluminum films were oxidized to alumina, and the arrays of holes were formed by anodizing the aluminum in aqueous solutions of sulfuric and/or oxalic acid at room temperature (see figure). The diameters, spacings, and rates of growth of the holes were found to depend, variously, on the composition of the anodizing solution, the applied current, or the applied potential, as follows: In galvanostatically controlled anodizing, regardless of the chemical composition of the solution, relatively high current densities (50 to 100 mA/cm2) resulted in arrays of holes that were more nearly regular than were those formed at lower current densities. . The rates of elongation of the holes were found to depend linearly on the applied current density: the observed factor of proportionality was 1.2 (m/h)/(mA/cm2). For a given fixed current density and room temperature, the hole diameters were found to depend mainly on the chemical compositions of the anodizing solutions. The holes produced in sulfuric acid solutions were smaller than those produced in oxalic acid solutions. The arrays of holes produced in sulfuric acid were more ordered than were those produced in oxalic acid. . The breakdown voltage was found to decrease logarithmically with increasing concentration of sulfuric acid. The breakdown voltage was also found to decrease with temperature and to be accompanied by a decrease in hole diameter. The hole diameter was found to vary linearly with applied potential, with a slope of 2.1 nm/V. This slope differs from slopes (2.2 and 2.77 nm/V) reported for similar prior measurements on nanotemplates made from bulk aluminum. The differences among these slopes may be attributable to differences among impurities and defects in bulk and electron-beam-evaporated aluminum specimens.

Myung, Nosang↗

Active Oxidation of SiC

The high temperature oxidation of silicon carbide occurs in either a passive or active mode, depending on temperature and oxygen potential. Passive oxidation forms a protective oxide film which limits attack of the SiC:SiC(s) + 3/2 O2(g) = SiO2(s) + CO(g.) Active oxidation forms a volatile oxide and leads to extensive attack of the SiC: SiC(s) + O2(g) = SiO(g) + CO(g). The transition points and rates of active oxidation are a major issue. Previous studies are reviewed and the leading theories of passive/active transitions summarized. Comparisons are made to the active/passive transitions in pure Si, which are relatively well-understood. Critical questions remain about the difference between the active-to-passive transition and passive-to-active transition. For Si, Wagner [2] points out that the active-to-passive transition is governed by the criterion for a stable Si/SiO2 equilibria and the passive-to-active transition is governed by the decomposition of the SiO2 film. This suggests a significant oxygen potential difference between these two transitions and our experiments confirm this. For Si, the initial stages of active oxidation are characterized by the formation of SiO(g) and further oxidation to SiO2(s) as micron-sized rods, with a distinctive morphology. SiC shows significant differences. The active-to-passive and the passive-to-active transitions are close. The SiO2 rods only appear as the passive film breaks down. These differences are explained in terms of the reactions at the SiC/SiO2 interface. In order to understand the breakdown of the passive film, pre-oxidation experiments are conducted. These involve forming dense protective scales of 0.5, 1, and 2 microns and then subjecting the samples with these scales to a known active oxidation environment. Microstructural studies show that SiC/SiO2 interfacial reactions lead to a breakdown of the scale with a distinct morphology.

Jacobson, Nathan S.↗

Photoelectrochemical etching of silicon carbide (SiC) and its characterization

Silicon carbide (SiC) is an attractive semiconductor material for high speed, high density, and high temperature device applications due to its wide bandgap (2.2-3.2 eV), high thermal conductivity, and high breakdown electric field (4 x 10(exp 6) V/cm). An instrumental process in the fabrication of semiconductor devices is the ability to etch in a highly controlled and selective manner for direct patterning techniques. A novel technique in etching using electrochemistry is described. This procedure involves the ultraviolet (UV) lamp-assisted photoelectrochemical etching of n-type 3C- and 6H-SiC to enhance the processing capability of device structures in SiC. While under UV illumination, the samples are anodically biased in an HF based aqueous solution since SiC has photoconductive properties. In order for this method to be effective, the UV light must be able to enhance the production of holes in the SiC during the etching process thus providing larger currents with light from the photocurrents generated than those currents with no light. Otherwise dark methods would be used as in the case of p-type 3C-SiC. Experiments have shown that the I/V characteristics of the SiC-electrolyte interface reveal a minimum etch voltage of 3 V and 4 V for n- and p-type 3C-SiC, respectively. Hence it is possible for etch-stops to occur. Etch rates calculated have been as high as 0.67 micrometer/min for p-type, 1.4 micrometer/min for n-type, and 1.1 micrometer/min for pn layer. On n-type 3C- SiC, an oxide formation is present where after etching a yellowish layer corresponds to a low Si/C ratio and a white layer corresponds to a high Si/C ratio. P-type 3C-SiC shows a grayish layer. Additionally, n-type 6H-SiC shows a brown layer with a minimum etch voltage of 3 V.

Collins, D. M.↗

Electric Drive Technologies Consortium (EDTC)/ Cost competitive, high-Performance, highly Reliable (CPR) Power Devices on 4H-SiC (Final Report)

4H-Silicon carbide (4H-SiC) is a wide bandgap semiconductor that offers superior material properties over silicon, including higher critical electric field, thermal conductivity, and electron saturation velocity. These advantages make 4H-SiC highly attractive for high-voltage, high-efficiency power electronics. However, realizing the full potential of SiC requires device technologies that are not only high-performing but also manufacturable and reliable under real-world operating conditions. This report summarizes the outcomes of a five-year R&D effort funded by the U.S. Department of Energy (DOE) under the Electric Drive Technologies Consortium (EDTC), focused on developing cost-competitive, high-performance, and highly reliable (CPR) power devices on 4H-SiC substrates. The program targeted scalable and manufacturable 1.2 kV-class SiC MOSFETs optimized for next-generation electric vehicles, renewable energy systems, and industrial power conversion. The project delivered transformative advancements in SiC power device performance and ruggedness. Particularly, Specific on-resistance (R on,sp ) was reduced by up to 37%, from ~4.0 m$\Omega \cdot$cm 2 in earlier designs to an industry-leading 2.40 m$\Omega \cdot$cm 2 , driven by optimized doping, refined JFET widths, and layout engineering. Breakdown voltages (BV) exceeded 1600 V, marking improvement over legacy baselines, and demonstrating the robustness of newly implemented junction profiles and edge terminations. Short-circuit withstand time (SCWT) saw a remarkable 4$\times$ increase, from ~2 $\mu$s to over 8 $\mu$s, achieved through the successful deployment of deep P-well structures (~1.8–2.0 $\mu$m) via channeling implantation. This innovative process breakthrough enabled precise junction formation without MeV-class implantation tools, reduced leakage under high field stress, and allowed even the shortest-channel devices (down to 0.3 $\mu$m) to achieve both high BV and excellent ruggedness—breaking the traditional trade-off between conduction efficiency and blocking capability. Several novel architectures pushed the performance envelope further. JBSFETs—featuring embedded Schottky portions—eliminated bipolar degradation and drastically reduced third-quadrant leakage, while Ladder MOSFETs introduced a clever orthogonal conduction path that achieved a 15.4% reduction in R on,sp over standard linear designs. Switching performance reached new benchmarks: short-channel devices showed a 31% reduction in total switching energy compared to 0.5 $\mu$m counterparts, while maintaining manageable gate drive requirements. Layout-optimized structures not only improved transconductance but also accelerated switching transitions, pointing to real-world benefits in converter-level efficiency. The devices also passed rigorous reliability validation. Stress-tested across TDDB, HTGB, HTRB, HVP, and burn-in, the devices screened under 30 V/10 hr and 43 V/1 s protocols consistently exhibited tighter lifetime distributions and long-term oxide robustness. These screening techniques proved effective in identifying latent defects and ensuring deployment-grade reliability. Meanwhile, advanced 3D TCAD simulations revealed and resolved electric field hotspots—particularly in HEXFET corners—where fields exceeding 4.8 MV/cm were mitigated through geometry-aware layout corrections. Overall, the results of this project demonstrate a manufacturable and scalable SiC power device platform that addresses key DOE performance targets for efficient, robust, and reliable 1.2kV 4H-SiC Power Devices. The developed technologies represent a meaningful step forward in the commercial readiness of high-voltage SiC solutions and provide a strong foundation for continued advancement in wide bandgap power electronics.

42 ENGINEERING↗

Fast Growth of Ga2O3 on Highly Offcut (100)-Oriented Substrates

Beta-Ga2O3 has emerged as a leading candidate for next-generation power electronics, radio frequency (RF) switches, and extreme environment electronics due to a wide band gap (4.6 - 4.9 eV), high dopability (approximately 40 meV activation energy for an isolated silicon donor), and melt growth characteristics resulting in commercially available 4-inch substrates and commercial demonstrations of 6-inch substrates by multiple techniques. The (100) surface of Ga2O3 is highly desirable from a device and epitaxy standpoint - bulk growth of (100) material is more scalable than (010), the surface is nearly lattice-matched to p-type partner NiO, and Al2O3 incorporates at higher concentrations without phase separation. More importantly, the impact ionization coefficients along the [100] direction are low, leading to the highest possible critical fields. This is advantageous compared to the current state of the art, (001), due to reduced surface defects and increased possible breakdown voltage. However, the epitaxial growth rate on (100) surfaces is less than 10% of other faces due to weak bonding and favorable desorption, and on-axis (100) growth easily forms twin domains. Recent demonstrations have shown growth rate improvements from 0.4 nm/min to 1.5 nm/min by growing on (100) wafers that are offcut 6 degrees in the -c direction. These films show step-flow growth from (20-1) step-edges and high electron mobility due to suppressed twins. Despite these exciting results, offcuts greater than 6 degrees have not been explored due to the waste associated with grinding and polishing large offcuts. In this talk we will discuss the molecular beam epitaxy (MBE) growth and properties of Beta-Ga2O3 grown on (100) substrates offcut in the -c direction up to 13.4 degrees. These large offcuts are enabled by edge-fed film-defined growth (EFG) where the offcut is grown into the surface by pulling the crystal through the EFG die with the seed crystal rotated by the desired offcut angle. We will demonstrate that 13.4 degrees offcut substrates still exhibit a terraced (100) surface, and that a >10x increase (>5 nm/min) in growth rate is achieved. As previously reported on lower offcuts, we observe reversal of substrate twin domains around the (001) direction at the substrate-epilayer interface. We will discuss electrical properties including record-low (by MBE) unintentional doping densities of < 5E15 cm-3 and critical breakdown field in Schottky barrier diodes comparable with state-of-the-art (001) Ga2O3 without edge termination.

36 MATERIALS SCIENCE↗