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NASA NTRS1984

Soft-error generation due to heavy-ion tracks in bipolar integrated circuits

Both bipolar and MOS integrated circuits have been empirically demonstrated to be susceptible to single-particle soft-error generation, commonly referred to as single-event upset (SEU), which is manifested in a bit-flip in a latch-circuit construction. Here, the intrinsic characteristics of SEU in bipolar (static) RAM's are demonstrated through results obtained from the modeling of this effect using computer circuit-simulation techniques. It is shown that as the dimensions of the devices decrease, the critical charge required to cause SEU decreases in proportion to the device cross-section. The overall results of the simulations are applicable to most integrated circuit designs.

Zoutendyk, J. A.↗
NASA NTRS1986

Radiation Hardening of Computers

Single-event upsets reduced by use of oversize transistors. Computers made less susceptible to ionizing radiation by replacing bipolar integrated circuits with properly designed, complementary metaloxide-semiconductor (CMOS) circuits. CMOS circuit chips made highly resistant to single-event upset (SEU), especially when certain feedback resistors are incorporated. Redesigned chips also consume less power than original chips.

Nichols, D. K.↗
NASA NTRS1986

1986 Annual Conference on Nuclear and Space Radiation Effects, 23rd, Providence, RI, July 21-23, 1986, Proceedings

The present conference on the effects of nuclear and space radiation on electronic hardware gives attention to topics in the basic mechanisms of radiation effects, dosimetry and energy-dependent effects, electronic device radiation hardness assurance, SOI/SOS radiation effects, spacecraft charging and space radiation, IC radiation effects and hardening, single-event upset (SEU) phenomena and hardening, and EMP/SGEMP/IEMP phenomena. Specific treatments encompass the generation of interface states by ionizing radiation in very thin MOS oxides, the microdosimetry of meson energy deposited on 1-micron sites in Si, total dose radiation and engineering studies, plasma interactions with biased concentrator solar cells, the transient imprint memory effect in MOS memories, mechanisms leading to SEU, and the vaporization and breakdown of thin columns of water.

Ellis, Thomas D.↗
NASA NTRS1988

Studies Of Single-Event-Upset Models

Report presents latest in series of investigations of "soft" bit errors known as single-event upsets (SEU). In this investigation, SEU response of low-power, Schottky-diode-clamped, transistor/transistor-logic (TTL) static random-access memory (RAM) observed during irradiation by Br and O ions in ranges of 100 to 240 and 20 to 100 MeV, respectively. Experimental data complete verification of computer model used to simulate SEU in this circuit.

Zoutendyk, J. A.↗
NASA NTRS1988

Estimating Rates Of Single-Event Upsets

Mathematical model yields estimates of upper and lower bounds on rates of single-event upsets (SEU's) in logic circuits. SEU's are reversible changes in logic states, caused by single high-energy ions. Energetic ions passed through device along tracks perpendicular to surface, to determine parameters of model. Used to estimate rates caused by ions of various energies incident at arbitrary angles. Useful in design of integrated circuits as high-density memories for minimal susceptibility to bit errors.

Zoutendyk, John A.↗
NASA NTRS1988

Measuring Critical Charges For Single-Event Upsets

Concept for determining susceptibility of integrated circuits to single-event upsets (SEU's) based on direct measurement of critical charge causing upset. Test circuit is modified version of standard complementary metal-oxide/semiconductor static cell. Contains six transistors, connected to form latch that retains state of cell set by input pulses. Makes possible to evaluate vulnerability to SEU during design and development of digital equipment.

Buehler, Martin G.↗
NASA NTRS1988

New Mode For Single-Event Upsets

Report presents theory and experimental data regarding newly discovered mode for single-event upsets, (SEU's) in complementary metal-oxide/semiconductor, static random-access memories, CMOS SRAM's. SEU cross sections larger than those expected from previously known modes given rise to speculation regarding additional mode, and subsequent cross-section measurements appear to confirm speculation.

Zoutendyk, John A.↗
NASA NTRS1989

Spread Of Charge From Ion Tracks In Integrated Circuits

Single-event upsets (SEU's) propagate to adjacent cells in integrated memory circuits. Findings of experiments in lateral transport of electrical-charge carriers from ion tracks in 256K dynamic randon-access memories (DRAM's). As dimensions of integrated circuits decrease, vulnerability to SEU's increases. Understanding gained enables design of less vulnerable circuits.

Zoutendyk, John A.↗
NASA NTRS1990

Single event induced transients in I/O devices - A characterization

The results of single-event upset (SEU) testing performed to evaluate the parametric transients, i.e., amplitude and duration, in several I/O devices, and the impact of these transients are discussed. The failure rate of these devices is dependent on the susceptibility of interconnected devices to the resulting transient change in the output of the I/O device. This failure rate, which is a function of the susceptibility of the interconnected device as well as the SEU response of the I/O device itself, may be significantly different from an upset rate calculated without taking these factors into account. The impact at the system level is discussed by way of an example.

Newberry, D. M.↗
NASA NTRS1993

Clementine Sensor Processing System

The design of the DSPSE Satellite Controller (DSC) is baselined as a single-string satellite controller. The DSC performs two main functions: health and maintenance of the spacecraft; and image capture, storage, and playback. The DSC contains two processors: a radiation-hardened Mil-Std-1750, and a commercial R3000. The Mil-Std-1750 processor performs all housekeeping operations, while the R3000 is mainly used to perform the image processing functions associated with the navigation functions, as well as performing various experiments. The DSC also contains a data handling unit (DHU) used to interface to various spacecraft imaging sensors and to capture, compress, and store selected images onto the solid-state data recorder. The development of the DSC evolved from several key requirements; the DSPSE satellite was to do the following: (1) have a radiation-hardened spacecraft control system and be immune to single-event upsets (SEU's); (2) use an R3000-based processor to run the star tracker software that was developed by SDIO (due to schedule and cost constraints, there was no time to port the software to a radiation-hardened processor); and (3) fly a commercial processor to verify its suitability for use in a space environment. In order to enhance the DSC reliability, the system was designed with multiple processing paths. These multiple processing paths provide for greater tolerance to various component failures. The DSC was designed so that all housekeeping processing functions are performed by either the Mil-Std-1750 processor or the R3000 processor. The image capture and storage is performed either by the DHU or the R3000 processor.

Feldstein, A. A.↗
NASA NTRS1994

Making A D-Latch Sensitive To Alpha Particles

Standard complementary metal oxide/semiconductor (CMOS) D-latch integrated circuit modified to increase susceptibility to single-event upsets (SEU's) (changes in logic state) caused by impacts of energetic alpha particles. Suitable for use in relatively inexpensive bench-scale SEU tests of itself and of related integrated circuits like static random-access memories.

Buehler, Martin G.↗
NASA NTRS1993

Complementary heterojunction FET technology for space application

A 32-bit serial integer multiplier was designed to investigate the yield and performance of complementary heterojunction FET (CHFET) technology. This is the largest reported CHFET logic circuit. The maximum operating frequency was 500 MHz. Very low power dissipation of 3 mW was obtained at 5 MHz operation. Single-event upset (SEU) characteristics of CHFET devices and latches were also measured and indicates the potential for SEU hard circuits for space and military applications.

Larue, George↗
NASA NTRS1993

SEU/SRAM as a Process Monitor

The SEU/SRAM is a 4-kbit Static Random Access Memory (SRAM) designed to detect Single-Event Upsets (SEUs) produced by high energy particles. This device was used to determine the distribution in the memory cell spontaneous flip potential.

distribution residual plots↗
NASA NTRS1995

Determination Of LETs Of SRAMs By Use Of A Laser

Report describes experimental study of use of microelectronic advanced laser scanner (MEALS) to cause single-event upsets (SEUs) in integrated logic circuits. Basic concepts of SEU testing by use of MEALS described in "Laser Scanner Tests for Single-Event Upsets" (NPO-18216), "Single-Event-Upset Laser Scanner With Optical Bias" (NPO-18217), and "More About Laser Scanner Tests for Single-Event Upsets" (NPO-18494). Study part of continuing effort to study SEU effects of ionizing radiation on such circuits and to use MEALS as relatively inexpensive SEU-prescreening laboratory apparatus serving as alternative to heavy-ion acclerator.

Kim, Quiesup↗
NASA NTRS1988

Empirical Modeling Of Single-Event Upset

Experimental study presents examples of empirical modeling of single-event upset in negatively-doped-source/drain metal-oxide-semiconductor static random-access memory cells. Data supports adoption of simplified worst-case model in which cross sectionof SEU by ion above threshold energy equals area of memory cell.

Zoutendyk, John A.↗
NASA NTRS1988

An exact, closed-form expression of the integral chord-length distribution for the calculation of single-event upsets induced by cosmic rays

This paper presents a derivation of an exact closed-form expression of the integral chord-length distribution for the calculation of single-event upsets (SEUs) in an electronic memory cell, caused by cosmic rays. Results computed for two rectangular parallelepipeds using this exact expression are compared with those computed with Bradford's (1979) semiexact expression of C(x). It is found that the values of C(x) are identical for x equal or smaller than b but are vastly different for x greater than b. Moreover, while C(x) of Bradford gives reasonably accurate values of SEU rate for certain sets of computational parameters, it gives values more than 10 times larger than the correct values for other sets of parameters.

Luke, Keung L.↗
NASA NTRS1986

The Galileo single-event upset solution and risk assessment

The Galileo probe will be subject to radiation fields and energetic particle bombardment during its outward bound journey and in orbit around Jupiter and its moons. To avoid the occurrence and propagation of effects of single event upset (SEU) bit state changes induced by the bombardments attempts were made to harden the Galileo electronics against SEUs. The hazards are especially acute for Schottky diode and low-power Schottky TTL parts. The preventive action options which were scheduled are reviewed, noting the selection of CMOS chips as replacements for SEU-susceptible devices. The simulation and risk assessment that were performed to evaluate the potential success of the replacements are summarized, with emphasis on the data employed to ensure the accuracy of the assessments and the predicted effects of SEUs in the various Galileo subsystems.

Burdick, Garry M.↗
NASA NTRS1991

Heavy-ion induced single-event upset in integrated circuits

The cosmic ray environment in space can affect the operation of Integrated Circuit (IC) devices via the phenomenon of Single Event Upset (SEU). In particular, heavy ions passing through an IC can induce sufficient integrated current (charge) to alter the state of a bistable circuit, for example a memory cell. The SEU effect is studied in great detail in both static and dynamic memory devices, as well as microprocessors fabricated from bipolar, Complementary Metal Oxide Semiconductor (CMOS) and N channel Metal Oxide Semiconductor (NMOS) technologies. Each device/process reflects its individual characteristics (minimum scale geometry/process parameters) via a unique response to the direct ionization of electron hole pairs by heavy ion tracks. A summary of these analytical and experimental SEU investigations is presented.

Zoutendyk, J. A.↗